Commit cc894b85 authored by Luca Coelho's avatar Luca Coelho

iwlwifi: pcie: always disable L0S states

L0S states have been found to be unstable with our devices and in
newer hardware they are not supported at all, so we must always set
the L0S_DISABLED bit.  Previously we were only disabling L0S states if
L1 was supported, because the assumption was that transitions from L0S
to L1 state was the problematic case.  But now we should never use
L0S, so do it regardless of whether L1 is supported or not.
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent 3d1b28fd
...@@ -302,18 +302,13 @@ void iwl_pcie_apm_config(struct iwl_trans *trans) ...@@ -302,18 +302,13 @@ void iwl_pcie_apm_config(struct iwl_trans *trans)
u16 cap; u16 cap;
/* /*
* HW bug W/A for instability in PCIe bus L0S->L1 transition. * L0S states have been found to be unstable with our devices
* Check if BIOS (or OS) enabled L1-ASPM on this device. * and in newer hardware they are not officially supported at
* If so (likely), disable L0S, so device moves directly L0->L1; * all, so we must always set the L0S_DISABLED bit.
* costs negligible amount of power savings.
* If not (unlikely), enable L0S, so there is at least some
* power savings, even without L1.
*/ */
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
else
iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
......
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