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Commit ccf9fc86 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/max9878', 'asoc/topic/max98927',... 

Merge remote-tracking branches 'asoc/topic/max9878', 'asoc/topic/max98927', 'asoc/topic/mtk' and 'asoc/topic/nau8540' into asoc-next
parents 50946b2a 56af0e4c 7c0c2000 362c5943 babd6585
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Documentation/devicetree/bindings/sound/max98925.txt deleted 100644 → 0
View file @ 50946b2a
max98925 audio CODEC
This device supports I2C.
Required properties:
- compatible : "maxim,max98925"
- vmon-slot-no : slot number used to send voltage information
- imon-slot-no : slot number used to send current information
- reg : the I2C address of the device for I2C
Example:
codec: max98925@1a {
compatible = "maxim,max98925";
vmon-slot-no = <0>;
imon-slot-no = <2>;
reg = <0x1a>;
};
Documentation/devicetree/bindings/sound/max98926.txt deleted 100644 → 0
View file @ 50946b2a
max98926 audio CODEC
This device supports I2C.
Required properties:
- compatible : "maxim,max98926"
- vmon-slot-no : slot number used to send voltage information
or in inteleave mode this will be used as
interleave slot.
- imon-slot-no : slot number used to send current information
- interleave-mode : When using two MAX98926 in a system it is
possible to create ADC data that that will
overflow the frame size. Digital Audio Interleave
mode provides a means to output VMON and IMON data
from two devices on a single DOUT line when running
smaller frames sizes such as 32 BCLKS per LRCLK or
48 BCLKS per LRCLK.
- reg : the I2C address of the device for I2C
Example:
codec: max98926@1a {
compatible = "maxim,max98926";
vmon-slot-no = <0>;
imon-slot-no = <2>;
reg = <0x1a>;
};
Documentation/devicetree/bindings/sound/max9892x.txt 0 → 100644
View file @ ccf9fc86
Maxim Integrated MAX98925/MAX98926/MAX98927 Speaker Amplifier
This device supports I2C.
Required properties:
- compatible : should be one of the following
- "maxim,max98925"
- "maxim,max98926"
- "maxim,max98927"
- vmon-slot-no : slot number used to send voltage information
or in inteleave mode this will be used as
interleave slot.
MAX98925/MAX98926 slot range : 0 ~ 30, Default : 0
MAX98927 slot range : 0 ~ 15, Default : 0
- imon-slot-no : slot number used to send current information
MAX98925/MAX98926 slot range : 0 ~ 30, Default : 0
MAX98927 slot range : 0 ~ 15, Default : 0
- interleave-mode : When using two MAX9892X in a system it is
possible to create ADC data that that will
overflow the frame size. Digital Audio Interleave
mode provides a means to output VMON and IMON data
from two devices on a single DOUT line when running
smaller frames sizes such as 32 BCLKS per LRCLK or
48 BCLKS per LRCLK.
Range : 0 (off), 1 (on), Default : 0
- reg : the I2C address of the device for I2C
Example:
codec: max98927@3a {
compatible = "maxim,max98927";
vmon-slot-no = <0>;
imon-slot-no = <1>;
interleave-mode = <0>;
reg = <0x3a>;
};
Documentation/devicetree/bindings/sound/mt2701-wm8960.txt 0 → 100644
View file @ ccf9fc86
MT2701 with WM8960 CODEC
Required properties:
- compatible: "mediatek,mt2701-wm8960-machine"
- mediatek,platform: the phandle of MT2701 ASoC platform
- audio-routing: a list of the connections between audio
- mediatek,audio-codec: the phandles of wm8960 codec
- pinctrl-names: Should contain only one value - "default"
- pinctrl-0: Should specify pin control groups used for this controller.
Example:
sound:sound {
compatible = "mediatek,mt2701-wm8960-machine";
mediatek,platform = <&afe>;
audio-routing =
"Headphone", "HP_L",
"Headphone", "HP_R",
"LINPUT1", "AMIC",
"RINPUT1", "AMIC";
mediatek,audio-codec = <&wm8960>;
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
};
sound/soc/codecs/Kconfig
View file @ ccf9fc86
......@@ -92,6 +92,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_MAX9867 if I2C
select SND_SOC_MAX98925 if I2C
select SND_SOC_MAX98926 if I2C
select SND_SOC_MAX98927 if I2C
select SND_SOC_MAX9850 if I2C
select SND_SOC_MAX9860 if I2C
select SND_SOC_MAX9768 if I2C
......@@ -604,6 +605,10 @@ config SND_SOC_MAX98925
config SND_SOC_MAX98926
tristate
config SND_SOC_MAX98927
tristate "Maxim Integrated MAX98927 Speaker Amplifier"
depends on I2C
config SND_SOC_MAX9850
tristate
......
sound/soc/codecs/Makefile
View file @ ccf9fc86
......@@ -86,6 +86,7 @@ snd-soc-max98371-objs := max98371.o
snd-soc-max9867-objs := max9867.o
snd-soc-max98925-objs := max98925.o
snd-soc-max98926-objs := max98926.o
snd-soc-max98927-objs := max98927.o
snd-soc-max9850-objs := max9850.o
snd-soc-max9860-objs := max9860.o
snd-soc-mc13783-objs := mc13783.o
......@@ -318,6 +319,7 @@ obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o
obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o
obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
obj-$(CONFIG_SND_SOC_MAX98927) += snd-soc-max98927.o
obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
......
sound/soc/codecs/max9867.c
View file @ ccf9fc86
......@@ -516,13 +516,13 @@ static const struct i2c_device_id max9867_i2c_id[] = {
{ "max9867", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9867_i2c_id);
static const struct of_device_id max9867_of_match[] = {
{ .compatible = "maxim,max9867", },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9867_i2c_id);
MODULE_DEVICE_TABLE(of, max9867_of_match);
static const struct dev_pm_ops max9867_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(max9867_suspend, max9867_resume)
......
sound/soc/codecs/max98927.c 0 → 100644
View file @ ccf9fc86
/*
* max98927.c -- MAX98927 ALSA Soc Audio driver
*
* Copyright (C) 2016 Maxim Integrated Products
* Author: Ryan Lee <ryans.lee@maximintegrated.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/tlv.h>
#include "max98927.h"
static struct reg_default max98927_reg[] = {
{MAX98927_R0001_INT_RAW1, 0x00},
{MAX98927_R0002_INT_RAW2, 0x00},
{MAX98927_R0003_INT_RAW3, 0x00},
{MAX98927_R0004_INT_STATE1, 0x00},
{MAX98927_R0005_INT_STATE2, 0x00},
{MAX98927_R0006_INT_STATE3, 0x00},
{MAX98927_R0007_INT_FLAG1, 0x00},
{MAX98927_R0008_INT_FLAG2, 0x00},
{MAX98927_R0009_INT_FLAG3, 0x00},
{MAX98927_R000A_INT_EN1, 0x00},
{MAX98927_R000B_INT_EN2, 0x00},
{MAX98927_R000C_INT_EN3, 0x00},
{MAX98927_R000D_INT_FLAG_CLR1, 0x00},
{MAX98927_R000E_INT_FLAG_CLR2, 0x00},
{MAX98927_R000F_INT_FLAG_CLR3, 0x00},
{MAX98927_R0010_IRQ_CTRL, 0x00},
{MAX98927_R0011_CLK_MON, 0x00},
{MAX98927_R0012_WDOG_CTRL, 0x00},
{MAX98927_R0013_WDOG_RST, 0x00},
{MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x00},
{MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x00},
{MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x00},
{MAX98927_R0017_PIN_CFG, 0x55},
{MAX98927_R0018_PCM_RX_EN_A, 0x00},
{MAX98927_R0019_PCM_RX_EN_B, 0x00},
{MAX98927_R001A_PCM_TX_EN_A, 0x00},
{MAX98927_R001B_PCM_TX_EN_B, 0x00},
{MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
{MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
{MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
{MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
{MAX98927_R0020_PCM_MODE_CFG, 0x40},
{MAX98927_R0021_PCM_MASTER_MODE, 0x00},
{MAX98927_R0022_PCM_CLK_SETUP, 0x22},
{MAX98927_R0023_PCM_SR_SETUP1, 0x00},
{MAX98927_R0024_PCM_SR_SETUP2, 0x00},
{MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
{MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
{MAX98927_R0027_ICC_RX_EN_A, 0x00},
{MAX98927_R0028_ICC_RX_EN_B, 0x00},
{MAX98927_R002B_ICC_TX_EN_A, 0x00},
{MAX98927_R002C_ICC_TX_EN_B, 0x00},
{MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
{MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
{MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
{MAX98927_R0031_ICC_LNK_EN, 0x00},
{MAX98927_R0032_PDM_TX_EN, 0x00},
{MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
{MAX98927_R0034_PDM_TX_CTRL, 0x00},
{MAX98927_R0035_PDM_RX_CTRL, 0x00},
{MAX98927_R0036_AMP_VOL_CTRL, 0x00},
{MAX98927_R0037_AMP_DSP_CFG, 0x02},
{MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
{MAX98927_R0039_DRE_CTRL, 0x01},
{MAX98927_R003A_AMP_EN, 0x00},
{MAX98927_R003B_SPK_SRC_SEL, 0x00},
{MAX98927_R003C_SPK_GAIN, 0x00},
{MAX98927_R003D_SSM_CFG, 0x01},
{MAX98927_R003E_MEAS_EN, 0x00},
{MAX98927_R003F_MEAS_DSP_CFG, 0x04},
{MAX98927_R0040_BOOST_CTRL0, 0x00},
{MAX98927_R0041_BOOST_CTRL3, 0x00},
{MAX98927_R0042_BOOST_CTRL1, 0x00},
{MAX98927_R0043_MEAS_ADC_CFG, 0x00},
{MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x00},
{MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
{MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
{MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
{MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
{MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
{MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
{MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
{MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
{MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
{MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
{MAX98927_R0051_BROWNOUT_STATUS, 0x00},
{MAX98927_R0052_BROWNOUT_EN, 0x00},
{MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
{MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
{MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
{MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
{MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
{MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
{MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
{MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
{MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
{MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
{MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
{MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
{MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
{MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
{MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
{MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
{MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
{MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
{MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
{MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
{MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
{MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
{MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
{MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
{MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
{MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
{MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
{MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
{MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
{MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
{MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
{MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
{MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
{MAX98927_R00FF_GLOBAL_SHDN, 0x00},
{MAX98927_R0100_SOFT_RESET, 0x00},
{MAX98927_R01FF_REV_ID, 0x40},
};
static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
unsigned int mode = 0;
unsigned int format = 0;
unsigned int invert = 0;
dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
mode = MAX98927_PCM_MASTER_MODE_SLAVE;
break;
case SND_SOC_DAIFMT_CBM_CFM:
max98927->master = true;
mode = MAX98927_PCM_MASTER_MODE_MASTER;
break;
default:
dev_err(codec->dev, "DAI clock mode unsupported");
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
MAX98927_R0021_PCM_MASTER_MODE,
MAX98927_PCM_MASTER_MODE_MASK,
mode);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(codec->dev, "DAI invert mode unsupported");
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
max98927->iface |= SND_SOC_DAIFMT_I2S;
format = MAX98927_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
max98927->iface |= SND_SOC_DAIFMT_LEFT_J;
format = MAX98927_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_PDM:
max98927->iface |= SND_SOC_DAIFMT_PDM;
break;
default:
return -EINVAL;
}
/* pcm channel configuration */
if (max98927->iface & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
regmap_update_bits(max98927->regmap,
MAX98927_R0018_PCM_RX_EN_A,
MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
regmap_update_bits(max98927->regmap,
MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
regmap_update_bits(max98927->regmap,
MAX98927_R003B_SPK_SRC_SEL,
MAX98927_SPK_SRC_MASK, 0);
} else
regmap_update_bits(max98927->regmap,
MAX98927_R0018_PCM_RX_EN_A,
MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
/* pdm channel configuration */
if (max98927->iface & SND_SOC_DAIFMT_PDM) {
regmap_update_bits(max98927->regmap,
MAX98927_R0035_PDM_RX_CTRL,
MAX98927_PDM_RX_EN_MASK, 1);
regmap_update_bits(max98927->regmap,
MAX98927_R003B_SPK_SRC_SEL,
MAX98927_SPK_SRC_MASK, 3);
} else
regmap_update_bits(max98927->regmap,
MAX98927_R0035_PDM_RX_CTRL,
MAX98927_PDM_RX_EN_MASK, 0);
return 0;
}
/* codec MCLK rate in master mode */
static const int rate_table[] = {
5644800, 6000000, 6144000, 6500000,
9600000, 11289600, 12000000, 12288000,
13000000, 19200000,
};
static int max98927_set_clock(struct max98927_priv *max98927,
struct snd_pcm_hw_params *params)
{
struct snd_soc_codec *codec = max98927->codec;
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98927->ch_size;
int value;
if (max98927->master) {
int i;
/* match rate to closest value */
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i] >= max98927->sysclk)
break;
}
if (i == ARRAY_SIZE(rate_table)) {
dev_err(codec->dev, "failed to find proper clock rate.\n");
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
MAX98927_R0021_PCM_MASTER_MODE,
MAX98927_PCM_MASTER_MODE_MCLK_MASK,
i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
}
switch (blr_clk_ratio) {
case 32:
value = 2;
break;
case 48:
value = 3;
break;
case 64:
value = 4;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
MAX98927_R0022_PCM_CLK_SETUP,
MAX98927_PCM_CLK_SETUP_BSEL_MASK,
value);
return 0;
}
static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(codec->dev, "format unsupported %d",
params_format(params));
goto err;
}
max98927->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98927->regmap,
MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(codec->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
break;
default:
dev_err(codec->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98927->regmap,
MAX98927_R0023_PCM_SR_SETUP1,
MAX98927_PCM_SR_SET1_SR_MASK,
sampling_rate);
regmap_update_bits(max98927->regmap,
MAX98927_R0024_PCM_SR_SETUP2,
MAX98927_PCM_SR_SET2_SR_MASK,
sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
if (max98927->interleave_mode &&
sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98927->regmap,
MAX98927_R0024_PCM_SR_SETUP2,
MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate - 3);
else
regmap_update_bits(max98927->regmap,
MAX98927_R0024_PCM_SR_SETUP2,
MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate);
return max98927_set_clock(max98927, params);
err:
return -EINVAL;
}
#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
max98927->sysclk = freq;
return 0;
}
static const struct snd_soc_dai_ops max98927_dai_ops = {
.set_sysclk = max98927_dai_set_sysclk,
.set_fmt = max98927_dai_set_fmt,
.hw_params = max98927_dai_hw_params,
};
static int max98927_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(max98927->regmap,
MAX98927_R003A_AMP_EN,
MAX98927_AMP_EN_MASK, 1);
/* enable VMON and IMON */
regmap_update_bits(max98927->regmap,
MAX98927_R003E_MEAS_EN,
MAX98927_MEAS_V_EN | MAX98927_MEAS_I_EN,
MAX98927_MEAS_V_EN | MAX98927_MEAS_I_EN);
regmap_update_bits(max98927->regmap,
MAX98927_R00FF_GLOBAL_SHDN,
MAX98927_GLOBAL_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(max98927->regmap,
MAX98927_R00FF_GLOBAL_SHDN,
MAX98927_GLOBAL_EN_MASK, 0);
regmap_update_bits(max98927->regmap,
MAX98927_R003A_AMP_EN,
MAX98927_AMP_EN_MASK, 0);
/* disable VMON and IMON */
regmap_update_bits(max98927->regmap,
MAX98927_R003E_MEAS_EN,
MAX98927_MEAS_V_EN | MAX98927_MEAS_I_EN, 0);
break;
default:
return 0;
}
return 0;
}
static const char * const max98927_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
3, max98927_switch_text);
static const struct snd_kcontrol_new max98927_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
0, 0, max98927_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98927_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
};
static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
static bool max98927_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
... MAX98927_R004E_MEAS_ADC_CH2_READ:
case MAX98927_R0051_BROWNOUT_STATUS
... MAX98927_R0055_BROWNOUT_LVL_HOLD:
case MAX98927_R005A_BROWNOUT_LVL1_THRESH
... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
case MAX98927_R00FF_GLOBAL_SHDN:
case MAX98927_R0100_SOFT_RESET:
case MAX98927_R01FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
return true;
default:
return false;
}
}
static const char * const max98927_boost_voltage_text[] = {
"6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
"7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
"8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
"9.5V", "9.625V", "9.75V", "9.875V", "10V"
};
static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
MAX98927_R0040_BOOST_CTRL0, 0,
max98927_boost_voltage_text);
static const char * const max98927_current_limit_text[] = {
"1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
"1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
"2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
"3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
};
static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
MAX98927_R0042_BOOST_CTRL1, 1,
max98927_current_limit_text);
static const struct snd_kcontrol_new max98927_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
0, 6, 0,
max98927_spk_tlv),
SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
max98927_digital_tlv),
SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
MAX98927_DRE_EN_SHIFT, 1, 0),
SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
SOC_ENUM("Current Limit", max98927_current_limit),
};
static const struct snd_soc_dapm_route max98927_audio_map[] = {
{"Amp Enable", NULL, "DAI_OUT"},
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
};
static struct snd_soc_dai_driver max98927_dai[] = {
{
.name = "max98927-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98927_RATES,
.formats = MAX98927_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98927_RATES,
.formats = MAX98927_FORMATS,
},
.ops = &max98927_dai_ops,
}
};
static int max98927_probe(struct snd_soc_codec *codec)
{
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
max98927->codec = codec;
codec->control_data = max98927->regmap;
codec->cache_bypass = 1;
/* Software Reset */
regmap_write(max98927->regmap,
MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
/* IV default slot configuration */
regmap_write(max98927->regmap,
MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
0xFF);
regmap_write(max98927->regmap,
MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
0xFF);
regmap_write(max98927->regmap,
MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
0x80);
regmap_write(max98927->regmap,
MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
0x1);
/* Set inital volume (+13dB) */
regmap_write(max98927->regmap,
MAX98927_R0036_AMP_VOL_CTRL,
0x38);
regmap_write(max98927->regmap,
MAX98927_R003C_SPK_GAIN,
0x05);
/* Enable DC blocker */
regmap_write(max98927->regmap,
MAX98927_R0037_AMP_DSP_CFG,
0x03);
/* Enable IMON VMON DC blocker */
regmap_write(max98927->regmap,
MAX98927_R003F_MEAS_DSP_CFG,
0xF7);
/* Boost Output Voltage & Current limit */
regmap_write(max98927->regmap,
MAX98927_R0040_BOOST_CTRL0,
0x1C);
regmap_write(max98927->regmap,
MAX98927_R0042_BOOST_CTRL1,
0x3E);
/* Measurement ADC config */
regmap_write(max98927->regmap,
MAX98927_R0043_MEAS_ADC_CFG,
0x04);
regmap_write(max98927->regmap,
MAX98927_R0044_MEAS_ADC_BASE_MSB,
0x00);
regmap_write(max98927->regmap,
MAX98927_R0045_MEAS_ADC_BASE_LSB,
0x24);
/* Brownout Level */
regmap_write(max98927->regmap,
MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
0x06);
/* Envelope Tracking configuration */
regmap_write(max98927->regmap,
MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
0x08);
regmap_write(max98927->regmap,
MAX98927_R0086_ENV_TRACK_CTRL,
0x01);
regmap_write(max98927->regmap,
MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
0x10);
/* voltage, current slot configuration */
regmap_write(max98927->regmap,
MAX98927_R001E_PCM_TX_CH_SRC_A,
(max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
max98927->v_l_slot)&0xFF);
if (max98927->v_l_slot < 8) {
regmap_update_bits(max98927->regmap,
MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
1 << max98927->v_l_slot, 0);
regmap_update_bits(max98927->regmap,
MAX98927_R001A_PCM_TX_EN_A,
1 << max98927->v_l_slot,
1 << max98927->v_l_slot);
} else {
regmap_update_bits(max98927->regmap,
MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
1 << (max98927->v_l_slot - 8), 0);
regmap_update_bits(max98927->regmap,
MAX98927_R001B_PCM_TX_EN_B,
1 << (max98927->v_l_slot - 8),
1 << (max98927->v_l_slot - 8));
}
if (max98927->i_l_slot < 8) {
regmap_update_bits(max98927->regmap,
MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
1 << max98927->i_l_slot, 0);
regmap_update_bits(max98927->regmap,
MAX98927_R001A_PCM_TX_EN_A,
1 << max98927->i_l_slot,
1 << max98927->i_l_slot);
} else {
regmap_update_bits(max98927->regmap,
MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
1 << (max98927->i_l_slot - 8), 0);
regmap_update_bits(max98927->regmap,
MAX98927_R001B_PCM_TX_EN_B,
1 << (max98927->i_l_slot - 8),
1 << (max98927->i_l_slot - 8));
}
/* Set interleave mode */
if (max98927->interleave_mode)
regmap_update_bits(max98927->regmap,
MAX98927_R001F_PCM_TX_CH_SRC_B,
MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
return 0;
}
static const struct snd_soc_codec_driver soc_codec_dev_max98927 = {
.probe = max98927_probe,
.component_driver = {
.controls = max98927_snd_controls,
.num_controls = ARRAY_SIZE(max98927_snd_controls),
.dapm_widgets = max98927_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
.dapm_routes = max98927_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
},
};
static const struct regmap_config max98927_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98927_R01FF_REV_ID,
.reg_defaults = max98927_reg,
.num_reg_defaults = ARRAY_SIZE(max98927_reg),
.readable_reg = max98927_readable_register,
.volatile_reg = max98927_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98927_slot_config(struct i2c_client *i2c,
struct max98927_priv *max98927)
{
int value;
if (!of_property_read_u32(i2c->dev.of_node,
"vmon-slot-no", &value))
max98927->v_l_slot = value & 0xF;
else
max98927->v_l_slot = 0;
if (!of_property_read_u32(i2c->dev.of_node,
"imon-slot-no", &value))
max98927->i_l_slot = value & 0xF;
else
max98927->i_l_slot = 1;
}
static int max98927_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
int ret = 0, value;
int reg = 0;
struct max98927_priv *max98927 = NULL;
max98927 = devm_kzalloc(&i2c->dev,
sizeof(*max98927), GFP_KERNEL);
if (!max98927) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98927);
/* update interleave mode info */
if (!of_property_read_u32(i2c->dev.of_node,
"interleave_mode", &value)) {
if (value > 0)
max98927->interleave_mode = 1;
else
max98927->interleave_mode = 0;
} else
max98927->interleave_mode = 0;
/* regmap initialization */
max98927->regmap
= devm_regmap_init_i2c(i2c, &max98927_regmap);
if (IS_ERR(max98927->regmap)) {
ret = PTR_ERR(max98927->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
/* Check Revision ID */
ret = regmap_read(max98927->regmap,
MAX98927_R01FF_REV_ID, &reg);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
/* voltage/current slot configuration */
max98927_slot_config(i2c, max98927);
/* codec registeration */
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98927,
max98927_dai, ARRAY_SIZE(max98927_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static int max98927_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id max98927_i2c_id[] = {
{ "max98927", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98927_of_match[] = {
{ .compatible = "maxim,max98927", },
{ }
};
MODULE_DEVICE_TABLE(of, max98927_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98927_acpi_match[] = {
{ "MX98927", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
#endif
static struct i2c_driver max98927_i2c_driver = {
.driver = {
.name = "max98927",
.of_match_table = of_match_ptr(max98927_of_match),
.acpi_match_table = ACPI_PTR(max98927_acpi_match),
.pm = NULL,
},
.probe = max98927_i2c_probe,
.remove = max98927_i2c_remove,
.id_table = max98927_i2c_id,
};
module_i2c_driver(max98927_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/max98927.h 0 → 100644
View file @ ccf9fc86
/*
* max98927.h -- MAX98927 ALSA Soc Audio driver
*
* Copyright 2013-15 Maxim Integrated Products
* Author: Ryan Lee <ryans.lee@maximintegrated.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _MAX98927_H
#define _MAX98927_H
/* Register Values */
#define MAX98927_R0001_INT_RAW1 0x0001
#define MAX98927_R0002_INT_RAW2 0x0002
#define MAX98927_R0003_INT_RAW3 0x0003
#define MAX98927_R0004_INT_STATE1 0x0004
#define MAX98927_R0005_INT_STATE2 0x0005
#define MAX98927_R0006_INT_STATE3 0x0006
#define MAX98927_R0007_INT_FLAG1 0x0007
#define MAX98927_R0008_INT_FLAG2 0x0008
#define MAX98927_R0009_INT_FLAG3 0x0009
#define MAX98927_R000A_INT_EN1 0x000A
#define MAX98927_R000B_INT_EN2 0x000B
#define MAX98927_R000C_INT_EN3 0x000C
#define MAX98927_R000D_INT_FLAG_CLR1 0x000D
#define MAX98927_R000E_INT_FLAG_CLR2 0x000E
#define MAX98927_R000F_INT_FLAG_CLR3 0x000F
#define MAX98927_R0010_IRQ_CTRL 0x0010
#define MAX98927_R0011_CLK_MON 0x0011
#define MAX98927_R0012_WDOG_CTRL 0x0012
#define MAX98927_R0013_WDOG_RST 0x0013
#define MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH 0x0014
#define MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH 0x0015
#define MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS 0x0016
#define MAX98927_R0017_PIN_CFG 0x0017
#define MAX98927_R0018_PCM_RX_EN_A 0x0018
#define MAX98927_R0019_PCM_RX_EN_B 0x0019
#define MAX98927_R001A_PCM_TX_EN_A 0x001A
#define MAX98927_R001B_PCM_TX_EN_B 0x001B
#define MAX98927_R001C_PCM_TX_HIZ_CTRL_A 0x001C
#define MAX98927_R001D_PCM_TX_HIZ_CTRL_B 0x001D
#define MAX98927_R001E_PCM_TX_CH_SRC_A 0x001E
#define MAX98927_R001F_PCM_TX_CH_SRC_B 0x001F
#define MAX98927_R0020_PCM_MODE_CFG 0x0020
#define MAX98927_R0021_PCM_MASTER_MODE 0x0021
#define MAX98927_R0022_PCM_CLK_SETUP 0x0022
#define MAX98927_R0023_PCM_SR_SETUP1 0x0023
#define MAX98927_R0024_PCM_SR_SETUP2 0x0024
#define MAX98927_R0025_PCM_TO_SPK_MONOMIX_A 0x0025
#define MAX98927_R0026_PCM_TO_SPK_MONOMIX_B 0x0026
#define MAX98927_R0027_ICC_RX_EN_A 0x0027
#define MAX98927_R0028_ICC_RX_EN_B 0x0028
#define MAX98927_R002B_ICC_TX_EN_A 0x002B
#define MAX98927_R002C_ICC_TX_EN_B 0x002C
#define MAX98927_R002E_ICC_HIZ_MANUAL_MODE 0x002E
#define MAX98927_R002F_ICC_TX_HIZ_EN_A 0x002F
#define MAX98927_R0030_ICC_TX_HIZ_EN_B 0x0030
#define MAX98927_R0031_ICC_LNK_EN 0x0031
#define MAX98927_R0032_PDM_TX_EN 0x0032
#define MAX98927_R0033_PDM_TX_HIZ_CTRL 0x0033
#define MAX98927_R0034_PDM_TX_CTRL 0x0034
#define MAX98927_R0035_PDM_RX_CTRL 0x0035
#define MAX98927_R0036_AMP_VOL_CTRL 0x0036
#define MAX98927_R0037_AMP_DSP_CFG 0x0037
#define MAX98927_R0038_TONE_GEN_DC_CFG 0x0038
#define MAX98927_R0039_DRE_CTRL 0x0039
#define MAX98927_R003A_AMP_EN 0x003A
#define MAX98927_R003B_SPK_SRC_SEL 0x003B
#define MAX98927_R003C_SPK_GAIN 0x003C
#define MAX98927_R003D_SSM_CFG 0x003D
#define MAX98927_R003E_MEAS_EN 0x003E
#define MAX98927_R003F_MEAS_DSP_CFG 0x003F
#define MAX98927_R0040_BOOST_CTRL0 0x0040
#define MAX98927_R0041_BOOST_CTRL3 0x0041
#define MAX98927_R0042_BOOST_CTRL1 0x0042
#define MAX98927_R0043_MEAS_ADC_CFG 0x0043
#define MAX98927_R0044_MEAS_ADC_BASE_MSB 0x0044
#define MAX98927_R0045_MEAS_ADC_BASE_LSB 0x0045
#define MAX98927_R0046_ADC_CH0_DIVIDE 0x0046
#define MAX98927_R0047_ADC_CH1_DIVIDE 0x0047
#define MAX98927_R0048_ADC_CH2_DIVIDE 0x0048
#define MAX98927_R0049_ADC_CH0_FILT_CFG 0x0049
#define MAX98927_R004A_ADC_CH1_FILT_CFG 0x004A
#define MAX98927_R004B_ADC_CH2_FILT_CFG 0x004B
#define MAX98927_R004C_MEAS_ADC_CH0_READ 0x004C
#define MAX98927_R004D_MEAS_ADC_CH1_READ 0x004D
#define MAX98927_R004E_MEAS_ADC_CH2_READ 0x004E
#define MAX98927_R0051_BROWNOUT_STATUS 0x0051
#define MAX98927_R0052_BROWNOUT_EN 0x0052
#define MAX98927_R0053_BROWNOUT_INFINITE_HOLD 0x0053
#define MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR 0x0054
#define MAX98927_R0055_BROWNOUT_LVL_HOLD 0x0055
#define MAX98927_R005A_BROWNOUT_LVL1_THRESH 0x005A
#define MAX98927_R005B_BROWNOUT_LVL2_THRESH 0x005B
#define MAX98927_R005C_BROWNOUT_LVL3_THRESH 0x005C
#define MAX98927_R005D_BROWNOUT_LVL4_THRESH 0x005D
#define MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS 0x005E
#define MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL 0x005F
#define MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL 0x0060
#define MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE 0x0061
#define MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 0x0072
#define MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1 0x0073
#define MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2 0x0074
#define MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3 0x0075
#define MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT 0x0076
#define MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1 0x0077
#define MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2 0x0078
#define MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3 0x0079
#define MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT 0x007A
#define MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1 0x007B
#define MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2 0x007C
#define MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3 0x007D
#define MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT 0x007E
#define MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1 0x007F
#define MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2 0x0080
#define MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3 0x0081
#define MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM 0x0082
#define MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY 0x0083
#define MAX98927_R0084_ENV_TRACK_REL_RATE 0x0084
#define MAX98927_R0085_ENV_TRACK_HOLD_RATE 0x0085
#define MAX98927_R0086_ENV_TRACK_CTRL 0x0086
#define MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ 0x0087
#define MAX98927_R00FF_GLOBAL_SHDN 0x00FF
#define MAX98927_R0100_SOFT_RESET 0x0100
#define MAX98927_R01FF_REV_ID 0x01FF
/* MAX98927_R0018_PCM_RX_EN_A */
#define MAX98927_PCM_RX_CH0_EN (0x1 << 0)
#define MAX98927_PCM_RX_CH1_EN (0x1 << 1)
#define MAX98927_PCM_RX_CH2_EN (0x1 << 2)
#define MAX98927_PCM_RX_CH3_EN (0x1 << 3)
#define MAX98927_PCM_RX_CH4_EN (0x1 << 4)
#define MAX98927_PCM_RX_CH5_EN (0x1 << 5)
#define MAX98927_PCM_RX_CH6_EN (0x1 << 6)
#define MAX98927_PCM_RX_CH7_EN (0x1 << 7)
/* MAX98927_R001A_PCM_TX_EN_A */
#define MAX98927_PCM_TX_CH0_EN (0x1 << 0)
#define MAX98927_PCM_TX_CH1_EN (0x1 << 1)
#define MAX98927_PCM_TX_CH2_EN (0x1 << 2)
#define MAX98927_PCM_TX_CH3_EN (0x1 << 3)
#define MAX98927_PCM_TX_CH4_EN (0x1 << 4)
#define MAX98927_PCM_TX_CH5_EN (0x1 << 5)
#define MAX98927_PCM_TX_CH6_EN (0x1 << 6)
#define MAX98927_PCM_TX_CH7_EN (0x1 << 7)
/* MAX98927_R001E_PCM_TX_CH_SRC_A */
#define MAX98927_PCM_TX_CH_SRC_A_V_SHIFT (0)
#define MAX98927_PCM_TX_CH_SRC_A_I_SHIFT (4)
/* MAX98927_R001F_PCM_TX_CH_SRC_B */
#define MAX98927_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 5)
/* MAX98927_R0020_PCM_MODE_CFG */
#define MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 2)
#define MAX98927_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
#define MAX98927_PCM_MODE_CFG_FORMAT_SHIFT (3)
#define MAX98927_PCM_FORMAT_I2S (0x0 << 0)
#define MAX98927_PCM_FORMAT_LJ (0x1 << 0)
#define MAX98927_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
#define MAX98927_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
#define MAX98927_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
#define MAX98927_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
/* MAX98927_R0021_PCM_MASTER_MODE */
#define MAX98927_PCM_MASTER_MODE_MASK (0x3 << 0)
#define MAX98927_PCM_MASTER_MODE_SLAVE (0x0 << 0)
#define MAX98927_PCM_MASTER_MODE_MASTER (0x3 << 0)
#define MAX98927_PCM_MASTER_MODE_MCLK_MASK (0xF << 2)
#define MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT (2)
/* MAX98927_R0022_PCM_CLK_SETUP */
#define MAX98927_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
/* MAX98927_R0023_PCM_SR_SETUP1 */
#define MAX98927_PCM_SR_SET1_SR_MASK (0xF << 0)
#define MAX98927_PCM_SR_SET1_SR_8000 (0x0 << 0)
#define MAX98927_PCM_SR_SET1_SR_11025 (0x1 << 0)
#define MAX98927_PCM_SR_SET1_SR_12000 (0x2 << 0)
#define MAX98927_PCM_SR_SET1_SR_16000 (0x3 << 0)
#define MAX98927_PCM_SR_SET1_SR_22050 (0x4 << 0)
#define MAX98927_PCM_SR_SET1_SR_24000 (0x5 << 0)
#define MAX98927_PCM_SR_SET1_SR_32000 (0x6 << 0)
#define MAX98927_PCM_SR_SET1_SR_44100 (0x7 << 0)
#define MAX98927_PCM_SR_SET1_SR_48000 (0x8 << 0)
/* MAX98927_R0024_PCM_SR_SETUP2 */
#define MAX98927_PCM_SR_SET2_SR_MASK (0xF << 4)
#define MAX98927_PCM_SR_SET2_SR_SHIFT (4)
#define MAX98927_PCM_SR_SET2_IVADC_SR_MASK (0xf << 0)
/* MAX98927_R0025_PCM_TO_SPK_MONOMIX_A */
#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
/* MAX98927_R0035_PDM_RX_CTRL */
#define MAX98927_PDM_RX_EN_MASK (0x1 << 0)
/* MAX98927_R0036_AMP_VOL_CTRL */
#define MAX98927_AMP_VOL_SEL (0x1 << 7)
#define MAX98927_AMP_VOL_SEL_WIDTH (1)
#define MAX98927_AMP_VOL_SEL_SHIFT (7)
#define MAX98927_AMP_VOL_MASK (0x7f << 0)
#define MAX98927_AMP_VOL_WIDTH (7)
#define MAX98927_AMP_VOL_SHIFT (0)
/* MAX98927_R0037_AMP_DSP_CFG */
#define MAX98927_AMP_DSP_CFG_DCBLK_EN (0x1 << 0)
#define MAX98927_AMP_DSP_CFG_DITH_EN (0x1 << 1)
#define MAX98927_AMP_DSP_CFG_RMP_BYPASS (0x1 << 4)
#define MAX98927_AMP_DSP_CFG_DAC_INV (0x1 << 5)
#define MAX98927_AMP_DSP_CFG_RMP_SHIFT (4)
/* MAX98927_R0039_DRE_CTRL */
#define MAX98927_DRE_CTRL_DRE_EN (0x1 << 0)
#define MAX98927_DRE_EN_SHIFT 0x1
/* MAX98927_R003A_AMP_EN */
#define MAX98927_AMP_EN_MASK (0x1 << 0)
/* MAX98927_R003B_SPK_SRC_SEL */
#define MAX98927_SPK_SRC_MASK (0x3 << 0)
/* MAX98927_R003C_SPK_GAIN */
#define MAX98927_SPK_PCM_GAIN_MASK (0x7 << 0)
#define MAX98927_SPK_PDM_GAIN_MASK (0x7 << 4)
#define MAX98927_SPK_GAIN_WIDTH (3)
/* MAX98927_R003E_MEAS_EN */
#define MAX98927_MEAS_V_EN (0x1 << 0)
#define MAX98927_MEAS_I_EN (0x1 << 1)
/* MAX98927_R0040_BOOST_CTRL0 */
#define MAX98927_BOOST_CTRL0_VOUT_MASK (0x1f << 0)
#define MAX98927_BOOST_CTRL0_PVDD_MASK (0x1 << 7)
#define MAX98927_BOOST_CTRL0_PVDD_EN_SHIFT (7)
/* MAX98927_R0052_BROWNOUT_EN */
#define MAX98927_BROWNOUT_BDE_EN (0x1 << 0)
#define MAX98927_BROWNOUT_AMP_EN (0x1 << 1)
#define MAX98927_BROWNOUT_DSP_EN (0x1 << 2)
#define MAX98927_BROWNOUT_DSP_SHIFT (2)
/* MAX98927_R0100_SOFT_RESET */
#define MAX98927_SOFT_RESET (0x1 << 0)
/* MAX98927_R00FF_GLOBAL_SHDN */
#define MAX98927_GLOBAL_EN_MASK (0x1 << 0)
struct max98927_priv {
struct regmap *regmap;
struct snd_soc_codec *codec;
struct max98927_pdata *pdata;
unsigned int spk_gain;
unsigned int sysclk;
unsigned int v_l_slot;
unsigned int i_l_slot;
bool interleave_mode;
unsigned int ch_size;
unsigned int rate;
unsigned int iface;
unsigned int master;
unsigned int digital_gain;
};
#endif
sound/soc/codecs/nau8540.c
View file @ ccf9fc86
......@@ -39,147 +39,147 @@
/* scaling for mclk from sysclk_src output */
static const struct nau8540_fll_attr mclk_src_scaling[] = {
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
};
/* ratio for input clk freq */
static const struct nau8540_fll_attr fll_ratio[] = {
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
};
static const struct nau8540_fll_attr fll_pre_scalar[] = {
{ 1, 0x0 },
{ 2, 0x1 },
{ 4, 0x2 },
{ 8, 0x3 },
{ 1, 0x0 },
{ 2, 0x1 },
{ 4, 0x2 },
{ 8, 0x3 },
};
/* over sampling rate */
static const struct nau8540_osr_attr osr_adc_sel[] = {
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
};
static const struct reg_default nau8540_reg_defaults[] = {
{NAU8540_REG_POWER_MANAGEMENT, 0x0000},
{NAU8540_REG_CLOCK_CTRL, 0x0000},
{NAU8540_REG_CLOCK_SRC, 0x0000},
{NAU8540_REG_FLL1, 0x0001},
{NAU8540_REG_FLL2, 0x3126},
{NAU8540_REG_FLL3, 0x0008},
{NAU8540_REG_FLL4, 0x0010},
{NAU8540_REG_FLL5, 0xC000},
{NAU8540_REG_FLL6, 0x6000},
{NAU8540_REG_FLL_VCO_RSV, 0xF13C},
{NAU8540_REG_PCM_CTRL0, 0x000B},
{NAU8540_REG_PCM_CTRL1, 0x3010},
{NAU8540_REG_PCM_CTRL2, 0x0800},
{NAU8540_REG_PCM_CTRL3, 0x0000},
{NAU8540_REG_PCM_CTRL4, 0x000F},
{NAU8540_REG_ALC_CONTROL_1, 0x0000},
{NAU8540_REG_ALC_CONTROL_2, 0x700B},
{NAU8540_REG_ALC_CONTROL_3, 0x0022},
{NAU8540_REG_ALC_CONTROL_4, 0x1010},
{NAU8540_REG_ALC_CONTROL_5, 0x1010},
{NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
{NAU8540_REG_HPF_FILTER_CH12, 0x0000},
{NAU8540_REG_HPF_FILTER_CH34, 0x0000},
{NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
{NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
{NAU8540_REG_DIGITAL_MUX, 0x00E4},
{NAU8540_REG_GPIO_CTRL, 0x0000},
{NAU8540_REG_MISC_CTRL, 0x0000},
{NAU8540_REG_I2C_CTRL, 0xEFFF},
{NAU8540_REG_VMID_CTRL, 0x0000},
{NAU8540_REG_MUTE, 0x0000},
{NAU8540_REG_ANALOG_ADC1, 0x0011},
{NAU8540_REG_ANALOG_ADC2, 0x0020},
{NAU8540_REG_ANALOG_PWR, 0x0000},
{NAU8540_REG_MIC_BIAS, 0x0004},
{NAU8540_REG_REFERENCE, 0x0000},
{NAU8540_REG_FEPGA1, 0x0000},
{NAU8540_REG_FEPGA2, 0x0000},
{NAU8540_REG_FEPGA3, 0x0101},
{NAU8540_REG_FEPGA4, 0x0101},
{NAU8540_REG_PWR, 0x0000},
{NAU8540_REG_POWER_MANAGEMENT, 0x0000},
{NAU8540_REG_CLOCK_CTRL, 0x0000},
{NAU8540_REG_CLOCK_SRC, 0x0000},
{NAU8540_REG_FLL1, 0x0001},
{NAU8540_REG_FLL2, 0x3126},
{NAU8540_REG_FLL3, 0x0008},
{NAU8540_REG_FLL4, 0x0010},
{NAU8540_REG_FLL5, 0xC000},
{NAU8540_REG_FLL6, 0x6000},
{NAU8540_REG_FLL_VCO_RSV, 0xF13C},
{NAU8540_REG_PCM_CTRL0, 0x000B},
{NAU8540_REG_PCM_CTRL1, 0x3010},
{NAU8540_REG_PCM_CTRL2, 0x0800},
{NAU8540_REG_PCM_CTRL3, 0x0000},
{NAU8540_REG_PCM_CTRL4, 0x000F},
{NAU8540_REG_ALC_CONTROL_1, 0x0000},
{NAU8540_REG_ALC_CONTROL_2, 0x700B},
{NAU8540_REG_ALC_CONTROL_3, 0x0022},
{NAU8540_REG_ALC_CONTROL_4, 0x1010},
{NAU8540_REG_ALC_CONTROL_5, 0x1010},
{NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
{NAU8540_REG_HPF_FILTER_CH12, 0x0000},
{NAU8540_REG_HPF_FILTER_CH34, 0x0000},
{NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
{NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
{NAU8540_REG_DIGITAL_MUX, 0x00E4},
{NAU8540_REG_GPIO_CTRL, 0x0000},
{NAU8540_REG_MISC_CTRL, 0x0000},
{NAU8540_REG_I2C_CTRL, 0xEFFF},
{NAU8540_REG_VMID_CTRL, 0x0000},
{NAU8540_REG_MUTE, 0x0000},
{NAU8540_REG_ANALOG_ADC1, 0x0011},
{NAU8540_REG_ANALOG_ADC2, 0x0020},
{NAU8540_REG_ANALOG_PWR, 0x0000},
{NAU8540_REG_MIC_BIAS, 0x0004},
{NAU8540_REG_REFERENCE, 0x0000},
{NAU8540_REG_FEPGA1, 0x0000},
{NAU8540_REG_FEPGA2, 0x0000},
{NAU8540_REG_FEPGA3, 0x0101},
{NAU8540_REG_FEPGA4, 0x0101},
{NAU8540_REG_PWR, 0x0000},
};
static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
case NAU8540_REG_I2C_DEVICE_ID:
case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
return true;
default:
return false;
}
switch (reg) {
case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
case NAU8540_REG_I2C_DEVICE_ID:
case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
return true;
default:
return false;
}
}
static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
case NAU8540_REG_RST:
case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
return true;
default:
return false;
}
switch (reg) {
case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
case NAU8540_REG_RST:
case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
return true;
default:
return false;
}
}
static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8540_REG_SW_RESET:
case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
case NAU8540_REG_I2C_DEVICE_ID:
case NAU8540_REG_RST:
return true;
default:
return false;
}
switch (reg) {
case NAU8540_REG_SW_RESET:
case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
case NAU8540_REG_I2C_DEVICE_ID:
case NAU8540_REG_RST:
return true;
default:
return false;
}
}
......@@ -187,255 +187,255 @@ static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
static const struct snd_kcontrol_new nau8540_snd_controls[] = {
SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
0, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
8, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
0, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
8, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
0, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
8, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
0, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
8, 0x25, 0, fepga_gain_tlv),
};
static const char * const adc_channel[] = {
"ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
"ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
};
static SOC_ENUM_SINGLE_DECL(
digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
static const struct snd_kcontrol_new digital_ch4_mux =
SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
static SOC_ENUM_SINGLE_DECL(
digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
static const struct snd_kcontrol_new digital_ch3_mux =
SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
static SOC_ENUM_SINGLE_DECL(
digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
static const struct snd_kcontrol_new digital_ch2_mux =
SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
static SOC_ENUM_SINGLE_DECL(
digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
static const struct snd_kcontrol_new digital_ch1_mux =
SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("MIC4"),
SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC1", NULL,
NAU8540_REG_POWER_MANAGEMENT, 0, 0),
SND_SOC_DAPM_ADC("ADC2", NULL,
NAU8540_REG_POWER_MANAGEMENT, 1, 0),
SND_SOC_DAPM_ADC("ADC3", NULL,
NAU8540_REG_POWER_MANAGEMENT, 2, 0),
SND_SOC_DAPM_ADC("ADC4", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0),
SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
SND_SOC_DAPM_MUX("Digital CH4 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
SND_SOC_DAPM_MUX("Digital CH3 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
SND_SOC_DAPM_MUX("Digital CH2 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
SND_SOC_DAPM_MUX("Digital CH1 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("MIC4"),
SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC1", NULL,
NAU8540_REG_POWER_MANAGEMENT, 0, 0),
SND_SOC_DAPM_ADC("ADC2", NULL,
NAU8540_REG_POWER_MANAGEMENT, 1, 0),
SND_SOC_DAPM_ADC("ADC3", NULL,
NAU8540_REG_POWER_MANAGEMENT, 2, 0),
SND_SOC_DAPM_ADC("ADC4", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0),
SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
SND_SOC_DAPM_MUX("Digital CH4 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
SND_SOC_DAPM_MUX("Digital CH3 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
SND_SOC_DAPM_MUX("Digital CH2 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
SND_SOC_DAPM_MUX("Digital CH1 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
{"Frontend PGA1", NULL, "MIC1"},
{"Frontend PGA2", NULL, "MIC2"},
{"Frontend PGA3", NULL, "MIC3"},
{"Frontend PGA4", NULL, "MIC4"},
{"ADC1", NULL, "Frontend PGA1"},
{"ADC2", NULL, "Frontend PGA2"},
{"ADC3", NULL, "Frontend PGA3"},
{"ADC4", NULL, "Frontend PGA4"},
{"ADC CH1", NULL, "ADC1"},
{"ADC CH2", NULL, "ADC2"},
{"ADC CH3", NULL, "ADC3"},
{"ADC CH4", NULL, "ADC4"},
{"ADC1", NULL, "MICBIAS1"},
{"ADC2", NULL, "MICBIAS1"},
{"ADC3", NULL, "MICBIAS2"},
{"ADC4", NULL, "MICBIAS2"},
{"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
{"AIFTX", NULL, "Digital CH1 Mux"},
{"AIFTX", NULL, "Digital CH2 Mux"},
{"AIFTX", NULL, "Digital CH3 Mux"},
{"AIFTX", NULL, "Digital CH4 Mux"},
{"Frontend PGA1", NULL, "MIC1"},
{"Frontend PGA2", NULL, "MIC2"},
{"Frontend PGA3", NULL, "MIC3"},
{"Frontend PGA4", NULL, "MIC4"},
{"ADC1", NULL, "Frontend PGA1"},
{"ADC2", NULL, "Frontend PGA2"},
{"ADC3", NULL, "Frontend PGA3"},
{"ADC4", NULL, "Frontend PGA4"},
{"ADC CH1", NULL, "ADC1"},
{"ADC CH2", NULL, "ADC2"},
{"ADC CH3", NULL, "ADC3"},
{"ADC CH4", NULL, "ADC4"},
{"ADC1", NULL, "MICBIAS1"},
{"ADC2", NULL, "MICBIAS1"},
{"ADC3", NULL, "MICBIAS2"},
{"ADC4", NULL, "MICBIAS2"},
{"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
{"AIFTX", NULL, "Digital CH1 Mux"},
{"AIFTX", NULL, "Digital CH2 Mux"},
{"AIFTX", NULL, "Digital CH3 Mux"},
{"AIFTX", NULL, "Digital CH4 Mux"},
};
static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr)
{
int osrate;
int osrate;
if (osr >= ARRAY_SIZE(osr_adc_sel))
return -EINVAL;
osrate = osr_adc_sel[osr].osr;
if (osr >= ARRAY_SIZE(osr_adc_sel))
return -EINVAL;
osrate = osr_adc_sel[osr].osr;
if (rate * osr > CLK_ADC_MAX) {
dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
return -EINVAL;
}
if (rate * osr > CLK_ADC_MAX) {
dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
return -EINVAL;
}
return 0;
return 0;
}
static int nau8540_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
unsigned int val_len = 0, osr;
/* CLK_ADC = OSR * FS
* ADC clock frequency is defined as Over Sampling Rate (OSR)
* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
* values must be selected such that the maximum frequency is less
* than 6.144 MHz.
*/
regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
osr &= NAU8540_ADC_OSR_MASK;
if (nau8540_clock_check(nau8540, params_rate(params), osr))
return -EINVAL;
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_ADC_SRC_MASK,
osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT);
switch (params_width(params)) {
case 16:
val_len |= NAU8540_I2S_DL_16;
break;
case 20:
val_len |= NAU8540_I2S_DL_20;
break;
case 24:
val_len |= NAU8540_I2S_DL_24;
break;
case 32:
val_len |= NAU8540_I2S_DL_32;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
NAU8540_I2S_DL_MASK, val_len);
return 0;
struct snd_soc_codec *codec = dai->codec;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
unsigned int val_len = 0, osr;
/* CLK_ADC = OSR * FS
* ADC clock frequency is defined as Over Sampling Rate (OSR)
* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
* values must be selected such that the maximum frequency is less
* than 6.144 MHz.
*/
regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
osr &= NAU8540_ADC_OSR_MASK;
if (nau8540_clock_check(nau8540, params_rate(params), osr))
return -EINVAL;
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_ADC_SRC_MASK,
osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT);
switch (params_width(params)) {
case 16:
val_len |= NAU8540_I2S_DL_16;
break;
case 20:
val_len |= NAU8540_I2S_DL_20;
break;
case 24:
val_len |= NAU8540_I2S_DL_24;
break;
case 32:
val_len |= NAU8540_I2S_DL_32;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
NAU8540_I2S_DL_MASK, val_len);
return 0;
}
static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
unsigned int ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= NAU8540_I2S_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8540_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8540_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8540_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1_val |= NAU8540_I2S_DF_RIGTH;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
ctrl1_val |= NAU8540_I2S_PCMB_EN;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_OE, 0);
return 0;
struct snd_soc_codec *codec = dai->codec;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
unsigned int ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= NAU8540_I2S_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8540_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8540_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8540_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1_val |= NAU8540_I2S_DF_RIGTH;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
ctrl1_val |= NAU8540_I2S_PCMB_EN;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_OE, 0);
return 0;
}
/**
......@@ -451,55 +451,55 @@ static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
* Configures a DAI for TDM operation. Only support 4 slots TDM.
*/
static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_codec *codec = dai->codec;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
unsigned int ctrl2_val = 0, ctrl4_val = 0;
if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
return -EINVAL;
ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
if (tx_mask & 0xf0) {
ctrl2_val = 4 * slot_width;
ctrl4_val |= (tx_mask >> 4);
} else {
ctrl4_val |= tx_mask;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
NAU8540_TDM_TX_MASK, ctrl4_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
NAU8540_I2S_DO34_OE | ctrl2_val);
return 0;
struct snd_soc_codec *codec = dai->codec;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
unsigned int ctrl2_val = 0, ctrl4_val = 0;
if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
return -EINVAL;
ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
if (tx_mask & 0xf0) {
ctrl2_val = 4 * slot_width;
ctrl4_val |= (tx_mask >> 4);
} else {
ctrl4_val |= tx_mask;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
NAU8540_TDM_TX_MASK, ctrl4_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
NAU8540_I2S_DO34_OE | ctrl2_val);
return 0;
}
static const struct snd_soc_dai_ops nau8540_dai_ops = {
.hw_params = nau8540_hw_params,
.set_fmt = nau8540_set_fmt,
.set_tdm_slot = nau8540_set_tdm_slot,
.hw_params = nau8540_hw_params,
.set_fmt = nau8540_set_fmt,
.set_tdm_slot = nau8540_set_tdm_slot,
};
#define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
#define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver nau8540_dai = {
.name = "nau8540-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = NAU8540_RATES,
.formats = NAU8540_FORMATS,
},
.ops = &nau8540_dai_ops,
.name = "nau8540-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = NAU8540_RATES,
.formats = NAU8540_FORMATS,
},
.ops = &nau8540_dai_ops,
};
/**
......@@ -513,320 +513,320 @@ static struct snd_soc_dai_driver nau8540_dai = {
* Returns 0 for success or negative error code.
*/
static int nau8540_calc_fll_param(unsigned int fll_in,
unsigned int fs, struct nau8540_fll *fll_param)
unsigned int fs, struct nau8540_fll *fll_param)
{
u64 fvco, fvco_max;
unsigned int fref, i, fvco_sel;
/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
* freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
* FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
*/
for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
fref = fll_in / fll_pre_scalar[i].param;
if (fref <= NAU_FREF_MAX)
break;
}
if (i == ARRAY_SIZE(fll_pre_scalar))
return -EINVAL;
fll_param->clk_ref_div = fll_pre_scalar[i].val;
/* Choose the FLL ratio based on FREF */
for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
if (fref >= fll_ratio[i].param)
break;
}
if (i == ARRAY_SIZE(fll_ratio))
return -EINVAL;
fll_param->ratio = fll_ratio[i].val;
/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
* FDCO must be within the 90MHz - 124MHz or the FFL cannot be
* guaranteed across the full range of operation.
* FDCO = freq_out * 2 * mclk_src_scaling
*/
fvco_max = 0;
fvco_sel = ARRAY_SIZE(mclk_src_scaling);
for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
fvco_max < fvco) {
fvco_max = fvco;
fvco_sel = i;
}
}
if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
return -EINVAL;
fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
* input based on FDCO, FREF and FLL ratio.
*/
fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
fll_param->fll_int = (fvco >> 16) & 0x3FF;
fll_param->fll_frac = fvco & 0xFFFF;
return 0;
u64 fvco, fvco_max;
unsigned int fref, i, fvco_sel;
/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
* freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
* FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
*/
for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
fref = fll_in / fll_pre_scalar[i].param;
if (fref <= NAU_FREF_MAX)
break;
}
if (i == ARRAY_SIZE(fll_pre_scalar))
return -EINVAL;
fll_param->clk_ref_div = fll_pre_scalar[i].val;
/* Choose the FLL ratio based on FREF */
for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
if (fref >= fll_ratio[i].param)
break;
}
if (i == ARRAY_SIZE(fll_ratio))
return -EINVAL;
fll_param->ratio = fll_ratio[i].val;
/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
* FDCO must be within the 90MHz - 124MHz or the FFL cannot be
* guaranteed across the full range of operation.
* FDCO = freq_out * 2 * mclk_src_scaling
*/
fvco_max = 0;
fvco_sel = ARRAY_SIZE(mclk_src_scaling);
for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
fvco_max < fvco) {
fvco_max = fvco;
fvco_sel = i;
}
}
if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
return -EINVAL;
fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
* input based on FDCO, FREF and FLL ratio.
*/
fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
fll_param->fll_int = (fvco >> 16) & 0x3FF;
fll_param->fll_frac = fvco & 0xFFFF;
return 0;
}
static void nau8540_fll_apply(struct regmap *regmap,
struct nau8540_fll *fll_param)
struct nau8540_fll *fll_param)
{
regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
regmap_update_bits(regmap, NAU8540_REG_FLL1,
NAU8540_FLL_RATIO_MASK, fll_param->ratio);
/* FLL 16-bit fractional input */
regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
/* FLL 10-bit integer input */
regmap_update_bits(regmap, NAU8540_REG_FLL3,
NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
/* FLL pre-scaler */
regmap_update_bits(regmap, NAU8540_REG_FLL4,
NAU8540_FLL_REF_DIV_MASK,
fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
regmap_update_bits(regmap,
NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
if (fll_param->fll_frac) {
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_SDM_EN, NAU8540_SDM_EN);
} else {
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap,
NAU8540_REG_FLL6, NAU8540_SDM_EN, 0);
}
regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
regmap_update_bits(regmap, NAU8540_REG_FLL1,
NAU8540_FLL_RATIO_MASK, fll_param->ratio);
/* FLL 16-bit fractional input */
regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
/* FLL 10-bit integer input */
regmap_update_bits(regmap, NAU8540_REG_FLL3,
NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
/* FLL pre-scaler */
regmap_update_bits(regmap, NAU8540_REG_FLL4,
NAU8540_FLL_REF_DIV_MASK,
fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
regmap_update_bits(regmap,
NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
if (fll_param->fll_frac) {
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_SDM_EN, NAU8540_SDM_EN);
} else {
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap,
NAU8540_REG_FLL6, NAU8540_SDM_EN, 0);
}
}
/* freq_out must be 256*Fs in order to achieve the best performance */
static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
unsigned int freq_in, unsigned int freq_out)
{
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
struct nau8540_fll fll_param;
int ret, fs;
switch (pll_id) {
case NAU8540_CLK_FLL_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK);
break;
case NAU8540_CLK_FLL_BLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK);
break;
case NAU8540_CLK_FLL_FS:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS);
break;
default:
dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
return -EINVAL;
}
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
freq_out, pll_id);
fs = freq_out / 256;
ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
if (ret < 0) {
dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
fll_param.fll_int, fll_param.clk_ref_div);
nau8540_fll_apply(nau8540->regmap, &fll_param);
mdelay(2);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
return 0;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
struct nau8540_fll fll_param;
int ret, fs;
switch (pll_id) {
case NAU8540_CLK_FLL_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK);
break;
case NAU8540_CLK_FLL_BLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK);
break;
case NAU8540_CLK_FLL_FS:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS);
break;
default:
dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
return -EINVAL;
}
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
freq_out, pll_id);
fs = freq_out / 256;
ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
if (ret < 0) {
dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
fll_param.fll_int, fll_param.clk_ref_div);
nau8540_fll_apply(nau8540->regmap, &fll_param);
mdelay(2);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
return 0;
}
static int nau8540_set_sysclk(struct snd_soc_codec *codec,
int clk_id, int source, unsigned int freq, int dir)
int clk_id, int source, unsigned int freq, int dir)
{
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
switch (clk_id) {
case NAU8540_CLK_DIS:
case NAU8540_CLK_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
NAU8540_DCO_EN, 0);
break;
case NAU8540_CLK_INTERNAL:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
NAU8540_DCO_EN, NAU8540_DCO_EN);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
break;
default:
dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
switch (clk_id) {
case NAU8540_CLK_DIS:
case NAU8540_CLK_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
NAU8540_DCO_EN, 0);
break;
case NAU8540_CLK_INTERNAL:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
NAU8540_DCO_EN, NAU8540_DCO_EN);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
break;
default:
dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static void nau8540_reset_chip(struct regmap *regmap)
{
regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
}
static void nau8540_init_regs(struct nau8540 *nau8540)
{
struct regmap *regmap = nau8540->regmap;
/* Enable Bias/VMID/VMID Tieoff */
regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
mdelay(2);
regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
NAU8540_PU_PRE, NAU8540_PU_PRE);
regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
/* ADC OSR selection, CLK_ADC = Fs * OSR */
regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
NAU8540_ADC_OSR_MASK, NAU8540_ADC_OSR_64);
struct regmap *regmap = nau8540->regmap;
/* Enable Bias/VMID/VMID Tieoff */
regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
mdelay(2);
regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
NAU8540_PU_PRE, NAU8540_PU_PRE);
regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
/* ADC OSR selection, CLK_ADC = Fs * OSR */
regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
NAU8540_ADC_OSR_MASK, NAU8540_ADC_OSR_64);
}
static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec)
{
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
regcache_cache_only(nau8540->regmap, true);
regcache_mark_dirty(nau8540->regmap);
regcache_cache_only(nau8540->regmap, true);
regcache_mark_dirty(nau8540->regmap);
return 0;
return 0;
}
static int __maybe_unused nau8540_resume(struct snd_soc_codec *codec)
{
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
regcache_cache_only(nau8540->regmap, false);
regcache_sync(nau8540->regmap);
regcache_cache_only(nau8540->regmap, false);
regcache_sync(nau8540->regmap);
return 0;
return 0;
}
static struct snd_soc_codec_driver nau8540_codec_driver = {
.set_sysclk = nau8540_set_sysclk,
.set_pll = nau8540_set_pll,
.suspend = nau8540_suspend,
.resume = nau8540_resume,
.suspend_bias_off = true,
.component_driver = {
.controls = nau8540_snd_controls,
.num_controls = ARRAY_SIZE(nau8540_snd_controls),
.dapm_widgets = nau8540_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets),
.dapm_routes = nau8540_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes),
},
.set_sysclk = nau8540_set_sysclk,
.set_pll = nau8540_set_pll,
.suspend = nau8540_suspend,
.resume = nau8540_resume,
.suspend_bias_off = true,
.component_driver = {
.controls = nau8540_snd_controls,
.num_controls = ARRAY_SIZE(nau8540_snd_controls),
.dapm_widgets = nau8540_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets),
.dapm_routes = nau8540_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes),
},
};
static const struct regmap_config nau8540_regmap_config = {
.val_bits = 16,
.reg_bits = 16,
.val_bits = 16,
.reg_bits = 16,
.max_register = NAU8540_REG_MAX,
.readable_reg = nau8540_readable_reg,
.writeable_reg = nau8540_writeable_reg,
.volatile_reg = nau8540_volatile_reg,
.max_register = NAU8540_REG_MAX,
.readable_reg = nau8540_readable_reg,
.writeable_reg = nau8540_writeable_reg,
.volatile_reg = nau8540_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8540_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8540_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
};
static int nau8540_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
const struct i2c_device_id *id)
{
struct device *dev = &i2c->dev;
struct nau8540 *nau8540 = dev_get_platdata(dev);
int ret, value;
if (!nau8540) {
nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
if (!nau8540)
return -ENOMEM;
}
i2c_set_clientdata(i2c, nau8540);
nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
if (IS_ERR(nau8540->regmap))
return PTR_ERR(nau8540->regmap);
ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
if (ret < 0) {
dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
ret);
return ret;
}
nau8540->dev = dev;
nau8540_reset_chip(nau8540->regmap);
nau8540_init_regs(nau8540);
return snd_soc_register_codec(dev,
&nau8540_codec_driver, &nau8540_dai, 1);
struct device *dev = &i2c->dev;
struct nau8540 *nau8540 = dev_get_platdata(dev);
int ret, value;
if (!nau8540) {
nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
if (!nau8540)
return -ENOMEM;
}
i2c_set_clientdata(i2c, nau8540);
nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
if (IS_ERR(nau8540->regmap))
return PTR_ERR(nau8540->regmap);
ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
if (ret < 0) {
dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
ret);
return ret;
}
nau8540->dev = dev;
nau8540_reset_chip(nau8540->regmap);
nau8540_init_regs(nau8540);
return snd_soc_register_codec(dev,
&nau8540_codec_driver, &nau8540_dai, 1);
}
static int nau8540_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id nau8540_i2c_ids[] = {
{ "nau8540", 0 },
{ }
{ "nau8540", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id nau8540_of_ids[] = {
{ .compatible = "nuvoton,nau8540", },
{}
{ .compatible = "nuvoton,nau8540", },
{}
};
MODULE_DEVICE_TABLE(of, nau8540_of_ids);
#endif
static struct i2c_driver nau8540_i2c_driver = {
.driver = {
.name = "nau8540",
.of_match_table = of_match_ptr(nau8540_of_ids),
},
.probe = nau8540_i2c_probe,
.remove = nau8540_i2c_remove,
.id_table = nau8540_i2c_ids,
.driver = {
.name = "nau8540",
.of_match_table = of_match_ptr(nau8540_of_ids),
},
.probe = nau8540_i2c_probe,
.remove = nau8540_i2c_remove,
.id_table = nau8540_i2c_ids,
};
module_i2c_driver(nau8540_i2c_driver);
......
sound/soc/codecs/nau8540.h
View file @ ccf9fc86
......@@ -12,211 +12,211 @@
#ifndef __NAU8540_H__
#define __NAU8540_H__
#define NAU8540_REG_SW_RESET 0x00
#define NAU8540_REG_POWER_MANAGEMENT 0x01
#define NAU8540_REG_CLOCK_CTRL 0x02
#define NAU8540_REG_CLOCK_SRC 0x03
#define NAU8540_REG_FLL1 0x04
#define NAU8540_REG_FLL2 0x05
#define NAU8540_REG_FLL3 0x06
#define NAU8540_REG_FLL4 0x07
#define NAU8540_REG_FLL5 0x08
#define NAU8540_REG_FLL6 0x09
#define NAU8540_REG_FLL_VCO_RSV 0x0A
#define NAU8540_REG_PCM_CTRL0 0x10
#define NAU8540_REG_PCM_CTRL1 0x11
#define NAU8540_REG_PCM_CTRL2 0x12
#define NAU8540_REG_PCM_CTRL3 0x13
#define NAU8540_REG_PCM_CTRL4 0x14
#define NAU8540_REG_ALC_CONTROL_1 0x20
#define NAU8540_REG_ALC_CONTROL_2 0x21
#define NAU8540_REG_ALC_CONTROL_3 0x22
#define NAU8540_REG_ALC_CONTROL_4 0x23
#define NAU8540_REG_ALC_CONTROL_5 0x24
#define NAU8540_REG_ALC_GAIN_CH12 0x2D
#define NAU8540_REG_ALC_GAIN_CH34 0x2E
#define NAU8540_REG_ALC_STATUS 0x2F
#define NAU8540_REG_NOTCH_FIL1_CH1 0x30
#define NAU8540_REG_NOTCH_FIL2_CH1 0x31
#define NAU8540_REG_NOTCH_FIL1_CH2 0x32
#define NAU8540_REG_NOTCH_FIL2_CH2 0x33
#define NAU8540_REG_NOTCH_FIL1_CH3 0x34
#define NAU8540_REG_NOTCH_FIL2_CH3 0x35
#define NAU8540_REG_NOTCH_FIL1_CH4 0x36
#define NAU8540_REG_NOTCH_FIL2_CH4 0x37
#define NAU8540_REG_HPF_FILTER_CH12 0x38
#define NAU8540_REG_HPF_FILTER_CH34 0x39
#define NAU8540_REG_ADC_SAMPLE_RATE 0x3A
#define NAU8540_REG_DIGITAL_GAIN_CH1 0x40
#define NAU8540_REG_DIGITAL_GAIN_CH2 0x41
#define NAU8540_REG_DIGITAL_GAIN_CH3 0x42
#define NAU8540_REG_DIGITAL_GAIN_CH4 0x43
#define NAU8540_REG_DIGITAL_MUX 0x44
#define NAU8540_REG_P2P_CH1 0x48
#define NAU8540_REG_P2P_CH2 0x49
#define NAU8540_REG_P2P_CH3 0x4A
#define NAU8540_REG_P2P_CH4 0x4B
#define NAU8540_REG_PEAK_CH1 0x4C
#define NAU8540_REG_PEAK_CH2 0x4D
#define NAU8540_REG_PEAK_CH3 0x4E
#define NAU8540_REG_PEAK_CH4 0x4F
#define NAU8540_REG_GPIO_CTRL 0x50
#define NAU8540_REG_MISC_CTRL 0x51
#define NAU8540_REG_I2C_CTRL 0x52
#define NAU8540_REG_I2C_DEVICE_ID 0x58
#define NAU8540_REG_RST 0x5A
#define NAU8540_REG_VMID_CTRL 0x60
#define NAU8540_REG_MUTE 0x61
#define NAU8540_REG_ANALOG_ADC1 0x64
#define NAU8540_REG_ANALOG_ADC2 0x65
#define NAU8540_REG_ANALOG_PWR 0x66
#define NAU8540_REG_MIC_BIAS 0x67
#define NAU8540_REG_REFERENCE 0x68
#define NAU8540_REG_FEPGA1 0x69
#define NAU8540_REG_FEPGA2 0x6A
#define NAU8540_REG_FEPGA3 0x6B
#define NAU8540_REG_FEPGA4 0x6C
#define NAU8540_REG_PWR 0x6D
#define NAU8540_REG_MAX NAU8540_REG_PWR
#define NAU8540_REG_SW_RESET 0x00
#define NAU8540_REG_POWER_MANAGEMENT 0x01
#define NAU8540_REG_CLOCK_CTRL 0x02
#define NAU8540_REG_CLOCK_SRC 0x03
#define NAU8540_REG_FLL1 0x04
#define NAU8540_REG_FLL2 0x05
#define NAU8540_REG_FLL3 0x06
#define NAU8540_REG_FLL4 0x07
#define NAU8540_REG_FLL5 0x08
#define NAU8540_REG_FLL6 0x09
#define NAU8540_REG_FLL_VCO_RSV 0x0A
#define NAU8540_REG_PCM_CTRL0 0x10
#define NAU8540_REG_PCM_CTRL1 0x11
#define NAU8540_REG_PCM_CTRL2 0x12
#define NAU8540_REG_PCM_CTRL3 0x13
#define NAU8540_REG_PCM_CTRL4 0x14
#define NAU8540_REG_ALC_CONTROL_1 0x20
#define NAU8540_REG_ALC_CONTROL_2 0x21
#define NAU8540_REG_ALC_CONTROL_3 0x22
#define NAU8540_REG_ALC_CONTROL_4 0x23
#define NAU8540_REG_ALC_CONTROL_5 0x24
#define NAU8540_REG_ALC_GAIN_CH12 0x2D
#define NAU8540_REG_ALC_GAIN_CH34 0x2E
#define NAU8540_REG_ALC_STATUS 0x2F
#define NAU8540_REG_NOTCH_FIL1_CH1 0x30
#define NAU8540_REG_NOTCH_FIL2_CH1 0x31
#define NAU8540_REG_NOTCH_FIL1_CH2 0x32
#define NAU8540_REG_NOTCH_FIL2_CH2 0x33
#define NAU8540_REG_NOTCH_FIL1_CH3 0x34
#define NAU8540_REG_NOTCH_FIL2_CH3 0x35
#define NAU8540_REG_NOTCH_FIL1_CH4 0x36
#define NAU8540_REG_NOTCH_FIL2_CH4 0x37
#define NAU8540_REG_HPF_FILTER_CH12 0x38
#define NAU8540_REG_HPF_FILTER_CH34 0x39
#define NAU8540_REG_ADC_SAMPLE_RATE 0x3A
#define NAU8540_REG_DIGITAL_GAIN_CH1 0x40
#define NAU8540_REG_DIGITAL_GAIN_CH2 0x41
#define NAU8540_REG_DIGITAL_GAIN_CH3 0x42
#define NAU8540_REG_DIGITAL_GAIN_CH4 0x43
#define NAU8540_REG_DIGITAL_MUX 0x44
#define NAU8540_REG_P2P_CH1 0x48
#define NAU8540_REG_P2P_CH2 0x49
#define NAU8540_REG_P2P_CH3 0x4A
#define NAU8540_REG_P2P_CH4 0x4B
#define NAU8540_REG_PEAK_CH1 0x4C
#define NAU8540_REG_PEAK_CH2 0x4D
#define NAU8540_REG_PEAK_CH3 0x4E
#define NAU8540_REG_PEAK_CH4 0x4F
#define NAU8540_REG_GPIO_CTRL 0x50
#define NAU8540_REG_MISC_CTRL 0x51
#define NAU8540_REG_I2C_CTRL 0x52
#define NAU8540_REG_I2C_DEVICE_ID 0x58
#define NAU8540_REG_RST 0x5A
#define NAU8540_REG_VMID_CTRL 0x60
#define NAU8540_REG_MUTE 0x61
#define NAU8540_REG_ANALOG_ADC1 0x64
#define NAU8540_REG_ANALOG_ADC2 0x65
#define NAU8540_REG_ANALOG_PWR 0x66
#define NAU8540_REG_MIC_BIAS 0x67
#define NAU8540_REG_REFERENCE 0x68
#define NAU8540_REG_FEPGA1 0x69
#define NAU8540_REG_FEPGA2 0x6A
#define NAU8540_REG_FEPGA3 0x6B
#define NAU8540_REG_FEPGA4 0x6C
#define NAU8540_REG_PWR 0x6D
#define NAU8540_REG_MAX NAU8540_REG_PWR
/* POWER_MANAGEMENT (0x01) */
#define NAU8540_ADC4_EN (0x1 << 3)
#define NAU8540_ADC3_EN (0x1 << 2)
#define NAU8540_ADC2_EN (0x1 << 1)
#define NAU8540_ADC1_EN 0x1
#define NAU8540_ADC4_EN (0x1 << 3)
#define NAU8540_ADC3_EN (0x1 << 2)
#define NAU8540_ADC2_EN (0x1 << 1)
#define NAU8540_ADC1_EN 0x1
/* CLOCK_CTRL (0x02) */
#define NAU8540_CLK_ADC_EN (0x1 << 15)
#define NAU8540_CLK_I2S_EN (0x1 << 1)
#define NAU8540_CLK_ADC_EN (0x1 << 15)
#define NAU8540_CLK_I2S_EN (0x1 << 1)
/* CLOCK_SRC (0x03) */
#define NAU8540_CLK_SRC_SFT 15
#define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT)
#define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT)
#define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT)
#define NAU8540_CLK_ADC_SRC_SFT 6
#define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT)
#define NAU8540_CLK_MCLK_SRC_MASK 0xf
#define NAU8540_CLK_SRC_SFT 15
#define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT)
#define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT)
#define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT)
#define NAU8540_CLK_ADC_SRC_SFT 6
#define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT)
#define NAU8540_CLK_MCLK_SRC_MASK 0xf
/* FLL1 (0x04) */
#define NAU8540_FLL_RATIO_MASK 0x7f
#define NAU8540_FLL_RATIO_MASK 0x7f
/* FLL3 (0x06) */
#define NAU8540_FLL_CLK_SRC_SFT 10
#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_INTEGER_MASK 0x3ff
#define NAU8540_FLL_CLK_SRC_SFT 10
#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_INTEGER_MASK 0x3ff
/* FLL4 (0x07) */
#define NAU8540_FLL_REF_DIV_SFT 10
#define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT)
#define NAU8540_FLL_REF_DIV_SFT 10
#define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT)
/* FLL5 (0x08) */
#define NAU8540_FLL_PDB_DAC_EN (0x1 << 15)
#define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)
#define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)
#define NAU8540_FLL_CLK_SW_N2 (0x1 << 13)
#define NAU8540_FLL_CLK_SW_REF (0x0 << 13)
#define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)
#define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)
#define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12)
#define NAU8540_FLL_PDB_DAC_EN (0x1 << 15)
#define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)
#define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)
#define NAU8540_FLL_CLK_SW_N2 (0x1 << 13)
#define NAU8540_FLL_CLK_SW_REF (0x0 << 13)
#define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)
#define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)
#define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12)
/* FLL6 (0x9) */
#define NAU8540_DCO_EN (0x1 << 15)
#define NAU8540_SDM_EN (0x1 << 14)
#define NAU8540_DCO_EN (0x1 << 15)
#define NAU8540_SDM_EN (0x1 << 14)
/* PCM_CTRL0 (0x10) */
#define NAU8540_I2S_BP_SFT 7
#define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT)
#define NAU8540_I2S_PCMB_SFT 6
#define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT)
#define NAU8540_I2S_DL_SFT 2
#define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DF_MASK 0x3
#define NAU8540_I2S_DF_RIGTH 0
#define NAU8540_I2S_DF_LEFT 0x1
#define NAU8540_I2S_DF_I2S 0x2
#define NAU8540_I2S_DF_PCM_AB 0x3
#define NAU8540_I2S_BP_SFT 7
#define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT)
#define NAU8540_I2S_PCMB_SFT 6
#define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT)
#define NAU8540_I2S_DL_SFT 2
#define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT)
#define NAU8540_I2S_DF_MASK 0x3
#define NAU8540_I2S_DF_RIGTH 0
#define NAU8540_I2S_DF_LEFT 0x1
#define NAU8540_I2S_DF_I2S 0x2
#define NAU8540_I2S_DF_PCM_AB 0x3
/* PCM_CTRL1 (0x11) */
#define NAU8540_I2S_LRC_DIV_SFT 12
#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
#define NAU8540_I2S_DO12_OE (0x1 << 4)
#define NAU8540_I2S_MS_SFT 3
#define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT)
#define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT)
#define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT)
#define NAU8540_I2S_BLK_DIV_MASK 0x7
#define NAU8540_I2S_LRC_DIV_SFT 12
#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
#define NAU8540_I2S_DO12_OE (0x1 << 4)
#define NAU8540_I2S_MS_SFT 3
#define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT)
#define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT)
#define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT)
#define NAU8540_I2S_BLK_DIV_MASK 0x7
/* PCM_CTRL1 (0x12) */
#define NAU8540_I2S_DO34_OE (0x1 << 11)
#define NAU8540_I2S_TSLOT_L_MASK 0x3ff
#define NAU8540_I2S_DO34_OE (0x1 << 11)
#define NAU8540_I2S_TSLOT_L_MASK 0x3ff
/* PCM_CTRL4 (0x14) */
#define NAU8540_TDM_MODE (0x1 << 15)
#define NAU8540_TDM_OFFSET_EN (0x1 << 14)
#define NAU8540_TDM_TX_MASK 0xf
#define NAU8540_TDM_MODE (0x1 << 15)
#define NAU8540_TDM_OFFSET_EN (0x1 << 14)
#define NAU8540_TDM_TX_MASK 0xf
/* ADC_SAMPLE_RATE (0x3A) */
#define NAU8540_ADC_OSR_MASK 0x3
#define NAU8540_ADC_OSR_256 0x3
#define NAU8540_ADC_OSR_128 0x2
#define NAU8540_ADC_OSR_64 0x1
#define NAU8540_ADC_OSR_32 0x0
#define NAU8540_ADC_OSR_MASK 0x3
#define NAU8540_ADC_OSR_256 0x3
#define NAU8540_ADC_OSR_128 0x2
#define NAU8540_ADC_OSR_64 0x1
#define NAU8540_ADC_OSR_32 0x0
/* VMID_CTRL (0x60) */
#define NAU8540_VMID_EN (1 << 6)
#define NAU8540_VMID_SEL_SFT 4
#define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT)
#define NAU8540_VMID_EN (1 << 6)
#define NAU8540_VMID_SEL_SFT 4
#define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT)
/* MIC_BIAS (0x67) */
#define NAU8540_PU_PRE (0x1 << 8)
#define NAU8540_PU_PRE (0x1 << 8)
/* REFERENCE (0x68) */
#define NAU8540_PRECHARGE_DIS (0x1 << 13)
#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
#define NAU8540_PRECHARGE_DIS (0x1 << 13)
#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
/* System Clock Source */
enum {
NAU8540_CLK_DIS,
NAU8540_CLK_MCLK,
NAU8540_CLK_INTERNAL,
NAU8540_CLK_FLL_MCLK,
NAU8540_CLK_FLL_BLK,
NAU8540_CLK_FLL_FS,
NAU8540_CLK_DIS,
NAU8540_CLK_MCLK,
NAU8540_CLK_INTERNAL,
NAU8540_CLK_FLL_MCLK,
NAU8540_CLK_FLL_BLK,
NAU8540_CLK_FLL_FS,
};
struct nau8540 {
struct device *dev;
struct regmap *regmap;
struct device *dev;
struct regmap *regmap;
};
struct nau8540_fll {
int mclk_src;
int ratio;
int fll_frac;
int fll_int;
int clk_ref_div;
int mclk_src;
int ratio;
int fll_frac;
int fll_int;
int clk_ref_div;
};
struct nau8540_fll_attr {
unsigned int param;
unsigned int val;
unsigned int param;
unsigned int val;
};
/* over sampling rate */
struct nau8540_osr_attr {
unsigned int osr;
unsigned int clk_src;
unsigned int osr;
unsigned int clk_src;
};
#endif /* __NAU8540_H__ */
#endif /* __NAU8540_H__ */
sound/soc/mediatek/Kconfig
View file @ ccf9fc86
......@@ -22,6 +22,16 @@ config SND_SOC_MT2701_CS42448
Select Y if you have such device.
If unsure select "N".
config SND_SOC_MT2701_WM8960
tristate "ASoc Audio driver for MT2701 with WM8960 codec"
depends on SND_SOC_MT2701 && I2C
select SND_SOC_WM8960
help
This adds ASoC driver for Mediatek MT2701 boards
with the WM8960 codecs.
Select Y if you have such device.
If unsure select "N".
config SND_SOC_MT8173
tristate "ASoC support for Mediatek MT8173 chip"
depends on ARCH_MEDIATEK
......
sound/soc/mediatek/mt2701/Makefile
View file @ ccf9fc86
......@@ -17,3 +17,4 @@ obj-$(CONFIG_SND_SOC_MT2701) += snd-soc-mt2701-afe.o
# machine driver
obj-$(CONFIG_SND_SOC_MT2701_CS42448) += mt2701-cs42448.o
obj-$(CONFIG_SND_SOC_MT2701_WM8960) += mt2701-wm8960.o
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
View file @ ccf9fc86
......@@ -603,6 +603,22 @@ static struct snd_soc_dai_ops mt2701_btmrg_ops = {
static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "PCMO0",
.id = MT2701_MEMIF_DL1,
.suspend = mtk_afe_dai_suspend,
.resume = mtk_afe_dai_resume,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_single_memif_dai_ops,
},
{
.name = "PCM_multi",
.id = MT2701_MEMIF_DLM,
......
sound/soc/mediatek/mt2701/mt2701-cs42448.c
View file @ ccf9fc86
......@@ -129,7 +129,7 @@ static int mt2701_cs42448_fe_ops_startup(struct snd_pcm_substream *substream)
return 0;
}
static struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
.startup = mt2701_cs42448_fe_ops_startup,
};
......
sound/soc/mediatek/mt2701/mt2701-wm8960.c 0 → 100644
View file @ ccf9fc86
/*
* mt2701-wm8960.c -- MT2701 WM8960 ALSA SoC machine driver
*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <sound/soc.h>
#include "mt2701-afe-common.h"
static const struct snd_soc_dapm_widget mt2701_wm8960_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
};
static const struct snd_kcontrol_new mt2701_wm8960_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("AMIC"),
};
static int mt2701_wm8960_be_ops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
unsigned int mclk_rate;
unsigned int rate = params_rate(params);
unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
unsigned int div_bck_over_lrck = 64;
mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
return 0;
}
static struct snd_soc_ops mt2701_wm8960_be_ops = {
.hw_params = mt2701_wm8960_be_ops_hw_params
};
static struct snd_soc_dai_link mt2701_wm8960_dai_links[] = {
/* FE */
{
.name = "wm8960-playback",
.stream_name = "wm8960-playback",
.cpu_dai_name = "PCMO0",
.codec_name = "snd-soc-dummy",
.codec_dai_name = "snd-soc-dummy-dai",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
},
{
.name = "wm8960-capture",
.stream_name = "wm8960-capture",
.cpu_dai_name = "PCM0",
.codec_name = "snd-soc-dummy",
.codec_dai_name = "snd-soc-dummy-dai",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
},
/* BE */
{
.name = "wm8960-codec",
.cpu_dai_name = "I2S0",
.no_pcm = 1,
.codec_dai_name = "wm8960-hifi",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_GATED,
.ops = &mt2701_wm8960_be_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
},
};
static struct snd_soc_card mt2701_wm8960_card = {
.name = "mt2701-wm8960",
.owner = THIS_MODULE,
.dai_link = mt2701_wm8960_dai_links,
.num_links = ARRAY_SIZE(mt2701_wm8960_dai_links),
.controls = mt2701_wm8960_controls,
.num_controls = ARRAY_SIZE(mt2701_wm8960_controls),
.dapm_widgets = mt2701_wm8960_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt2701_wm8960_widgets),
};
static int mt2701_wm8960_machine_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt2701_wm8960_card;
struct device_node *platform_node, *codec_node;
int ret, i;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for (i = 0; i < card->num_links; i++) {
if (mt2701_wm8960_dai_links[i].platform_name)
continue;
mt2701_wm8960_dai_links[i].platform_of_node = platform_node;
}
card->dev = &pdev->dev;
codec_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
return -EINVAL;
}
for (i = 0; i < card->num_links; i++) {
if (mt2701_wm8960_dai_links[i].codec_name)
continue;
mt2701_wm8960_dai_links[i].codec_of_node = codec_node;
}
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
__func__, ret);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt2701_wm8960_machine_dt_match[] = {
{.compatible = "mediatek,mt2701-wm8960-machine",},
{}
};
#endif
static struct platform_driver mt2701_wm8960_machine = {
.driver = {
.name = "mt2701-wm8960",
.owner = THIS_MODULE,
#ifdef CONFIG_OF
.of_match_table = mt2701_wm8960_machine_dt_match,
#endif
},
.probe = mt2701_wm8960_machine_probe,
};
module_platform_driver(mt2701_wm8960_machine);
/* Module information */
MODULE_DESCRIPTION("MT2701 WM8960 ALSA SoC machine driver");
MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt2701 wm8960 soc card");
sound/soc/mediatek/mt8173/mt8173-max98090.c
View file @ ccf9fc86
......@@ -67,7 +67,7 @@ static int mt8173_max98090_hw_params(struct snd_pcm_substream *substream,
SND_SOC_CLOCK_IN);
}
static struct snd_soc_ops mt8173_max98090_ops = {
static const struct snd_soc_ops mt8173_max98090_ops = {
.hw_params = mt8173_max98090_hw_params,
};
......
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
View file @ ccf9fc86
......@@ -75,7 +75,7 @@ static int mt8173_rt5650_rt5514_hw_params(struct snd_pcm_substream *substream,
return 0;
}
static struct snd_soc_ops mt8173_rt5650_rt5514_ops = {
static const struct snd_soc_ops mt8173_rt5650_rt5514_ops = {
.hw_params = mt8173_rt5650_rt5514_hw_params,
};
......
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
View file @ ccf9fc86
......@@ -79,7 +79,7 @@ static int mt8173_rt5650_rt5676_hw_params(struct snd_pcm_substream *substream,
return 0;
}
static struct snd_soc_ops mt8173_rt5650_rt5676_ops = {
static const struct snd_soc_ops mt8173_rt5650_rt5676_ops = {
.hw_params = mt8173_rt5650_rt5676_hw_params,
};
......
sound/soc/mediatek/mt8173/mt8173-rt5650.c
View file @ ccf9fc86
......@@ -105,7 +105,7 @@ static int mt8173_rt5650_hw_params(struct snd_pcm_substream *substream,
return 0;
}
static struct snd_soc_ops mt8173_rt5650_ops = {
static const struct snd_soc_ops mt8173_rt5650_ops = {
.hw_params = mt8173_rt5650_hw_params,
};
......
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