Commit cdaeb578 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux into drm-fixes

* 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux: (25 commits)
  drm/i915: Fix inconsistent backlight level during disabled
  drm, i915: Fix memory leak in i915_gem_busy_ioctl().
  drm/i915: Use DPCD value for max DP lanes.
  drm/i915: Initiate DP link training only on the lanes we'll be using
  drm/i915: Remove trailing white space
  drm/i915: Try harder during dp pattern 1 link training
  drm/i915: Make DP prepare/commit consistent with DP dpms
  drm/i915: Let panel power sequencing hardware do its job
  drm/i915: Treat PCH eDP like DP in most places
  drm/i915: Remove link_status field from intel_dp structure
  drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control
  drm/i915: Module parameters using '-1' as default must be signed type
  drm/i915: Turn on another required clock gating bit on gen6.
  drm/i915: Turn on a required 3D clock gating bit on Sandybridge.
  drm/i915: enable cacheable objects on Ivybridge
  drm/i915: add constants to size fence arrays and fields
  drm/i915: Ivybridge still has fences!
  drm/i915: forcewake warning fixes in debugfs
  drm/i915: Fix object refcount leak on mmappable size limit error path.
  drm/i915: Use mode_config.mutex in ironlake_panel_vdd_work
  ...
parents e70f224c 04b38670
...@@ -636,11 +636,16 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) ...@@ -636,11 +636,16 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring; struct intel_ring_buffer *ring;
int ret;
ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
if (ring->size == 0) if (ring->size == 0)
return 0; return 0;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
seq_printf(m, "Ring %s:\n", ring->name); seq_printf(m, "Ring %s:\n", ring->name);
seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR); seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR); seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
...@@ -654,6 +659,8 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) ...@@ -654,6 +659,8 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring)); seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
seq_printf(m, " Start : %08x\n", I915_READ_START(ring)); seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -842,7 +849,16 @@ static int i915_rstdby_delays(struct seq_file *m, void *unused) ...@@ -842,7 +849,16 @@ static int i915_rstdby_delays(struct seq_file *m, void *unused)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u16 crstanddelay = I915_READ16(CRSTANDVID); u16 crstanddelay;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
crstanddelay = I915_READ16(CRSTANDVID);
mutex_unlock(&dev->struct_mutex);
seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
...@@ -940,7 +956,11 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) ...@@ -940,7 +956,11 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 delayfreq; u32 delayfreq;
int i; int ret, i;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
delayfreq = I915_READ(PXVFREQ_BASE + i * 4); delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
...@@ -948,6 +968,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) ...@@ -948,6 +968,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused)
(delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
} }
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -962,13 +984,19 @@ static int i915_inttoext_table(struct seq_file *m, void *unused) ...@@ -962,13 +984,19 @@ static int i915_inttoext_table(struct seq_file *m, void *unused)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 inttoext; u32 inttoext;
int i; int ret, i;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
for (i = 1; i <= 32; i++) { for (i = 1; i <= 32; i++) {
inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
} }
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -977,9 +1005,19 @@ static int i915_drpc_info(struct seq_file *m, void *unused) ...@@ -977,9 +1005,19 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 rgvmodectl = I915_READ(MEMMODECTL); u32 rgvmodectl, rstdbyctl;
u32 rstdbyctl = I915_READ(RSTDBYCTL); u16 crstandvid;
u16 crstandvid = I915_READ16(CRSTANDVID); int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
rgvmodectl = I915_READ(MEMMODECTL);
rstdbyctl = I915_READ(RSTDBYCTL);
crstandvid = I915_READ16(CRSTANDVID);
mutex_unlock(&dev->struct_mutex);
seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
"yes" : "no"); "yes" : "no");
...@@ -1167,9 +1205,16 @@ static int i915_gfxec(struct seq_file *m, void *unused) ...@@ -1167,9 +1205,16 @@ static int i915_gfxec(struct seq_file *m, void *unused)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
......
...@@ -68,7 +68,7 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); ...@@ -68,7 +68,7 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
MODULE_PARM_DESC(i915_enable_rc6, MODULE_PARM_DESC(i915_enable_rc6,
"Enable power-saving render C-state 6 (default: true)"); "Enable power-saving render C-state 6 (default: true)");
unsigned int i915_enable_fbc __read_mostly = -1; int i915_enable_fbc __read_mostly = -1;
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
MODULE_PARM_DESC(i915_enable_fbc, MODULE_PARM_DESC(i915_enable_fbc,
"Enable frame buffer compression for power savings " "Enable frame buffer compression for power savings "
...@@ -80,7 +80,7 @@ MODULE_PARM_DESC(lvds_downclock, ...@@ -80,7 +80,7 @@ MODULE_PARM_DESC(lvds_downclock,
"Use panel (LVDS/eDP) downclocking for power savings " "Use panel (LVDS/eDP) downclocking for power savings "
"(default: false)"); "(default: false)");
unsigned int i915_panel_use_ssc __read_mostly = -1; int i915_panel_use_ssc __read_mostly = -1;
module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
MODULE_PARM_DESC(lvds_use_ssc, MODULE_PARM_DESC(lvds_use_ssc,
"Use Spread Spectrum Clock with panels [LVDS/eDP] " "Use Spread Spectrum Clock with panels [LVDS/eDP] "
...@@ -107,7 +107,7 @@ static struct drm_driver driver; ...@@ -107,7 +107,7 @@ static struct drm_driver driver;
extern int intel_agp_enabled; extern int intel_agp_enabled;
#define INTEL_VGA_DEVICE(id, info) { \ #define INTEL_VGA_DEVICE(id, info) { \
.class = PCI_CLASS_DISPLAY_VGA << 8, \ .class = PCI_BASE_CLASS_DISPLAY << 16, \
.class_mask = 0xff0000, \ .class_mask = 0xff0000, \
.vendor = 0x8086, \ .vendor = 0x8086, \
.device = id, \ .device = id, \
......
...@@ -126,6 +126,9 @@ struct drm_i915_master_private { ...@@ -126,6 +126,9 @@ struct drm_i915_master_private {
struct _drm_i915_sarea *sarea_priv; struct _drm_i915_sarea *sarea_priv;
}; };
#define I915_FENCE_REG_NONE -1 #define I915_FENCE_REG_NONE -1
#define I915_MAX_NUM_FENCES 16
/* 16 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 5
struct drm_i915_fence_reg { struct drm_i915_fence_reg {
struct list_head lru_list; struct list_head lru_list;
...@@ -168,7 +171,7 @@ struct drm_i915_error_state { ...@@ -168,7 +171,7 @@ struct drm_i915_error_state {
u32 instdone1; u32 instdone1;
u32 seqno; u32 seqno;
u64 bbaddr; u64 bbaddr;
u64 fence[16]; u64 fence[I915_MAX_NUM_FENCES];
struct timeval time; struct timeval time;
struct drm_i915_error_object { struct drm_i915_error_object {
int page_count; int page_count;
...@@ -182,7 +185,7 @@ struct drm_i915_error_state { ...@@ -182,7 +185,7 @@ struct drm_i915_error_state {
u32 gtt_offset; u32 gtt_offset;
u32 read_domains; u32 read_domains;
u32 write_domain; u32 write_domain;
s32 fence_reg:5; s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
s32 pinned:2; s32 pinned:2;
u32 tiling:2; u32 tiling:2;
u32 dirty:1; u32 dirty:1;
...@@ -375,7 +378,7 @@ typedef struct drm_i915_private { ...@@ -375,7 +378,7 @@ typedef struct drm_i915_private {
struct notifier_block lid_notifier; struct notifier_block lid_notifier;
int crt_ddc_pin; int crt_ddc_pin;
struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
int num_fence_regs; /* 8 on pre-965, 16 otherwise */ int num_fence_regs; /* 8 on pre-965, 16 otherwise */
...@@ -506,7 +509,7 @@ typedef struct drm_i915_private { ...@@ -506,7 +509,7 @@ typedef struct drm_i915_private {
u8 saveAR[21]; u8 saveAR[21];
u8 saveDACMASK; u8 saveDACMASK;
u8 saveCR[37]; u8 saveCR[37];
uint64_t saveFENCE[16]; uint64_t saveFENCE[I915_MAX_NUM_FENCES];
u32 saveCURACNTR; u32 saveCURACNTR;
u32 saveCURAPOS; u32 saveCURAPOS;
u32 saveCURABASE; u32 saveCURABASE;
...@@ -777,10 +780,8 @@ struct drm_i915_gem_object { ...@@ -777,10 +780,8 @@ struct drm_i915_gem_object {
* Fence register bits (if any) for this object. Will be set * Fence register bits (if any) for this object. Will be set
* as needed when mapped into the GTT. * as needed when mapped into the GTT.
* Protected by dev->struct_mutex. * Protected by dev->struct_mutex.
*
* Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
*/ */
signed int fence_reg:5; signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
/** /**
* Advice: are the backing pages purgeable? * Advice: are the backing pages purgeable?
...@@ -999,10 +1000,10 @@ extern int i915_panel_ignore_lid __read_mostly; ...@@ -999,10 +1000,10 @@ extern int i915_panel_ignore_lid __read_mostly;
extern unsigned int i915_powersave __read_mostly; extern unsigned int i915_powersave __read_mostly;
extern unsigned int i915_semaphores __read_mostly; extern unsigned int i915_semaphores __read_mostly;
extern unsigned int i915_lvds_downclock __read_mostly; extern unsigned int i915_lvds_downclock __read_mostly;
extern unsigned int i915_panel_use_ssc __read_mostly; extern int i915_panel_use_ssc __read_mostly;
extern int i915_vbt_sdvo_panel_type __read_mostly; extern int i915_vbt_sdvo_panel_type __read_mostly;
extern unsigned int i915_enable_rc6 __read_mostly; extern unsigned int i915_enable_rc6 __read_mostly;
extern unsigned int i915_enable_fbc __read_mostly; extern int i915_enable_fbc __read_mostly;
extern bool i915_enable_hangcheck __read_mostly; extern bool i915_enable_hangcheck __read_mostly;
extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_suspend(struct drm_device *dev, pm_message_t state);
......
...@@ -1745,7 +1745,7 @@ static void i915_gem_reset_fences(struct drm_device *dev) ...@@ -1745,7 +1745,7 @@ static void i915_gem_reset_fences(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int i; int i;
for (i = 0; i < 16; i++) { for (i = 0; i < dev_priv->num_fence_regs; i++) {
struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
struct drm_i915_gem_object *obj = reg->obj; struct drm_i915_gem_object *obj = reg->obj;
...@@ -3512,9 +3512,11 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, ...@@ -3512,9 +3512,11 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
* so emit a request to do so. * so emit a request to do so.
*/ */
request = kzalloc(sizeof(*request), GFP_KERNEL); request = kzalloc(sizeof(*request), GFP_KERNEL);
if (request) if (request) {
ret = i915_add_request(obj->ring, NULL, request); ret = i915_add_request(obj->ring, NULL, request);
else if (ret)
kfree(request);
} else
ret = -ENOMEM; ret = -ENOMEM;
} }
...@@ -3613,7 +3615,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, ...@@ -3613,7 +3615,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU;
obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU;
if (IS_GEN6(dev)) { if (IS_GEN6(dev) || IS_GEN7(dev)) {
/* On Gen6, we can have the GPU use the LLC (the CPU /* On Gen6, we can have the GPU use the LLC (the CPU
* cache) for about a 10% performance improvement * cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than * compared to uncached. Graphics requests other than
...@@ -3877,7 +3879,7 @@ i915_gem_load(struct drm_device *dev) ...@@ -3877,7 +3879,7 @@ i915_gem_load(struct drm_device *dev)
INIT_LIST_HEAD(&dev_priv->mm.gtt_list); INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
for (i = 0; i < I915_NUM_RINGS; i++) for (i = 0; i < I915_NUM_RINGS; i++)
init_ring_lists(&dev_priv->ring[i]); init_ring_lists(&dev_priv->ring[i]);
for (i = 0; i < 16; i++) for (i = 0; i < I915_MAX_NUM_FENCES; i++)
INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
INIT_DELAYED_WORK(&dev_priv->mm.retire_work, INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
i915_gem_retire_work_handler); i915_gem_retire_work_handler);
......
...@@ -824,6 +824,7 @@ static void i915_gem_record_fences(struct drm_device *dev, ...@@ -824,6 +824,7 @@ static void i915_gem_record_fences(struct drm_device *dev,
/* Fences */ /* Fences */
switch (INTEL_INFO(dev)->gen) { switch (INTEL_INFO(dev)->gen) {
case 7:
case 6: case 6:
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++)
error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
......
...@@ -1553,12 +1553,21 @@ ...@@ -1553,12 +1553,21 @@
*/ */
#define PP_READY (1 << 30) #define PP_READY (1 << 30)
#define PP_SEQUENCE_NONE (0 << 28) #define PP_SEQUENCE_NONE (0 << 28)
#define PP_SEQUENCE_ON (1 << 28) #define PP_SEQUENCE_POWER_UP (1 << 28)
#define PP_SEQUENCE_OFF (2 << 28) #define PP_SEQUENCE_POWER_DOWN (2 << 28)
#define PP_SEQUENCE_MASK 0x30000000 #define PP_SEQUENCE_MASK (3 << 28)
#define PP_SEQUENCE_SHIFT 28
#define PP_CYCLE_DELAY_ACTIVE (1 << 27) #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
#define PP_SEQUENCE_STATE_MASK 0x0000000f #define PP_SEQUENCE_STATE_MASK 0x0000000f
#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
#define PP_SEQUENCE_STATE_RESET (0xf << 0)
#define PP_CONTROL 0x61204 #define PP_CONTROL 0x61204
#define POWER_TARGET_ON (1 << 0) #define POWER_TARGET_ON (1 << 0)
#define PP_ON_DELAYS 0x61208 #define PP_ON_DELAYS 0x61208
...@@ -3444,6 +3453,10 @@ ...@@ -3444,6 +3453,10 @@
#define GT_FIFO_FREE_ENTRIES 0x120008 #define GT_FIFO_FREE_ENTRIES 0x120008
#define GT_FIFO_NUM_RESERVED_ENTRIES 20 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
#define GEN6_UCGCTL2 0x9404
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
#define GEN6_RPNSWREQ 0xA008 #define GEN6_RPNSWREQ 0xA008
#define GEN6_TURBO_DISABLE (1<<31) #define GEN6_TURBO_DISABLE (1<<31)
#define GEN6_FREQUENCY(x) ((x)<<25) #define GEN6_FREQUENCY(x) ((x)<<25)
......
...@@ -370,6 +370,7 @@ static void i915_save_modeset_reg(struct drm_device *dev) ...@@ -370,6 +370,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
/* Fences */ /* Fences */
switch (INTEL_INFO(dev)->gen) { switch (INTEL_INFO(dev)->gen) {
case 7:
case 6: case 6:
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++)
dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
...@@ -404,6 +405,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev) ...@@ -404,6 +405,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
/* Fences */ /* Fences */
switch (INTEL_INFO(dev)->gen) { switch (INTEL_INFO(dev)->gen) {
case 7:
case 6: case 6:
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++)
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]); I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
......
...@@ -2933,7 +2933,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) ...@@ -2933,7 +2933,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
/* For PCH DP, enable TRANS_DP_CTL */ /* For PCH DP, enable TRANS_DP_CTL */
if (HAS_PCH_CPT(dev) && if (HAS_PCH_CPT(dev) &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
reg = TRANS_DP_CTL(pipe); reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg); temp = I915_READ(reg);
...@@ -4711,7 +4712,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, ...@@ -4711,7 +4712,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
lvds_bpc = 6; lvds_bpc = 6;
if (lvds_bpc < display_bpc) { if (lvds_bpc < display_bpc) {
DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
display_bpc = lvds_bpc; display_bpc = lvds_bpc;
} }
continue; continue;
...@@ -4722,7 +4723,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, ...@@ -4722,7 +4723,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
unsigned int edp_bpc = dev_priv->edp.bpp / 3; unsigned int edp_bpc = dev_priv->edp.bpp / 3;
if (edp_bpc < display_bpc) { if (edp_bpc < display_bpc) {
DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
display_bpc = edp_bpc; display_bpc = edp_bpc;
} }
continue; continue;
...@@ -4737,7 +4738,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, ...@@ -4737,7 +4738,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
/* Don't use an invalid EDID bpc value */ /* Don't use an invalid EDID bpc value */
if (connector->display_info.bpc && if (connector->display_info.bpc &&
connector->display_info.bpc < display_bpc) { connector->display_info.bpc < display_bpc) {
DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
display_bpc = connector->display_info.bpc; display_bpc = connector->display_info.bpc;
} }
} }
...@@ -4748,10 +4749,10 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, ...@@ -4748,10 +4749,10 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
*/ */
if (intel_encoder->type == INTEL_OUTPUT_HDMI) { if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
if (display_bpc > 8 && display_bpc < 12) { if (display_bpc > 8 && display_bpc < 12) {
DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n"); DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
display_bpc = 12; display_bpc = 12;
} else { } else {
DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n"); DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
display_bpc = 8; display_bpc = 8;
} }
} }
...@@ -4789,7 +4790,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, ...@@ -4789,7 +4790,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
display_bpc = min(display_bpc, bpc); display_bpc = min(display_bpc, bpc);
DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n", DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
bpc, display_bpc); bpc, display_bpc);
*pipe_bpp = display_bpc * 3; *pipe_bpp = display_bpc * 3;
...@@ -5671,7 +5672,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, ...@@ -5671,7 +5672,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
if ((is_lvds && dev_priv->lvds_dither) || dither) { if ((is_lvds && dev_priv->lvds_dither) || dither) {
pipeconf |= PIPECONF_DITHER_EN; pipeconf |= PIPECONF_DITHER_EN;
pipeconf |= PIPECONF_DITHER_TYPE_ST1; pipeconf |= PIPECONF_DITHER_TYPE_SP;
} }
if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
intel_dp_set_m_n(crtc, mode, adjusted_mode); intel_dp_set_m_n(crtc, mode, adjusted_mode);
...@@ -8148,6 +8149,20 @@ static void gen6_init_clock_gating(struct drm_device *dev) ...@@ -8148,6 +8149,20 @@ static void gen6_init_clock_gating(struct drm_device *dev)
I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0);
/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
* gating disable must be set. Failure to set it results in
* flickering pixels due to Z write ordering failures after
* some amount of runtime in the Mesa "fire" demo, and Unigine
* Sanctuary and Tropics, and apparently anything else with
* alpha test or pixel discard.
*
* According to the spec, bit 11 (RCCUNIT) must also be set,
* but we didn't debug actual testcases to find it out.
*/
I915_WRITE(GEN6_UCGCTL2,
GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
/* /*
* According to the spec the following bits should be * According to the spec the following bits should be
* set in order to enable memory self-refresh and fbc: * set in order to enable memory self-refresh and fbc:
......
This diff is collapsed.
...@@ -326,7 +326,8 @@ static int intel_panel_update_status(struct backlight_device *bd) ...@@ -326,7 +326,8 @@ static int intel_panel_update_status(struct backlight_device *bd)
static int intel_panel_get_brightness(struct backlight_device *bd) static int intel_panel_get_brightness(struct backlight_device *bd)
{ {
struct drm_device *dev = bl_get_data(bd); struct drm_device *dev = bl_get_data(bd);
return intel_panel_get_backlight(dev); struct drm_i915_private *dev_priv = dev->dev_private;
return dev_priv->backlight_level;
} }
static const struct backlight_ops intel_panel_bl_ops = { static const struct backlight_ops intel_panel_bl_ops = {
......
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