Commit cec6721d authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds

[PATCH] ppc32: IBM 40x and 4xx fixes

From: Tom Rini <trini@kernel.crashing.org>

On IBM 40x and IBM 4xx (or more specifically, all Book E processors), the
Save/Restor Registers 2 and 3 Critical Save and Restore Registers 0 and 1
are logically and functionally equivalent.  And since the 40x is the early
variant on the Book E model, make generic 4xx/BookE code refer to
CSRR0/CSRR1, and map these to SRR2/SRR3 on 40x.
parent 959fb245
...@@ -689,8 +689,8 @@ ret_from_crit_exc: ...@@ -689,8 +689,8 @@ ret_from_crit_exc:
mtspr SPRN_ESR,r10 mtspr SPRN_ESR,r10
lwz r11,_NIP(r1) lwz r11,_NIP(r1)
lwz r12,_MSR(r1) lwz r12,_MSR(r1)
mtspr SRR2,r11 mtspr CSRR0,r11
mtspr SRR3,r12 mtspr CSRR1,r12
lwz r9,GPR9(r1) lwz r9,GPR9(r1)
lwz r12,GPR12(r1) lwz r12,GPR12(r1)
lwz r10,crit_sprg0@l(0) lwz r10,crit_sprg0@l(0)
......
...@@ -130,6 +130,8 @@ do { \ ...@@ -130,6 +130,8 @@ do { \
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif #endif
/* Bit definitions for the DBSR. */ /* Bit definitions for the DBSR. */
...@@ -237,8 +239,13 @@ do { \ ...@@ -237,8 +239,13 @@ do { \
#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ #define SGR_GUARDED 1 /* Speculative fetching disallowed. */
/* Short-hand for various SPRs. */ /* Short-hand for various SPRs. */
#ifdef CONFIG_BOOKE
#define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */ #define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */
#define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */ #define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */
#else
#define CSRR0 SPRN_SRR2 /* Logically and functionally equivalent. */
#define CSRR1 SPRN_SRR3 /* Logically and functionally equivalent. */
#endif
#define DCMP SPRN_DCMP /* Data TLB Compare Register */ #define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define SPRG4R SPRN_SPRG4R /* Supervisor Private Registers */ #define SPRG4R SPRN_SPRG4R /* Supervisor Private Registers */
#define SPRG5R SPRN_SPRG5R #define SPRG5R SPRN_SPRG5R
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment