Commit cf66ea8e authored by Dong Aisheng's avatar Dong Aisheng Committed by Sascha Hauer

ARM: mxs: add saif clock

Set pll0 as parent.
Signed-off-by: default avatarDong Aisheng <b29396@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: default avatarWolfram Sang <w.sang@pengutronix.de>
parent 322a8b03
...@@ -640,6 +640,8 @@ static struct clk_lookup lookups[] = { ...@@ -640,6 +640,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "lradc", lradc_clk) _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
_REGISTER_CLOCK(NULL, "spdif", spdif_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk) _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
}; };
static int clk_misc_init(void) static int clk_misc_init(void)
...@@ -774,6 +776,8 @@ int __init mx28_clocks_init(void) ...@@ -774,6 +776,8 @@ int __init mx28_clocks_init(void)
clk_enable(&uart_clk); clk_enable(&uart_clk);
clk_set_parent(&lcdif_clk, &ref_pix_clk); clk_set_parent(&lcdif_clk, &ref_pix_clk);
clk_set_parent(&saif0_clk, &pll0_clk);
clk_set_parent(&saif1_clk, &pll0_clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups)); clkdev_add_table(lookups, ARRAY_SIZE(lookups));
......
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