ARM: mxs: add saif clock
Set pll0 as parent. Signed-off-by: Dong Aisheng <b29396@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Showing
Please register or sign in to comment
Set pll0 as parent. Signed-off-by: Dong Aisheng <b29396@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>