Commit cf98fe6b authored by Nam Cao's avatar Nam Cao Committed by Conor Dooley

riscv: dts: starfive: visionfive 2: correct spi's ss pin

The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.

Fixes: 74fb20c8 ("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: default avatarNam Cao <namcao@linutronix.de>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 15582095
......@@ -431,7 +431,7 @@ GPOEN_ENABLE,
};
ss-pins {
pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>;
bias-disable;
......
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