Commit d00b39c1 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-next-analogix-dp-v2' of github.com:yakir-Yang/linux into drm-next

This pull request want to land the analogix_dp driver into drm/bridge directory,
which reused the Exynos DP code, and add Rockchip DP support. And those
patches have been:

* 'drm-next-analogix-dp-v2' of github.com:yakir-Yang/linux:
  drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time
  drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time
  drm: bridge: analogix/dp: add edid modes parse in get_modes method
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  dt-bindings: add document for rockchip variant of analogix_dp
  drm: rockchip: dp: add rockchip platform dp driver
  ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  dt-bindings: add document for analogix display port driver
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
  drm: bridge: analogix/dp: fix some obvious code style
  drm: bridge: analogix/dp: rename register constants
  drm/exynos: dp: rename implementation specific driver part
  drm: bridge: analogix/dp: split exynos dp driver to bridge directory
parents 85bd5ac3 7b4b7a8d
Analogix Display Port bridge bindings
Required properties for dp-controller:
-compatible:
platform specific such as:
* "samsung,exynos5-dp"
* "rockchip,rk3288-dp"
-reg:
physical base address of the controller and length
of memory mapped region.
-interrupts:
interrupt combiner values.
-clocks:
from common clock binding: handle to dp clock.
-clock-names:
from common clock binding: Shall be "dp".
-interrupt-parent:
phandle to Interrupt combiner node.
-phys:
from general PHY binding: the phandle for the PHY device.
-phy-names:
from general PHY binding: Should be "dp".
Optional properties for dp-controller:
-force-hpd:
Indicate driver need force hpd when hpd detect failed, this
is used for some eDP screen which don't have hpd signal.
-hpd-gpios:
Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug detection
-port@[X]: SoC specific port nodes with endpoint definitions as defined
in Documentation/devicetree/bindings/media/video-interfaces.txt,
please refer to the SoC specific binding document:
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-------------------------------------------------------------------------------
Example:
dp-controller {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x10000>;
interrupts = <10 3>;
interrupt-parent = <&combiner>;
clocks = <&clock 342>;
clock-names = "dp";
phys = <&dp_phy>;
phy-names = "dp";
};
Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
DisplayPort is industry standard to accommodate the growing board adoption
of digital display technology within the PC and CE industries.
It consolidates the internal and external connection methods to reduce device
complexity and cost. It also supports necessary features for important cross
industry applications and provides performance scalability to enable the next
generation of displays that feature higher color depths, refresh rates, and
display resolutions.
eDP (embedded display port) device is compliant with Embedded DisplayPort
standard as follows,
- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
The Exynos display port interface should be configured based on The Exynos display port interface should be configured based on
the type of panel connected to it. the type of panel connected to it.
...@@ -48,26 +31,6 @@ Required properties for dp-controller: ...@@ -48,26 +31,6 @@ Required properties for dp-controller:
from general PHY binding: the phandle for the PHY device. from general PHY binding: the phandle for the PHY device.
-phy-names: -phy-names:
from general PHY binding: Should be "dp". from general PHY binding: Should be "dp".
-samsung,color-space:
input video data format.
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-samsung,dynamic-range:
dynamic range for input video data.
VESA = 0, CEA = 1
-samsung,ycbcr-coeff:
YCbCr co-efficients for input video.
COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-samsung,color-depth:
number of bits per colour component.
COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-samsung,link-rate:
link rate supported by the panel.
LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-samsung,lane-count:
number of lanes supported by the panel.
LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
- display-timings: timings for the connected panel as described by
Documentation/devicetree/bindings/display/display-timing.txt
Optional properties for dp-controller: Optional properties for dp-controller:
-interlaced: -interlaced:
...@@ -83,17 +46,31 @@ Optional properties for dp-controller: ...@@ -83,17 +46,31 @@ Optional properties for dp-controller:
Hotplug detect GPIO. Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug Indicates which GPIO should be used for hotplug
detection detection
Video interfaces: -video interfaces: Device node can contain video interface port
Device node can contain video interface port nodes according to [1]. nodes according to [1].
The following are properties specific to those nodes: - display-timings: timings for the connected panel as described by
Documentation/devicetree/bindings/display/panel/display-timing.txt
endpoint node connected to bridge or panel node:
- remote-endpoint: specifies the endpoint in panel or bridge node. For the below properties, please refer to Analogix DP binding document:
This node is required in all kinds of exynos dp * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
to represent the connection between dp and bridge -phys (required)
or dp and panel. -phy-names (required)
-hpd-gpios (optional)
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt force-hpd (optional)
Deprecated properties for DisplayPort:
-interlaced: deprecated prop that can parsed from drm_display_mode.
-vsync-active-high: deprecated prop that can parsed from drm_display_mode.
-hsync-active-high: deprecated prop that can parsed from drm_display_mode.
-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
-samsung,color-space: deprecated prop that can parsed from drm_display_info.
-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
-samsung,hpd-gpio: deprecated name for hpd-gpios.
-------------------------------------------------------------------------------
Example: Example:
...@@ -112,13 +89,6 @@ SOC specific portion: ...@@ -112,13 +89,6 @@ SOC specific portion:
Board Specific portion: Board Specific portion:
dp-controller { dp-controller {
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
display-timings { display-timings {
native-mode = <&lcd_timing>; native-mode = <&lcd_timing>;
lcd_timing: 1366x768 { lcd_timing: 1366x768 {
...@@ -135,18 +105,9 @@ Board Specific portion: ...@@ -135,18 +105,9 @@ Board Specific portion:
}; };
ports { ports {
port { port@0 {
dp_out: endpoint { dp_out: endpoint {
remote-endpoint = <&dp_in>; remote-endpoint = <&bridge_in>;
};
};
};
panel {
...
port {
dp_in: endpoint {
remote-endpoint = <&dp_out>;
}; };
}; };
}; };
......
Rockchip RK3288 specific extensions to the Analogix Display Port
================================
Required properties:
- compatible: "rockchip,rk3288-edp";
- reg: physical base address of the controller and length
- clocks: from common clock binding: handle to dp clock.
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "dp" "pclk"
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
- pinctrl-0: pin-control mode. should be <&edp_hpd>
- reset-names: Must include the name "dp"
- rockchip,grf: this soc should set GRF regs, so need get grf here.
- ports: there are 2 port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Port 0: contained 2 endpoints, connecting to the output of vop.
Port 1: contained 1 endpoint, connecting to the input of panel.
For the below properties, please refer to Analogix DP binding document:
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
- phys (required)
- phy-names (required)
- hpd-gpios (optional)
- force-hpd (optional)
-------------------------------------------------------------------------------
Example:
dp-controller: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
phys = <&dp_phy>;
phy-names = "dp";
rockchip,grf = <&grf>;
resets = <&cru 111>;
reset-names = "dp";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint {
reg = <0>;
remote-endpoint = <&panel_in_edp>
};
};
};
};
pinctrl {
edp {
edp_hpd: edp-hpd {
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
};
};
};
...@@ -124,8 +124,6 @@ &cpu0 { ...@@ -124,8 +124,6 @@ &cpu0 {
&dp { &dp {
status = "okay"; status = "okay";
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x0a>; samsung,link-rate = <0x0a>;
samsung,lane-count = <4>; samsung,lane-count = <4>;
......
...@@ -80,8 +80,6 @@ &cpu0 { ...@@ -80,8 +80,6 @@ &cpu0 {
&dp { &dp {
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x0a>; samsung,link-rate = <0x0a>;
samsung,lane-count = <4>; samsung,lane-count = <4>;
......
...@@ -236,12 +236,10 @@ &dp { ...@@ -236,12 +236,10 @@ &dp {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>; pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x0a>; samsung,link-rate = <0x0a>;
samsung,lane-count = <2>; samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
ports { ports {
port@0 { port@0 {
......
...@@ -74,12 +74,10 @@ &dp { ...@@ -74,12 +74,10 @@ &dp {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>; pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x0a>; samsung,link-rate = <0x0a>;
samsung,lane-count = <1>; samsung,lane-count = <1>;
samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>; hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
}; };
&ehci { &ehci {
......
...@@ -157,12 +157,10 @@ &dp { ...@@ -157,12 +157,10 @@ &dp {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>; pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x06>; samsung,link-rate = <0x06>;
samsung,lane-count = <2>; samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
ports { ports {
port@0 { port@0 {
......
...@@ -102,8 +102,6 @@ &dp { ...@@ -102,8 +102,6 @@ &dp {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>; pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x0a>; samsung,link-rate = <0x0a>;
samsung,lane-count = <4>; samsung,lane-count = <4>;
......
...@@ -157,8 +157,6 @@ &dp { ...@@ -157,8 +157,6 @@ &dp {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>; pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>; samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>; samsung,color-depth = <1>;
samsung,link-rate = <0x0a>; samsung,link-rate = <0x0a>;
samsung,lane-count = <2>; samsung,lane-count = <2>;
......
...@@ -40,4 +40,6 @@ config DRM_PARADE_PS8622 ...@@ -40,4 +40,6 @@ config DRM_PARADE_PS8622
---help--- ---help---
Parade eDP-LVDS bridge chip driver. Parade eDP-LVDS bridge chip driver.
source "drivers/gpu/drm/bridge/analogix/Kconfig"
endmenu endmenu
...@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o ...@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
config DRM_ANALOGIX_DP
tristate
depends on DRM
analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
/* /*
* Samsung SoC DP (Display Port) interface driver. * Analogix DP (Display Port) core interface driver.
* *
* Copyright (C) 2012 Samsung Electronics Co., Ltd. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your * Free Software Foundation; either version 2 of the License, or (at your
* option) any later version. * option) any later version.
*/ */
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
...@@ -18,77 +18,86 @@ ...@@ -18,77 +18,86 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_gpio.h> #include <linux/of_gpio.h>
#include <linux/of_graph.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/component.h> #include <linux/component.h>
#include <linux/phy/phy.h> #include <linux/phy/phy.h>
#include <video/of_display_timing.h>
#include <video/of_videomode.h>
#include <drm/drmP.h> #include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h> #include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h> #include <drm/drm_crtc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h> #include <drm/drm_panel.h>
#include "exynos_dp_core.h" #include <drm/bridge/analogix_dp.h>
#include "exynos_drm_crtc.h"
#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \ #include "analogix_dp_core.h"
connector)
static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
{
return to_exynos_crtc(dp->encoder.crtc);
}
static inline struct exynos_dp_device *encoder_to_dp( #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
struct drm_encoder *e)
{
return container_of(e, struct exynos_dp_device, encoder);
}
struct bridge_init { struct bridge_init {
struct i2c_client *client; struct i2c_client *client;
struct device_node *node; struct device_node *node;
}; };
static void exynos_dp_init_dp(struct exynos_dp_device *dp) static void analogix_dp_init_dp(struct analogix_dp_device *dp)
{ {
exynos_dp_reset(dp); analogix_dp_reset(dp);
exynos_dp_swreset(dp); analogix_dp_swreset(dp);
exynos_dp_init_analog_param(dp); analogix_dp_init_analog_param(dp);
exynos_dp_init_interrupt(dp); analogix_dp_init_interrupt(dp);
/* SW defined function Normal operation */ /* SW defined function Normal operation */
exynos_dp_enable_sw_function(dp); analogix_dp_enable_sw_function(dp);
exynos_dp_config_interrupt(dp); analogix_dp_config_interrupt(dp);
exynos_dp_init_analog_func(dp); analogix_dp_init_analog_func(dp);
exynos_dp_init_hpd(dp); analogix_dp_init_hpd(dp);
exynos_dp_init_aux(dp); analogix_dp_init_aux(dp);
} }
static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
{ {
int timeout_loop = 0; int timeout_loop = 0;
while (exynos_dp_get_plug_in_status(dp) != 0) { while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
if (analogix_dp_get_plug_in_status(dp) == 0)
return 0;
timeout_loop++; timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get hpd plug status\n");
return -ETIMEDOUT;
}
usleep_range(10, 11); usleep_range(10, 11);
} }
/*
* Some edp screen do not have hpd signal, so we can't just
* return failed when hpd plug in detect failed, DT property
* "force-hpd" would indicate whether driver need this.
*/
if (!dp->force_hpd)
return -ETIMEDOUT;
/*
* The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
* will not work, so we need to give a force hpd action to
* set HPD_STATUS manually.
*/
dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
analogix_dp_force_hpd(dp);
if (analogix_dp_get_plug_in_status(dp) != 0) {
dev_err(dp->dev, "failed to get hpd plug in status\n");
return -EINVAL;
}
dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
return 0; return 0;
} }
static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
{ {
int i; int i;
unsigned char sum = 0; unsigned char sum = 0;
...@@ -99,9 +108,9 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) ...@@ -99,9 +108,9 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
return sum; return sum;
} }
static int exynos_dp_read_edid(struct exynos_dp_device *dp) static int analogix_dp_read_edid(struct analogix_dp_device *dp)
{ {
unsigned char edid[EDID_BLOCK_LENGTH * 2]; unsigned char *edid = dp->edid;
unsigned int extend_block = 0; unsigned int extend_block = 0;
unsigned char sum; unsigned char sum;
unsigned char test_vector; unsigned char test_vector;
...@@ -114,9 +123,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) ...@@ -114,9 +123,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
*/ */
/* Read Extension Flag, Number of 128-byte EDID extension blocks */ /* Read Extension Flag, Number of 128-byte EDID extension blocks */
retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
EDID_EXTENSION_FLAG, EDID_EXTENSION_FLAG,
&extend_block); &extend_block);
if (retval) if (retval)
return retval; return retval;
...@@ -124,7 +133,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) ...@@ -124,7 +133,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
dev_dbg(dp->dev, "EDID data includes a single extension!\n"); dev_dbg(dp->dev, "EDID data includes a single extension!\n");
/* Read EDID data */ /* Read EDID data */
retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, retval = analogix_dp_read_bytes_from_i2c(dp,
I2C_EDID_DEVICE_ADDR,
EDID_HEADER_PATTERN, EDID_HEADER_PATTERN,
EDID_BLOCK_LENGTH, EDID_BLOCK_LENGTH,
&edid[EDID_HEADER_PATTERN]); &edid[EDID_HEADER_PATTERN]);
...@@ -132,14 +142,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) ...@@ -132,14 +142,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
dev_err(dp->dev, "EDID Read failed!\n"); dev_err(dp->dev, "EDID Read failed!\n");
return -EIO; return -EIO;
} }
sum = exynos_dp_calc_edid_check_sum(edid); sum = analogix_dp_calc_edid_check_sum(edid);
if (sum != 0) { if (sum != 0) {
dev_err(dp->dev, "EDID bad checksum!\n"); dev_err(dp->dev, "EDID bad checksum!\n");
return -EIO; return -EIO;
} }
/* Read additional EDID data */ /* Read additional EDID data */
retval = exynos_dp_read_bytes_from_i2c(dp, retval = analogix_dp_read_bytes_from_i2c(dp,
I2C_EDID_DEVICE_ADDR, I2C_EDID_DEVICE_ADDR,
EDID_BLOCK_LENGTH, EDID_BLOCK_LENGTH,
EDID_BLOCK_LENGTH, EDID_BLOCK_LENGTH,
...@@ -148,19 +158,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) ...@@ -148,19 +158,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
dev_err(dp->dev, "EDID Read failed!\n"); dev_err(dp->dev, "EDID Read failed!\n");
return -EIO; return -EIO;
} }
sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
if (sum != 0) { if (sum != 0) {
dev_err(dp->dev, "EDID bad checksum!\n"); dev_err(dp->dev, "EDID bad checksum!\n");
return -EIO; return -EIO;
} }
exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
&test_vector); &test_vector);
if (test_vector & DP_TEST_LINK_EDID_READ) { if (test_vector & DP_TEST_LINK_EDID_READ) {
exynos_dp_write_byte_to_dpcd(dp, analogix_dp_write_byte_to_dpcd(dp,
DP_TEST_EDID_CHECKSUM, DP_TEST_EDID_CHECKSUM,
edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
exynos_dp_write_byte_to_dpcd(dp, analogix_dp_write_byte_to_dpcd(dp,
DP_TEST_RESPONSE, DP_TEST_RESPONSE,
DP_TEST_EDID_CHECKSUM_WRITE); DP_TEST_EDID_CHECKSUM_WRITE);
} }
...@@ -168,31 +178,26 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) ...@@ -168,31 +178,26 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
dev_info(dp->dev, "EDID data does not include any extensions.\n"); dev_info(dp->dev, "EDID data does not include any extensions.\n");
/* Read EDID data */ /* Read EDID data */
retval = exynos_dp_read_bytes_from_i2c(dp, retval = analogix_dp_read_bytes_from_i2c(dp,
I2C_EDID_DEVICE_ADDR, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
EDID_HEADER_PATTERN, EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
EDID_BLOCK_LENGTH,
&edid[EDID_HEADER_PATTERN]);
if (retval != 0) { if (retval != 0) {
dev_err(dp->dev, "EDID Read failed!\n"); dev_err(dp->dev, "EDID Read failed!\n");
return -EIO; return -EIO;
} }
sum = exynos_dp_calc_edid_check_sum(edid); sum = analogix_dp_calc_edid_check_sum(edid);
if (sum != 0) { if (sum != 0) {
dev_err(dp->dev, "EDID bad checksum!\n"); dev_err(dp->dev, "EDID bad checksum!\n");
return -EIO; return -EIO;
} }
exynos_dp_read_byte_from_dpcd(dp, analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
DP_TEST_REQUEST, &test_vector);
&test_vector);
if (test_vector & DP_TEST_LINK_EDID_READ) { if (test_vector & DP_TEST_LINK_EDID_READ) {
exynos_dp_write_byte_to_dpcd(dp, analogix_dp_write_byte_to_dpcd(dp,
DP_TEST_EDID_CHECKSUM, DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
edid[EDID_CHECKSUM]); analogix_dp_write_byte_to_dpcd(dp,
exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
DP_TEST_RESPONSE,
DP_TEST_EDID_CHECKSUM_WRITE);
} }
} }
...@@ -200,21 +205,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) ...@@ -200,21 +205,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
return 0; return 0;
} }
static int exynos_dp_handle_edid(struct exynos_dp_device *dp) static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
{ {
u8 buf[12]; u8 buf[12];
int i; int i;
int retval; int retval;
/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
12, buf);
if (retval) if (retval)
return retval; return retval;
/* Read EDID */ /* Read EDID */
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
retval = exynos_dp_read_edid(dp); retval = analogix_dp_read_edid(dp);
if (!retval) if (!retval)
break; break;
} }
...@@ -222,73 +226,74 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp) ...@@ -222,73 +226,74 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
return retval; return retval;
} }
static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, static void
bool enable) analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
bool enable)
{ {
u8 data; u8 data;
exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
if (enable) if (enable)
exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
DP_LANE_COUNT_ENHANCED_FRAME_EN | DP_LANE_COUNT_ENHANCED_FRAME_EN |
DPCD_LANE_COUNT_SET(data)); DPCD_LANE_COUNT_SET(data));
else else
exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
DPCD_LANE_COUNT_SET(data)); DPCD_LANE_COUNT_SET(data));
} }
static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
{ {
u8 data; u8 data;
int retval; int retval;
exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
retval = DPCD_ENHANCED_FRAME_CAP(data); retval = DPCD_ENHANCED_FRAME_CAP(data);
return retval; return retval;
} }
static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp) static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
{ {
u8 data; u8 data;
data = exynos_dp_is_enhanced_mode_available(dp); data = analogix_dp_is_enhanced_mode_available(dp);
exynos_dp_enable_rx_to_enhanced_mode(dp, data); analogix_dp_enable_rx_to_enhanced_mode(dp, data);
exynos_dp_enable_enhanced_mode(dp, data); analogix_dp_enable_enhanced_mode(dp, data);
} }
static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
{ {
exynos_dp_set_training_pattern(dp, DP_NONE); analogix_dp_set_training_pattern(dp, DP_NONE);
exynos_dp_write_byte_to_dpcd(dp, analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
DP_TRAINING_PATTERN_DISABLE);
} }
static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static void
int pre_emphasis, int lane) analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
int pre_emphasis, int lane)
{ {
switch (lane) { switch (lane) {
case 0: case 0:
exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis); analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
break; break;
case 1: case 1:
exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis); analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
break; break;
case 2: case 2:
exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis); analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
break; break;
case 3: case 3:
exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis); analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
break; break;
} }
} }
static int exynos_dp_link_start(struct exynos_dp_device *dp) static int analogix_dp_link_start(struct analogix_dp_device *dp)
{ {
u8 buf[4]; u8 buf[4];
int lane, lane_count, pll_tries, retval; int lane, lane_count, pll_tries, retval;
...@@ -302,25 +307,24 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) ...@@ -302,25 +307,24 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
dp->link_train.cr_loop[lane] = 0; dp->link_train.cr_loop[lane] = 0;
/* Set link rate and count as you want to establish*/ /* Set link rate and count as you want to establish*/
exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
exynos_dp_set_lane_count(dp, dp->link_train.lane_count); analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
/* Setup RX configuration */ /* Setup RX configuration */
buf[0] = dp->link_train.link_rate; buf[0] = dp->link_train.link_rate;
buf[1] = dp->link_train.lane_count; buf[1] = dp->link_train.lane_count;
retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
2, buf);
if (retval) if (retval)
return retval; return retval;
/* Set TX pre-emphasis to minimum */ /* Set TX pre-emphasis to minimum */
for (lane = 0; lane < lane_count; lane++) for (lane = 0; lane < lane_count; lane++)
exynos_dp_set_lane_lane_pre_emphasis(dp, analogix_dp_set_lane_lane_pre_emphasis(dp,
PRE_EMPHASIS_LEVEL_0, lane); PRE_EMPHASIS_LEVEL_0, lane);
/* Wait for PLL lock */ /* Wait for PLL lock */
pll_tries = 0; pll_tries = 0;
while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Wait for PLL lock timed out\n"); dev_err(dp->dev, "Wait for PLL lock timed out\n");
return -ETIMEDOUT; return -ETIMEDOUT;
...@@ -331,10 +335,10 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) ...@@ -331,10 +335,10 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
} }
/* Set training pattern 1 */ /* Set training pattern 1 */
exynos_dp_set_training_pattern(dp, TRAINING_PTN1); analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
/* Set RX training pattern */ /* Set RX training pattern */
retval = exynos_dp_write_byte_to_dpcd(dp, retval = analogix_dp_write_byte_to_dpcd(dp,
DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_SET,
DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
if (retval) if (retval)
...@@ -344,35 +348,35 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) ...@@ -344,35 +348,35 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
DP_TRAIN_VOLTAGE_SWING_LEVEL_0; DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
lane_count, buf); lane_count, buf);
return retval; return retval;
} }
static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
{ {
int shift = (lane & 1) * 4; int shift = (lane & 1) * 4;
u8 link_value = link_status[lane>>1]; u8 link_value = link_status[lane >> 1];
return (link_value >> shift) & 0xf; return (link_value >> shift) & 0xf;
} }
static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
{ {
int lane; int lane;
u8 lane_status; u8 lane_status;
for (lane = 0; lane < lane_count; lane++) { for (lane = 0; lane < lane_count; lane++) {
lane_status = exynos_dp_get_lane_status(link_status, lane); lane_status = analogix_dp_get_lane_status(link_status, lane);
if ((lane_status & DP_LANE_CR_DONE) == 0) if ((lane_status & DP_LANE_CR_DONE) == 0)
return -EINVAL; return -EINVAL;
} }
return 0; return 0;
} }
static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
int lane_count) int lane_count)
{ {
int lane; int lane;
u8 lane_status; u8 lane_status;
...@@ -381,7 +385,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, ...@@ -381,7 +385,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
return -EINVAL; return -EINVAL;
for (lane = 0; lane < lane_count; lane++) { for (lane = 0; lane < lane_count; lane++) {
lane_status = exynos_dp_get_lane_status(link_status, lane); lane_status = analogix_dp_get_lane_status(link_status, lane);
lane_status &= DP_CHANNEL_EQ_BITS; lane_status &= DP_CHANNEL_EQ_BITS;
if (lane_status != DP_CHANNEL_EQ_BITS) if (lane_status != DP_CHANNEL_EQ_BITS)
return -EINVAL; return -EINVAL;
...@@ -390,64 +394,64 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, ...@@ -390,64 +394,64 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
return 0; return 0;
} }
static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], static unsigned char
int lane) analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
{ {
int shift = (lane & 1) * 4; int shift = (lane & 1) * 4;
u8 link_value = adjust_request[lane>>1]; u8 link_value = adjust_request[lane >> 1];
return (link_value >> shift) & 0x3; return (link_value >> shift) & 0x3;
} }
static unsigned char exynos_dp_get_adjust_request_pre_emphasis( static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
u8 adjust_request[2], u8 adjust_request[2],
int lane) int lane)
{ {
int shift = (lane & 1) * 4; int shift = (lane & 1) * 4;
u8 link_value = adjust_request[lane>>1]; u8 link_value = adjust_request[lane >> 1];
return ((link_value >> shift) & 0xc) >> 2; return ((link_value >> shift) & 0xc) >> 2;
} }
static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
u8 training_lane_set, int lane) u8 training_lane_set, int lane)
{ {
switch (lane) { switch (lane) {
case 0: case 0:
exynos_dp_set_lane0_link_training(dp, training_lane_set); analogix_dp_set_lane0_link_training(dp, training_lane_set);
break; break;
case 1: case 1:
exynos_dp_set_lane1_link_training(dp, training_lane_set); analogix_dp_set_lane1_link_training(dp, training_lane_set);
break; break;
case 2: case 2:
exynos_dp_set_lane2_link_training(dp, training_lane_set); analogix_dp_set_lane2_link_training(dp, training_lane_set);
break; break;
case 3: case 3:
exynos_dp_set_lane3_link_training(dp, training_lane_set); analogix_dp_set_lane3_link_training(dp, training_lane_set);
break; break;
} }
} }
static unsigned int exynos_dp_get_lane_link_training( static unsigned int
struct exynos_dp_device *dp, analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
int lane) int lane)
{ {
u32 reg; u32 reg;
switch (lane) { switch (lane) {
case 0: case 0:
reg = exynos_dp_get_lane0_link_training(dp); reg = analogix_dp_get_lane0_link_training(dp);
break; break;
case 1: case 1:
reg = exynos_dp_get_lane1_link_training(dp); reg = analogix_dp_get_lane1_link_training(dp);
break; break;
case 2: case 2:
reg = exynos_dp_get_lane2_link_training(dp); reg = analogix_dp_get_lane2_link_training(dp);
break; break;
case 3: case 3:
reg = exynos_dp_get_lane3_link_training(dp); reg = analogix_dp_get_lane3_link_training(dp);
break; break;
default: default:
WARN_ON(1); WARN_ON(1);
...@@ -457,25 +461,25 @@ static unsigned int exynos_dp_get_lane_link_training( ...@@ -457,25 +461,25 @@ static unsigned int exynos_dp_get_lane_link_training(
return reg; return reg;
} }
static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
{ {
exynos_dp_training_pattern_dis(dp); analogix_dp_training_pattern_dis(dp);
exynos_dp_set_enhanced_mode(dp); analogix_dp_set_enhanced_mode(dp);
dp->link_train.lt_state = FAILED; dp->link_train.lt_state = FAILED;
} }
static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
u8 adjust_request[2]) u8 adjust_request[2])
{ {
int lane, lane_count; int lane, lane_count;
u8 voltage_swing, pre_emphasis, training_lane; u8 voltage_swing, pre_emphasis, training_lane;
lane_count = dp->link_train.lane_count; lane_count = dp->link_train.lane_count;
for (lane = 0; lane < lane_count; lane++) { for (lane = 0; lane < lane_count; lane++) {
voltage_swing = exynos_dp_get_adjust_request_voltage( voltage_swing = analogix_dp_get_adjust_request_voltage(
adjust_request, lane); adjust_request, lane);
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
adjust_request, lane); adjust_request, lane);
training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
DPCD_PRE_EMPHASIS_SET(pre_emphasis); DPCD_PRE_EMPHASIS_SET(pre_emphasis);
...@@ -489,7 +493,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, ...@@ -489,7 +493,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
} }
} }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
{ {
int lane, lane_count, retval; int lane, lane_count, retval;
u8 voltage_swing, pre_emphasis, training_lane; u8 voltage_swing, pre_emphasis, training_lane;
...@@ -499,21 +503,21 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) ...@@ -499,21 +503,21 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
lane_count = dp->link_train.lane_count; lane_count = dp->link_train.lane_count;
retval = exynos_dp_read_bytes_from_dpcd(dp, retval = analogix_dp_read_bytes_from_dpcd(dp,
DP_LANE0_1_STATUS, 2, link_status); DP_LANE0_1_STATUS, 2, link_status);
if (retval) if (retval)
return retval; return retval;
retval = exynos_dp_read_bytes_from_dpcd(dp, retval = analogix_dp_read_bytes_from_dpcd(dp,
DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
if (retval) if (retval)
return retval; return retval;
if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
/* set training pattern 2 for EQ */ /* set training pattern 2 for EQ */
exynos_dp_set_training_pattern(dp, TRAINING_PTN2); analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
retval = exynos_dp_write_byte_to_dpcd(dp, retval = analogix_dp_write_byte_to_dpcd(dp,
DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_SET,
DP_LINK_SCRAMBLING_DISABLE | DP_LINK_SCRAMBLING_DISABLE |
DP_TRAINING_PATTERN_2); DP_TRAINING_PATTERN_2);
...@@ -524,11 +528,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) ...@@ -524,11 +528,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
dp->link_train.lt_state = EQUALIZER_TRAINING; dp->link_train.lt_state = EQUALIZER_TRAINING;
} else { } else {
for (lane = 0; lane < lane_count; lane++) { for (lane = 0; lane < lane_count; lane++) {
training_lane = exynos_dp_get_lane_link_training( training_lane = analogix_dp_get_lane_link_training(
dp, lane); dp, lane);
voltage_swing = exynos_dp_get_adjust_request_voltage( voltage_swing = analogix_dp_get_adjust_request_voltage(
adjust_request, lane); adjust_request, lane);
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
adjust_request, lane); adjust_request, lane);
if (DPCD_VOLTAGE_SWING_GET(training_lane) == if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
...@@ -543,19 +547,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) ...@@ -543,19 +547,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
dp->link_train.cr_loop[lane], dp->link_train.cr_loop[lane],
voltage_swing, pre_emphasis); voltage_swing, pre_emphasis);
exynos_dp_reduce_link_rate(dp); analogix_dp_reduce_link_rate(dp);
return -EIO; return -EIO;
} }
} }
} }
exynos_dp_get_adjust_training_lane(dp, adjust_request); analogix_dp_get_adjust_training_lane(dp, adjust_request);
for (lane = 0; lane < lane_count; lane++) for (lane = 0; lane < lane_count; lane++)
exynos_dp_set_lane_link_training(dp, analogix_dp_set_lane_link_training(dp,
dp->link_train.training_lane[lane], lane); dp->link_train.training_lane[lane], lane);
retval = exynos_dp_write_bytes_to_dpcd(dp, retval = analogix_dp_write_bytes_to_dpcd(dp,
DP_TRAINING_LANE0_SET, lane_count, DP_TRAINING_LANE0_SET, lane_count,
dp->link_train.training_lane); dp->link_train.training_lane);
if (retval) if (retval)
...@@ -564,7 +568,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) ...@@ -564,7 +568,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
return retval; return retval;
} }
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
{ {
int lane, lane_count, retval; int lane, lane_count, retval;
u32 reg; u32 reg;
...@@ -574,46 +578,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) ...@@ -574,46 +578,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
lane_count = dp->link_train.lane_count; lane_count = dp->link_train.lane_count;
retval = exynos_dp_read_bytes_from_dpcd(dp, retval = analogix_dp_read_bytes_from_dpcd(dp,
DP_LANE0_1_STATUS, 2, link_status); DP_LANE0_1_STATUS, 2, link_status);
if (retval) if (retval)
return retval; return retval;
if (exynos_dp_clock_recovery_ok(link_status, lane_count)) { if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
exynos_dp_reduce_link_rate(dp); analogix_dp_reduce_link_rate(dp);
return -EIO; return -EIO;
} }
retval = exynos_dp_read_bytes_from_dpcd(dp, retval = analogix_dp_read_bytes_from_dpcd(dp,
DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
if (retval) if (retval)
return retval; return retval;
retval = exynos_dp_read_byte_from_dpcd(dp, retval = analogix_dp_read_byte_from_dpcd(dp,
DP_LANE_ALIGN_STATUS_UPDATED, &link_align); DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
if (retval) if (retval)
return retval; return retval;
exynos_dp_get_adjust_training_lane(dp, adjust_request); analogix_dp_get_adjust_training_lane(dp, adjust_request);
if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) { if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
/* traing pattern Set to Normal */ /* traing pattern Set to Normal */
exynos_dp_training_pattern_dis(dp); analogix_dp_training_pattern_dis(dp);
dev_info(dp->dev, "Link Training success!\n"); dev_info(dp->dev, "Link Training success!\n");
exynos_dp_get_link_bandwidth(dp, &reg); analogix_dp_get_link_bandwidth(dp, &reg);
dp->link_train.link_rate = reg; dp->link_train.link_rate = reg;
dev_dbg(dp->dev, "final bandwidth = %.2x\n", dev_dbg(dp->dev, "final bandwidth = %.2x\n",
dp->link_train.link_rate); dp->link_train.link_rate);
exynos_dp_get_lane_count(dp, &reg); analogix_dp_get_lane_count(dp, &reg);
dp->link_train.lane_count = reg; dp->link_train.lane_count = reg;
dev_dbg(dp->dev, "final lane count = %.2x\n", dev_dbg(dp->dev, "final lane count = %.2x\n",
dp->link_train.lane_count); dp->link_train.lane_count);
/* set enhanced mode if available */ /* set enhanced mode if available */
exynos_dp_set_enhanced_mode(dp); analogix_dp_set_enhanced_mode(dp);
dp->link_train.lt_state = FINISHED; dp->link_train.lt_state = FINISHED;
return 0; return 0;
...@@ -624,35 +628,37 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) ...@@ -624,35 +628,37 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
if (dp->link_train.eq_loop > MAX_EQ_LOOP) { if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
dev_err(dp->dev, "EQ Max loop\n"); dev_err(dp->dev, "EQ Max loop\n");
exynos_dp_reduce_link_rate(dp); analogix_dp_reduce_link_rate(dp);
return -EIO; return -EIO;
} }
for (lane = 0; lane < lane_count; lane++) for (lane = 0; lane < lane_count; lane++)
exynos_dp_set_lane_link_training(dp, analogix_dp_set_lane_link_training(dp,
dp->link_train.training_lane[lane], lane); dp->link_train.training_lane[lane], lane);
retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
lane_count, dp->link_train.training_lane); lane_count, dp->link_train.training_lane);
return retval; return retval;
} }
static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
u8 *bandwidth) u8 *bandwidth)
{ {
u8 data; u8 data;
/* /*
* For DP rev.1.1, Maximum link rate of Main Link lanes * For DP rev.1.1, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
* For DP rev.1.2, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
*/ */
exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
*bandwidth = data; *bandwidth = data;
} }
static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
u8 *lane_count) u8 *lane_count)
{ {
u8 data; u8 data;
...@@ -660,29 +666,30 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, ...@@ -660,29 +666,30 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
* For DP rev.1.1, Maximum number of Main Link lanes * For DP rev.1.1, Maximum number of Main Link lanes
* 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
*/ */
exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
*lane_count = DPCD_MAX_LANE_COUNT(data); *lane_count = DPCD_MAX_LANE_COUNT(data);
} }
static void exynos_dp_init_training(struct exynos_dp_device *dp, static void analogix_dp_init_training(struct analogix_dp_device *dp,
enum link_lane_count_type max_lane, enum link_lane_count_type max_lane,
enum link_rate_type max_rate) int max_rate)
{ {
/* /*
* MACRO_RST must be applied after the PLL_LOCK to avoid * MACRO_RST must be applied after the PLL_LOCK to avoid
* the DP inter pair skew issue for at least 10 us * the DP inter pair skew issue for at least 10 us
*/ */
exynos_dp_reset_macro(dp); analogix_dp_reset_macro(dp);
/* Initialize by reading RX's DPCD */ /* Initialize by reading RX's DPCD */
exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
(dp->link_train.link_rate != DP_LINK_BW_5_4)) {
dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate); dp->link_train.link_rate);
dp->link_train.link_rate = LINK_RATE_1_62GBPS; dp->link_train.link_rate = DP_LINK_BW_1_62;
} }
if (dp->link_train.lane_count == 0) { if (dp->link_train.lane_count == 0) {
...@@ -698,10 +705,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp, ...@@ -698,10 +705,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
dp->link_train.link_rate = max_rate; dp->link_train.link_rate = max_rate;
/* All DP analog module power up */ /* All DP analog module power up */
exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
} }
static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
{ {
int retval = 0, training_finished = 0; int retval = 0, training_finished = 0;
...@@ -711,17 +718,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) ...@@ -711,17 +718,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
while (!retval && !training_finished) { while (!retval && !training_finished) {
switch (dp->link_train.lt_state) { switch (dp->link_train.lt_state) {
case START: case START:
retval = exynos_dp_link_start(dp); retval = analogix_dp_link_start(dp);
if (retval) if (retval)
dev_err(dp->dev, "LT link start failed!\n"); dev_err(dp->dev, "LT link start failed!\n");
break; break;
case CLOCK_RECOVERY: case CLOCK_RECOVERY:
retval = exynos_dp_process_clock_recovery(dp); retval = analogix_dp_process_clock_recovery(dp);
if (retval) if (retval)
dev_err(dp->dev, "LT CR failed!\n"); dev_err(dp->dev, "LT CR failed!\n");
break; break;
case EQUALIZER_TRAINING: case EQUALIZER_TRAINING:
retval = exynos_dp_process_equalizer_training(dp); retval = analogix_dp_process_equalizer_training(dp);
if (retval) if (retval)
dev_err(dp->dev, "LT EQ failed!\n"); dev_err(dp->dev, "LT EQ failed!\n");
break; break;
...@@ -738,16 +745,15 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) ...@@ -738,16 +745,15 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
return retval; return retval;
} }
static int exynos_dp_set_link_train(struct exynos_dp_device *dp, static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
u32 count, u32 count, u32 bwtype)
u32 bwtype)
{ {
int i; int i;
int retval; int retval;
for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
exynos_dp_init_training(dp, count, bwtype); analogix_dp_init_training(dp, count, bwtype);
retval = exynos_dp_sw_link_training(dp); retval = analogix_dp_sw_link_training(dp);
if (retval == 0) if (retval == 0)
break; break;
...@@ -757,26 +763,26 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp, ...@@ -757,26 +763,26 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
return retval; return retval;
} }
static int exynos_dp_config_video(struct exynos_dp_device *dp) static int analogix_dp_config_video(struct analogix_dp_device *dp)
{ {
int retval = 0; int retval = 0;
int timeout_loop = 0; int timeout_loop = 0;
int done_count = 0; int done_count = 0;
exynos_dp_config_video_slave_mode(dp); analogix_dp_config_video_slave_mode(dp);
exynos_dp_set_video_color_format(dp); analogix_dp_set_video_color_format(dp);
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
dev_err(dp->dev, "PLL is not locked yet.\n"); dev_err(dp->dev, "PLL is not locked yet.\n");
return -EINVAL; return -EINVAL;
} }
for (;;) { for (;;) {
timeout_loop++; timeout_loop++;
if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0) if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
break; break;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Timeout of video streamclk ok\n"); dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -785,29 +791,29 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp) ...@@ -785,29 +791,29 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
} }
/* Set to use the register calculated M/N video */ /* Set to use the register calculated M/N video */
exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
/* For video bist, Video timing must be generated by register */ /* For video bist, Video timing must be generated by register */
exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
/* Disable video mute */ /* Disable video mute */
exynos_dp_enable_video_mute(dp, 0); analogix_dp_enable_video_mute(dp, 0);
/* Configure video slave mode */ /* Configure video slave mode */
exynos_dp_enable_video_master(dp, 0); analogix_dp_enable_video_master(dp, 0);
timeout_loop = 0; timeout_loop = 0;
for (;;) { for (;;) {
timeout_loop++; timeout_loop++;
if (exynos_dp_is_video_stream_on(dp) == 0) { if (analogix_dp_is_video_stream_on(dp) == 0) {
done_count++; done_count++;
if (done_count > 10) if (done_count > 10)
break; break;
} else if (done_count) { } else if (done_count) {
done_count = 0; done_count = 0;
} }
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Timeout of video streamclk ok\n"); dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -821,313 +827,355 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp) ...@@ -821,313 +827,355 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
return retval; return retval;
} }
static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
bool enable)
{ {
u8 data; u8 data;
if (enable) { if (enable) {
exynos_dp_enable_scrambling(dp); analogix_dp_enable_scrambling(dp);
exynos_dp_read_byte_from_dpcd(dp, analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_SET, &data);
&data); analogix_dp_write_byte_to_dpcd(dp,
exynos_dp_write_byte_to_dpcd(dp,
DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_SET,
(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
} else { } else {
exynos_dp_disable_scrambling(dp); analogix_dp_disable_scrambling(dp);
exynos_dp_read_byte_from_dpcd(dp, analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_SET, &data);
&data); analogix_dp_write_byte_to_dpcd(dp,
exynos_dp_write_byte_to_dpcd(dp,
DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_SET,
(u8)(data | DP_LINK_SCRAMBLING_DISABLE)); (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
} }
} }
static irqreturn_t exynos_dp_irq_handler(int irq, void *arg) static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
{ {
struct exynos_dp_device *dp = arg; struct analogix_dp_device *dp = arg;
irqreturn_t ret = IRQ_NONE;
enum dp_irq_type irq_type; enum dp_irq_type irq_type;
irq_type = exynos_dp_get_irq_type(dp); irq_type = analogix_dp_get_irq_type(dp);
switch (irq_type) { if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
case DP_IRQ_TYPE_HP_CABLE_IN: analogix_dp_mute_hpd_interrupt(dp);
dev_dbg(dp->dev, "Received irq - cable in\n"); ret = IRQ_WAKE_THREAD;
schedule_work(&dp->hotplug_work);
exynos_dp_clear_hotplug_interrupts(dp);
break;
case DP_IRQ_TYPE_HP_CABLE_OUT:
dev_dbg(dp->dev, "Received irq - cable out\n");
exynos_dp_clear_hotplug_interrupts(dp);
break;
case DP_IRQ_TYPE_HP_CHANGE:
/*
* We get these change notifications once in a while, but there
* is nothing we can do with them. Just ignore it for now and
* only handle cable changes.
*/
dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
exynos_dp_clear_hotplug_interrupts(dp);
break;
default:
dev_err(dp->dev, "Received irq - unknown type!\n");
break;
} }
return IRQ_HANDLED;
return ret;
} }
static void exynos_dp_hotplug(struct work_struct *work) static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
{ {
struct exynos_dp_device *dp; struct analogix_dp_device *dp = arg;
enum dp_irq_type irq_type;
irq_type = analogix_dp_get_irq_type(dp);
if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
dev_dbg(dp->dev, "Detected cable status changed!\n");
if (dp->drm_dev)
drm_helper_hpd_irq_event(dp->drm_dev);
}
dp = container_of(work, struct exynos_dp_device, hotplug_work); if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
analogix_dp_clear_hotplug_interrupts(dp);
analogix_dp_unmute_hpd_interrupt(dp);
}
if (dp->drm_dev) return IRQ_HANDLED;
drm_helper_hpd_irq_event(dp->drm_dev);
} }
static void exynos_dp_commit(struct drm_encoder *encoder) static void analogix_dp_commit(struct analogix_dp_device *dp)
{ {
struct exynos_dp_device *dp = encoder_to_dp(encoder);
int ret; int ret;
/* Keep the panel disabled while we configure video */ /* Keep the panel disabled while we configure video */
if (dp->panel) { if (dp->plat_data->panel) {
if (drm_panel_disable(dp->panel)) if (drm_panel_disable(dp->plat_data->panel))
DRM_ERROR("failed to disable the panel\n"); DRM_ERROR("failed to disable the panel\n");
} }
ret = exynos_dp_detect_hpd(dp); ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
if (ret) { dp->video_info.max_link_rate);
/* Cable has been disconnected, we're done */
return;
}
ret = exynos_dp_handle_edid(dp);
if (ret) {
dev_err(dp->dev, "unable to handle edid\n");
return;
}
ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
dp->video_info->link_rate);
if (ret) { if (ret) {
dev_err(dp->dev, "unable to do link train\n"); dev_err(dp->dev, "unable to do link train\n");
return; return;
} }
exynos_dp_enable_scramble(dp, 1); analogix_dp_enable_scramble(dp, 1);
exynos_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
exynos_dp_enable_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1);
exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
exynos_dp_init_video(dp); analogix_dp_init_video(dp);
ret = exynos_dp_config_video(dp); ret = analogix_dp_config_video(dp);
if (ret) if (ret)
dev_err(dp->dev, "unable to config video\n"); dev_err(dp->dev, "unable to config video\n");
/* Safe to enable the panel now */ /* Safe to enable the panel now */
if (dp->panel) { if (dp->plat_data->panel) {
if (drm_panel_enable(dp->panel)) if (drm_panel_enable(dp->plat_data->panel))
DRM_ERROR("failed to enable the panel\n"); DRM_ERROR("failed to enable the panel\n");
} }
/* Enable video */ /* Enable video */
exynos_dp_start_video(dp); analogix_dp_start_video(dp);
} }
static enum drm_connector_status exynos_dp_detect( int analogix_dp_get_modes(struct drm_connector *connector)
struct drm_connector *connector, bool force)
{ {
return connector_status_connected; struct analogix_dp_device *dp = to_dp(connector);
} struct edid *edid = (struct edid *)dp->edid;
int num_modes = 0;
static void exynos_dp_connector_destroy(struct drm_connector *connector) if (analogix_dp_handle_edid(dp) == 0) {
{ drm_mode_connector_update_edid_property(&dp->connector, edid);
drm_connector_unregister(connector); num_modes += drm_add_edid_modes(&dp->connector, edid);
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs exynos_dp_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.detect = exynos_dp_detect,
.destroy = exynos_dp_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static int exynos_dp_get_modes(struct drm_connector *connector)
{
struct exynos_dp_device *dp = ctx_from_connector(connector);
struct drm_display_mode *mode;
if (dp->panel)
return drm_panel_get_modes(dp->panel);
mode = drm_mode_create(connector->dev);
if (!mode) {
DRM_ERROR("failed to create a new display mode.\n");
return 0;
} }
drm_display_mode_from_videomode(&dp->vm, mode); if (dp->plat_data->panel)
connector->display_info.width_mm = mode->width_mm; num_modes += drm_panel_get_modes(dp->plat_data->panel);
connector->display_info.height_mm = mode->height_mm;
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; if (dp->plat_data->get_modes)
drm_mode_set_name(mode); num_modes += dp->plat_data->get_modes(dp->plat_data);
drm_mode_probed_add(connector, mode);
return 1; return num_modes;
} }
static struct drm_encoder *exynos_dp_best_encoder( static struct drm_encoder *
struct drm_connector *connector) analogix_dp_best_encoder(struct drm_connector *connector)
{ {
struct exynos_dp_device *dp = ctx_from_connector(connector); struct analogix_dp_device *dp = to_dp(connector);
return &dp->encoder; return dp->encoder;
} }
static const struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = { static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
.get_modes = exynos_dp_get_modes, .get_modes = analogix_dp_get_modes,
.best_encoder = exynos_dp_best_encoder, .best_encoder = analogix_dp_best_encoder,
}; };
/* returns the number of bridges attached */ enum drm_connector_status
static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp, analogix_dp_detect(struct drm_connector *connector, bool force)
struct drm_encoder *encoder)
{ {
int ret; struct analogix_dp_device *dp = to_dp(connector);
encoder->bridge->next = dp->ptn_bridge; if (analogix_dp_detect_hpd(dp))
dp->ptn_bridge->encoder = encoder; return connector_status_disconnected;
ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
if (ret) {
DRM_ERROR("Failed to attach bridge to drm\n");
return ret;
}
return 0; return connector_status_connected;
} }
static int exynos_dp_bridge_attach(struct drm_bridge *bridge) static void analogix_dp_connector_destroy(struct drm_connector *connector)
{ {
struct exynos_dp_device *dp = bridge->driver_private; drm_connector_unregister(connector);
struct drm_encoder *encoder = &dp->encoder; drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs analogix_dp_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.detect = analogix_dp_detect,
.destroy = analogix_dp_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
{
struct analogix_dp_device *dp = bridge->driver_private;
struct drm_encoder *encoder = dp->encoder;
struct drm_connector *connector = &dp->connector; struct drm_connector *connector = &dp->connector;
int ret; int ret;
/* Pre-empt DP connector creation if there's a bridge */ if (!bridge->encoder) {
if (dp->ptn_bridge) { DRM_ERROR("Parent encoder object not found");
ret = exynos_drm_attach_lcd_bridge(dp, encoder); return -ENODEV;
if (!ret)
return 0;
} }
connector->polled = DRM_CONNECTOR_POLL_HPD; connector->polled = DRM_CONNECTOR_POLL_HPD;
ret = drm_connector_init(dp->drm_dev, connector, ret = drm_connector_init(dp->drm_dev, connector,
&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP); &analogix_dp_connector_funcs,
DRM_MODE_CONNECTOR_eDP);
if (ret) { if (ret) {
DRM_ERROR("Failed to initialize connector with drm\n"); DRM_ERROR("Failed to initialize connector with drm\n");
return ret; return ret;
} }
drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs); drm_connector_helper_add(connector,
drm_connector_register(connector); &analogix_dp_connector_helper_funcs);
drm_mode_connector_attach_encoder(connector, encoder); drm_mode_connector_attach_encoder(connector, encoder);
if (dp->panel) /*
ret = drm_panel_attach(dp->panel, &dp->connector); * NOTE: the connector registration is implemented in analogix
* platform driver, that to say connector would be exist after
* plat_data->attch return, that's why we record the connector
* point after plat attached.
*/
if (dp->plat_data->attach) {
ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
if (ret) {
DRM_ERROR("Failed at platform attch func\n");
return ret;
}
}
if (dp->plat_data->panel) {
ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
if (ret) {
DRM_ERROR("Failed to attach panel\n");
return ret;
}
}
return ret; return 0;
} }
static void exynos_dp_bridge_enable(struct drm_bridge *bridge) static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
{ {
struct exynos_dp_device *dp = bridge->driver_private; struct analogix_dp_device *dp = bridge->driver_private;
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
if (dp->dpms_mode == DRM_MODE_DPMS_ON) if (dp->dpms_mode == DRM_MODE_DPMS_ON)
return; return;
pm_runtime_get_sync(dp->dev); pm_runtime_get_sync(dp->dev);
if (dp->panel) { if (dp->plat_data->power_on)
if (drm_panel_prepare(dp->panel)) { dp->plat_data->power_on(dp->plat_data);
DRM_ERROR("failed to setup the panel\n");
return;
}
}
if (crtc->ops->clock_enable)
crtc->ops->clock_enable(dp_to_crtc(dp), true);
phy_power_on(dp->phy); phy_power_on(dp->phy);
exynos_dp_init_dp(dp); analogix_dp_init_dp(dp);
enable_irq(dp->irq); enable_irq(dp->irq);
exynos_dp_commit(&dp->encoder); analogix_dp_commit(dp);
dp->dpms_mode = DRM_MODE_DPMS_ON; dp->dpms_mode = DRM_MODE_DPMS_ON;
} }
static void exynos_dp_bridge_disable(struct drm_bridge *bridge) static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
{ {
struct exynos_dp_device *dp = bridge->driver_private; struct analogix_dp_device *dp = bridge->driver_private;
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
if (dp->dpms_mode != DRM_MODE_DPMS_ON) if (dp->dpms_mode != DRM_MODE_DPMS_ON)
return; return;
if (dp->panel) { if (dp->plat_data->panel) {
if (drm_panel_disable(dp->panel)) { if (drm_panel_disable(dp->plat_data->panel)) {
DRM_ERROR("failed to disable the panel\n"); DRM_ERROR("failed to disable the panel\n");
return; return;
} }
} }
disable_irq(dp->irq); disable_irq(dp->irq);
flush_work(&dp->hotplug_work);
phy_power_off(dp->phy); phy_power_off(dp->phy);
if (crtc->ops->clock_enable) if (dp->plat_data->power_off)
crtc->ops->clock_enable(dp_to_crtc(dp), false); dp->plat_data->power_off(dp->plat_data);
if (dp->panel) {
if (drm_panel_unprepare(dp->panel))
DRM_ERROR("failed to turnoff the panel\n");
}
pm_runtime_put_sync(dp->dev); pm_runtime_put_sync(dp->dev);
dp->dpms_mode = DRM_MODE_DPMS_OFF; dp->dpms_mode = DRM_MODE_DPMS_OFF;
} }
static void exynos_dp_bridge_nop(struct drm_bridge *bridge) static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *orig_mode,
struct drm_display_mode *mode)
{
struct analogix_dp_device *dp = bridge->driver_private;
struct drm_display_info *display_info = &dp->connector.display_info;
struct video_info *video = &dp->video_info;
struct device_node *dp_node = dp->dev->of_node;
int vic;
/* Input video interlaces & hsync pol & vsync pol */
video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
/* Input video dynamic_range & colorimetry */
vic = drm_match_cea_mode(mode);
if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
(vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
video->dynamic_range = CEA;
video->ycbcr_coeff = COLOR_YCBCR601;
} else if (vic) {
video->dynamic_range = CEA;
video->ycbcr_coeff = COLOR_YCBCR709;
} else {
video->dynamic_range = VESA;
video->ycbcr_coeff = COLOR_YCBCR709;
}
/* Input vide bpc and color_formats */
switch (display_info->bpc) {
case 12:
video->color_depth = COLOR_12;
break;
case 10:
video->color_depth = COLOR_10;
break;
case 8:
video->color_depth = COLOR_8;
break;
case 6:
video->color_depth = COLOR_6;
break;
default:
video->color_depth = COLOR_8;
break;
}
if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
video->color_space = COLOR_YCBCR444;
else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
video->color_space = COLOR_YCBCR422;
else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
video->color_space = COLOR_RGB;
else
video->color_space = COLOR_RGB;
/*
* NOTE: those property parsing code is used for providing backward
* compatibility for samsung platform.
* Due to we used the "of_property_read_u32" interfaces, when this
* property isn't present, the "video_info" can keep the original
* values and wouldn't be modified.
*/
of_property_read_u32(dp_node, "samsung,color-space",
&video->color_space);
of_property_read_u32(dp_node, "samsung,dynamic-range",
&video->dynamic_range);
of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
&video->ycbcr_coeff);
of_property_read_u32(dp_node, "samsung,color-depth",
&video->color_depth);
if (of_property_read_bool(dp_node, "hsync-active-high"))
video->h_sync_polarity = true;
if (of_property_read_bool(dp_node, "vsync-active-high"))
video->v_sync_polarity = true;
if (of_property_read_bool(dp_node, "interlaced"))
video->interlaced = true;
}
static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
{ {
/* do nothing */ /* do nothing */
} }
static const struct drm_bridge_funcs exynos_dp_bridge_funcs = { static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
.enable = exynos_dp_bridge_enable, .enable = analogix_dp_bridge_enable,
.disable = exynos_dp_bridge_disable, .disable = analogix_dp_bridge_disable,
.pre_enable = exynos_dp_bridge_nop, .pre_enable = analogix_dp_bridge_nop,
.post_disable = exynos_dp_bridge_nop, .post_disable = analogix_dp_bridge_nop,
.attach = exynos_dp_bridge_attach, .mode_set = analogix_dp_bridge_mode_set,
.attach = analogix_dp_bridge_attach,
}; };
static int exynos_dp_create_connector(struct drm_encoder *encoder) static int analogix_dp_create_bridge(struct drm_device *drm_dev,
struct analogix_dp_device *dp)
{ {
struct exynos_dp_device *dp = encoder_to_dp(encoder);
struct drm_device *drm_dev = dp->drm_dev;
struct drm_bridge *bridge; struct drm_bridge *bridge;
int ret; int ret;
...@@ -1139,10 +1187,10 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder) ...@@ -1139,10 +1187,10 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
dp->bridge = bridge; dp->bridge = bridge;
encoder->bridge = bridge; dp->encoder->bridge = bridge;
bridge->driver_private = dp; bridge->driver_private = dp;
bridge->encoder = encoder; bridge->encoder = dp->encoder;
bridge->funcs = &exynos_dp_bridge_funcs; bridge->funcs = &analogix_dp_bridge_funcs;
ret = drm_bridge_attach(drm_dev, bridge); ret = drm_bridge_attach(drm_dev, bridge);
if (ret) { if (ret) {
...@@ -1153,116 +1201,68 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder) ...@@ -1153,116 +1201,68 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
return 0; return 0;
} }
static void exynos_dp_mode_set(struct drm_encoder *encoder, static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
}
static void exynos_dp_enable(struct drm_encoder *encoder)
{
}
static void exynos_dp_disable(struct drm_encoder *encoder)
{
}
static const struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
.mode_set = exynos_dp_mode_set,
.enable = exynos_dp_enable,
.disable = exynos_dp_disable,
};
static const struct drm_encoder_funcs exynos_dp_encoder_funcs = {
.destroy = drm_encoder_cleanup,
};
static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
{ {
struct device_node *dp_node = dev->of_node; struct device_node *dp_node = dp->dev->of_node;
struct video_info *dp_video_config; struct video_info *video_info = &dp->video_info;
dp_video_config = devm_kzalloc(dev, switch (dp->plat_data->dev_type) {
sizeof(*dp_video_config), GFP_KERNEL); case RK3288_DP:
if (!dp_video_config) /*
return ERR_PTR(-ENOMEM); * Like Rk3288 DisplayPort TRM indicate that "Main link
* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
dp_video_config->h_sync_polarity = */
of_property_read_bool(dp_node, "hsync-active-high"); video_info->max_link_rate = 0x0A;
video_info->max_lane_count = 0x04;
dp_video_config->v_sync_polarity = break;
of_property_read_bool(dp_node, "vsync-active-high"); case EXYNOS_DP:
/*
dp_video_config->interlaced = * NOTE: those property parseing code is used for
of_property_read_bool(dp_node, "interlaced"); * providing backward compatibility for samsung platform.
*/
if (of_property_read_u32(dp_node, "samsung,color-space", of_property_read_u32(dp_node, "samsung,link-rate",
&dp_video_config->color_space)) { &video_info->max_link_rate);
dev_err(dev, "failed to get color-space\n"); of_property_read_u32(dp_node, "samsung,lane-count",
return ERR_PTR(-EINVAL); &video_info->max_lane_count);
} break;
if (of_property_read_u32(dp_node, "samsung,dynamic-range",
&dp_video_config->dynamic_range)) {
dev_err(dev, "failed to get dynamic-range\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
&dp_video_config->ycbcr_coeff)) {
dev_err(dev, "failed to get ycbcr-coeff\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,color-depth",
&dp_video_config->color_depth)) {
dev_err(dev, "failed to get color-depth\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,link-rate",
&dp_video_config->link_rate)) {
dev_err(dev, "failed to get link-rate\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,lane-count",
&dp_video_config->lane_count)) {
dev_err(dev, "failed to get lane-count\n");
return ERR_PTR(-EINVAL);
} }
return dp_video_config;
}
static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
{
int ret;
ret = of_get_videomode(dp->dev->of_node, &dp->vm, OF_USE_NATIVE_MODE);
if (ret) {
DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
return ret;
}
return 0; return 0;
} }
static int exynos_dp_bind(struct device *dev, struct device *master, void *data) int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
struct analogix_dp_plat_data *plat_data)
{ {
struct exynos_dp_device *dp = dev_get_drvdata(dev);
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm_dev = data; struct analogix_dp_device *dp;
struct drm_encoder *encoder = &dp->encoder;
struct resource *res; struct resource *res;
unsigned int irq_flags; unsigned int irq_flags;
int pipe, ret = 0; int ret;
if (!plat_data) {
dev_err(dev, "Invalided input plat_data\n");
return -EINVAL;
}
dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
if (!dp)
return -ENOMEM;
dev_set_drvdata(dev, dp);
dp->dev = &pdev->dev; dp->dev = &pdev->dev;
dp->dpms_mode = DRM_MODE_DPMS_OFF; dp->dpms_mode = DRM_MODE_DPMS_OFF;
dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev); /*
if (IS_ERR(dp->video_info)) * platform dp driver need containor_of the plat_data to get
return PTR_ERR(dp->video_info); * the driver private data, so we need to store the point of
* plat_data, not the context of plat_data.
*/
dp->plat_data = plat_data;
ret = analogix_dp_dt_parse_pdata(dp);
if (ret)
return ret;
dp->phy = devm_phy_get(dp->dev, "dp"); dp->phy = devm_phy_get(dp->dev, "dp");
if (IS_ERR(dp->phy)) { if (IS_ERR(dp->phy)) {
...@@ -1280,12 +1280,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data) ...@@ -1280,12 +1280,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
} }
} }
if (!dp->panel && !dp->ptn_bridge) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
return ret;
}
dp->clock = devm_clk_get(&pdev->dev, "dp"); dp->clock = devm_clk_get(&pdev->dev, "dp");
if (IS_ERR(dp->clock)) { if (IS_ERR(dp->clock)) {
dev_err(&pdev->dev, "failed to get clock\n"); dev_err(&pdev->dev, "failed to get clock\n");
...@@ -1300,7 +1294,12 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data) ...@@ -1300,7 +1294,12 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
if (IS_ERR(dp->reg_base)) if (IS_ERR(dp->reg_base))
return PTR_ERR(dp->reg_base); return PTR_ERR(dp->reg_base);
dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0); dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
if (!gpio_is_valid(dp->hpd_gpio))
dp->hpd_gpio = of_get_named_gpio(dev->of_node,
"samsung,hpd-gpio", 0);
if (gpio_is_valid(dp->hpd_gpio)) { if (gpio_is_valid(dp->hpd_gpio)) {
/* /*
...@@ -1329,138 +1328,83 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data) ...@@ -1329,138 +1328,83 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
return -ENODEV; return -ENODEV;
} }
INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug); pm_runtime_enable(dev);
phy_power_on(dp->phy);
if (dp->plat_data->panel) {
if (drm_panel_prepare(dp->plat_data->panel)) {
DRM_ERROR("failed to setup the panel\n");
return -EBUSY;
}
}
analogix_dp_init_dp(dp);
ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
irq_flags, "exynos-dp", dp); analogix_dp_hardirq,
analogix_dp_irq_thread,
irq_flags, "analogix-dp", dp);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to request irq\n"); dev_err(&pdev->dev, "failed to request irq\n");
return ret; goto err_disable_pm_runtime;
} }
disable_irq(dp->irq); disable_irq(dp->irq);
dp->drm_dev = drm_dev; dp->drm_dev = drm_dev;
dp->encoder = dp->plat_data->encoder;
pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev, ret = analogix_dp_create_bridge(drm_dev, dp);
EXYNOS_DISPLAY_TYPE_LCD);
if (pipe < 0)
return pipe;
encoder->possible_crtcs = 1 << pipe;
DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
ret = exynos_dp_create_connector(encoder);
if (ret) { if (ret) {
DRM_ERROR("failed to create connector ret = %d\n", ret); DRM_ERROR("failed to create bridge (%d)\n", ret);
drm_encoder_cleanup(encoder); drm_encoder_cleanup(dp->encoder);
return ret; goto err_disable_pm_runtime;
} }
return 0; return 0;
}
static void exynos_dp_unbind(struct device *dev, struct device *master, err_disable_pm_runtime:
void *data) pm_runtime_disable(dev);
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
exynos_dp_disable(&dp->encoder); return ret;
} }
EXPORT_SYMBOL_GPL(analogix_dp_bind);
static const struct component_ops exynos_dp_ops = { void analogix_dp_unbind(struct device *dev, struct device *master,
.bind = exynos_dp_bind, void *data)
.unbind = exynos_dp_unbind,
};
static int exynos_dp_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev; struct analogix_dp_device *dp = dev_get_drvdata(dev);
struct device_node *np = NULL, *endpoint = NULL;
struct exynos_dp_device *dp;
int ret;
dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device), analogix_dp_bridge_disable(dp->bridge);
GFP_KERNEL);
if (!dp)
return -ENOMEM;
platform_set_drvdata(pdev, dp); if (dp->plat_data->panel) {
if (drm_panel_unprepare(dp->plat_data->panel))
/* This is for the backward compatibility. */ DRM_ERROR("failed to turnoff the panel\n");
np = of_parse_phandle(dev->of_node, "panel", 0);
if (np) {
dp->panel = of_drm_find_panel(np);
of_node_put(np);
if (!dp->panel)
return -EPROBE_DEFER;
goto out;
}
endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
if (endpoint) {
np = of_graph_get_remote_port_parent(endpoint);
if (np) {
/* The remote port can be either a panel or a bridge */
dp->panel = of_drm_find_panel(np);
if (!dp->panel) {
dp->ptn_bridge = of_drm_find_bridge(np);
if (!dp->ptn_bridge) {
of_node_put(np);
return -EPROBE_DEFER;
}
}
of_node_put(np);
} else {
DRM_ERROR("no remote endpoint device node found.\n");
return -EINVAL;
}
} else {
DRM_ERROR("no port endpoint subnode found.\n");
return -EINVAL;
} }
out:
pm_runtime_enable(dev);
ret = component_add(&pdev->dev, &exynos_dp_ops);
if (ret)
goto err_disable_pm_runtime;
return ret;
err_disable_pm_runtime:
pm_runtime_disable(dev); pm_runtime_disable(dev);
return ret;
}
static int exynos_dp_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
component_del(&pdev->dev, &exynos_dp_ops);
return 0;
} }
EXPORT_SYMBOL_GPL(analogix_dp_unbind);
#ifdef CONFIG_PM #ifdef CONFIG_PM
static int exynos_dp_suspend(struct device *dev) int analogix_dp_suspend(struct device *dev)
{ {
struct exynos_dp_device *dp = dev_get_drvdata(dev); struct analogix_dp_device *dp = dev_get_drvdata(dev);
clk_disable_unprepare(dp->clock); clk_disable_unprepare(dp->clock);
if (dp->plat_data->panel) {
if (drm_panel_unprepare(dp->plat_data->panel))
DRM_ERROR("failed to turnoff the panel\n");
}
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(analogix_dp_suspend);
static int exynos_dp_resume(struct device *dev) int analogix_dp_resume(struct device *dev)
{ {
struct exynos_dp_device *dp = dev_get_drvdata(dev); struct analogix_dp_device *dp = dev_get_drvdata(dev);
int ret; int ret;
ret = clk_prepare_enable(dp->clock); ret = clk_prepare_enable(dp->clock);
...@@ -1469,31 +1413,18 @@ static int exynos_dp_resume(struct device *dev) ...@@ -1469,31 +1413,18 @@ static int exynos_dp_resume(struct device *dev)
return ret; return ret;
} }
if (dp->plat_data->panel) {
if (drm_panel_prepare(dp->plat_data->panel)) {
DRM_ERROR("failed to setup the panel\n");
return -EBUSY;
}
}
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(analogix_dp_resume);
#endif #endif
static const struct dev_pm_ops exynos_dp_pm_ops = {
SET_RUNTIME_PM_OPS(exynos_dp_suspend, exynos_dp_resume, NULL)
};
static const struct of_device_id exynos_dp_match[] = {
{ .compatible = "samsung,exynos5-dp" },
{},
};
MODULE_DEVICE_TABLE(of, exynos_dp_match);
struct platform_driver dp_driver = {
.probe = exynos_dp_probe,
.remove = exynos_dp_remove,
.driver = {
.name = "exynos-dp",
.owner = THIS_MODULE,
.pm = &exynos_dp_pm_ops,
.of_match_table = exynos_dp_match,
},
};
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
MODULE_DESCRIPTION("Samsung SoC DP Driver"); MODULE_DESCRIPTION("Analogix DP Core Driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
/* /*
* Header file for Samsung DP (Display Port) interface driver. * Header file for Analogix DP (Display Port) core interface driver.
* *
* Copyright (C) 2012 Samsung Electronics Co., Ltd. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
...@@ -10,24 +10,37 @@ ...@@ -10,24 +10,37 @@
* option) any later version. * option) any later version.
*/ */
#ifndef _EXYNOS_DP_CORE_H #ifndef _ANALOGIX_DP_CORE_H
#define _EXYNOS_DP_CORE_H #define _ANALOGIX_DP_CORE_H
#include <drm/drm_crtc.h> #include <drm/drm_crtc.h>
#include <drm/drm_dp_helper.h> #include <drm/drm_dp_helper.h>
#include <drm/exynos_drm.h>
#include <video/videomode.h>
#include "exynos_drm_drv.h"
#define DP_TIMEOUT_LOOP_COUNT 100 #define DP_TIMEOUT_LOOP_COUNT 100
#define MAX_CR_LOOP 5 #define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5 #define MAX_EQ_LOOP 5
enum link_rate_type { /* I2C EDID Chip ID, Slave Address */
LINK_RATE_1_62GBPS = 0x06, #define I2C_EDID_DEVICE_ADDR 0x50
LINK_RATE_2_70GBPS = 0x0a #define I2C_E_EDID_DEVICE_ADDR 0x30
};
#define EDID_BLOCK_LENGTH 0x80
#define EDID_HEADER_PATTERN 0x00
#define EDID_EXTENSION_FLAG 0x7e
#define EDID_CHECKSUM 0x7f
/* DP_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
/* DP_LANE_COUNT_SET */
#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
/* DP_TRAINING_LANE0_SET */
#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
enum link_lane_count_type { enum link_lane_count_type {
LANE_COUNT1 = 1, LANE_COUNT1 = 1,
...@@ -132,8 +145,8 @@ struct video_info { ...@@ -132,8 +145,8 @@ struct video_info {
enum color_coefficient ycbcr_coeff; enum color_coefficient ycbcr_coeff;
enum color_depth color_depth; enum color_depth color_depth;
enum link_rate_type link_rate; int max_link_rate;
enum link_lane_count_type lane_count; enum link_lane_count_type max_lane_count;
}; };
struct link_train { struct link_train {
...@@ -147,136 +160,122 @@ struct link_train { ...@@ -147,136 +160,122 @@ struct link_train {
enum link_training_state lt_state; enum link_training_state lt_state;
}; };
struct exynos_dp_device { struct analogix_dp_device {
struct drm_encoder encoder; struct drm_encoder *encoder;
struct device *dev; struct device *dev;
struct drm_device *drm_dev; struct drm_device *drm_dev;
struct drm_connector connector; struct drm_connector connector;
struct drm_panel *panel;
struct drm_bridge *bridge; struct drm_bridge *bridge;
struct drm_bridge *ptn_bridge;
struct clk *clock; struct clk *clock;
unsigned int irq; unsigned int irq;
void __iomem *reg_base; void __iomem *reg_base;
struct video_info *video_info; struct video_info video_info;
struct link_train link_train; struct link_train link_train;
struct work_struct hotplug_work;
struct phy *phy; struct phy *phy;
int dpms_mode; int dpms_mode;
int hpd_gpio; int hpd_gpio;
struct videomode vm; bool force_hpd;
}; unsigned char edid[EDID_BLOCK_LENGTH * 2];
/* exynos_dp_reg.c */ struct analogix_dp_plat_data *plat_data;
void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable); };
void exynos_dp_stop_video(struct exynos_dp_device *dp);
void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
void exynos_dp_reset(struct exynos_dp_device *dp);
void exynos_dp_swreset(struct exynos_dp_device *dp);
void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
enum analog_power_block block,
bool enable);
void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
void exynos_dp_init_hpd(struct exynos_dp_device *dp);
enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
void exynos_dp_reset_aux(struct exynos_dp_device *dp);
void exynos_dp_init_aux(struct exynos_dp_device *dp);
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned char data);
int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned char *data);
int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr);
int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int *data);
int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int count,
unsigned char edid[]);
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
enum pattern_set pattern);
void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
u32 training_lane);
void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
u32 training_lane);
void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
u32 training_lane);
void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
u32 training_lane);
u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
void exynos_dp_reset_macro(struct exynos_dp_device *dp);
void exynos_dp_init_video(struct exynos_dp_device *dp);
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
enum clock_recovery_m_value_type type,
u32 m_value,
u32 n_value);
void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
void exynos_dp_start_video(struct exynos_dp_device *dp);
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
/* I2C EDID Chip ID, Slave Address */
#define I2C_EDID_DEVICE_ADDR 0x50
#define I2C_E_EDID_DEVICE_ADDR 0x30
#define EDID_BLOCK_LENGTH 0x80
#define EDID_HEADER_PATTERN 0x00
#define EDID_EXTENSION_FLAG 0x7e
#define EDID_CHECKSUM 0x7f
/* DP_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
/* DP_LANE_COUNT_SET */
#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
/* DP_TRAINING_LANE0_SET */
#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
#endif /* _EXYNOS_DP_CORE_H */ /* analogix_dp_reg.c */
void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
void analogix_dp_stop_video(struct analogix_dp_device *dp);
void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
void analogix_dp_reset(struct analogix_dp_device *dp);
void analogix_dp_swreset(struct analogix_dp_device *dp);
void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
enum analog_power_block block,
bool enable);
void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
void analogix_dp_init_hpd(struct analogix_dp_device *dp);
void analogix_dp_force_hpd(struct analogix_dp_device *dp);
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
void analogix_dp_reset_aux(struct analogix_dp_device *dp);
void analogix_dp_init_aux(struct analogix_dp_device *dp);
int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr,
unsigned char data);
int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr,
unsigned char *data);
int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr);
int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int *data);
int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int count,
unsigned char edid[]);
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
bool enable);
void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
enum pattern_set pattern);
void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
u32 level);
void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
u32 level);
void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
u32 level);
void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
u32 level);
void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
u32 training_lane);
void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
u32 training_lane);
void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
u32 training_lane);
void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
u32 training_lane);
u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
void analogix_dp_reset_macro(struct analogix_dp_device *dp);
void analogix_dp_init_video(struct analogix_dp_device *dp);
void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
enum clock_recovery_m_value_type type,
u32 m_value,
u32 n_value);
void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
bool enable);
void analogix_dp_start_video(struct analogix_dp_device *dp);
int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
#endif /* _ANALOGIX_DP_CORE_H */
/* /*
* Samsung DP (Display port) register interface driver. * Analogix DP (Display port) core register interface driver.
* *
* Copyright (C) 2012 Samsung Electronics Co., Ltd. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
...@@ -15,8 +15,10 @@ ...@@ -15,8 +15,10 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include "exynos_dp_core.h" #include <drm/bridge/analogix_dp.h>
#include "exynos_dp_reg.h"
#include "analogix_dp_core.h"
#include "analogix_dp_reg.h"
#define COMMON_INT_MASK_1 0 #define COMMON_INT_MASK_1 0
#define COMMON_INT_MASK_2 0 #define COMMON_INT_MASK_2 0
...@@ -24,263 +26,301 @@ ...@@ -24,263 +26,301 @@
#define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
#define INT_STA_MASK INT_HPD #define INT_STA_MASK INT_HPD
void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable) void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
{ {
u32 reg; u32 reg;
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
reg |= HDCP_VIDEO_MUTE; reg |= HDCP_VIDEO_MUTE;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
reg &= ~HDCP_VIDEO_MUTE; reg &= ~HDCP_VIDEO_MUTE;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
} }
} }
void exynos_dp_stop_video(struct exynos_dp_device *dp) void analogix_dp_stop_video(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
reg &= ~VIDEO_EN; reg &= ~VIDEO_EN;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
} }
void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable) void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
{ {
u32 reg; u32 reg;
if (enable) if (enable)
reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
else else
reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
} }
void exynos_dp_init_analog_param(struct exynos_dp_device *dp) void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = TX_TERMINAL_CTRL_50_OHM; reg = TX_TERMINAL_CTRL_50_OHM;
writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
reg = SEL_24M | TX_DVDD_BIT_1_0625V; reg = SEL_24M | TX_DVDD_BIT_1_0625V;
writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
}
reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
TX_CUR1_2X | TX_CUR_16_MA; TX_CUR1_2X | TX_CUR_16_MA;
writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
reg = CH3_AMP_400_MV | CH2_AMP_400_MV | reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
CH1_AMP_400_MV | CH0_AMP_400_MV; CH1_AMP_400_MV | CH0_AMP_400_MV;
writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
} }
void exynos_dp_init_interrupt(struct exynos_dp_device *dp) void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
{ {
/* Set interrupt pin assertion polarity as high */ /* Set interrupt pin assertion polarity as high */
writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
/* Clear pending regisers */ /* Clear pending regisers */
writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2); writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3); writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA); writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
/* 0:mask,1: unmask */ /* 0:mask,1: unmask */
writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK); writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
} }
void exynos_dp_reset(struct exynos_dp_device *dp) void analogix_dp_reset(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
exynos_dp_stop_video(dp); analogix_dp_stop_video(dp);
exynos_dp_enable_video_mute(dp, 0); analogix_dp_enable_video_mute(dp, 0);
reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
HDCP_FUNC_EN_N | SW_FUNC_EN_N; HDCP_FUNC_EN_N | SW_FUNC_EN_N;
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
SERDES_FIFO_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N |
LS_CLK_DOMAIN_FUNC_EN_N; LS_CLK_DOMAIN_FUNC_EN_N;
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
usleep_range(20, 30); usleep_range(20, 30);
exynos_dp_lane_swap(dp, 0); analogix_dp_lane_swap(dp, 0);
writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2); writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3); writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4); writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL); writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL); writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L); writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H); writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL); writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST); writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD); writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN); writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH); writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
} }
void exynos_dp_swreset(struct exynos_dp_device *dp) void analogix_dp_swreset(struct analogix_dp_device *dp)
{ {
writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET); writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
} }
void exynos_dp_config_interrupt(struct exynos_dp_device *dp) void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
/* 0: mask, 1: unmask */ /* 0: mask, 1: unmask */
reg = COMMON_INT_MASK_1; reg = COMMON_INT_MASK_1;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
reg = COMMON_INT_MASK_2; reg = COMMON_INT_MASK_2;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
reg = COMMON_INT_MASK_3; reg = COMMON_INT_MASK_3;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
reg = COMMON_INT_MASK_4;
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
reg = INT_STA_MASK;
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
}
void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
{
u32 reg;
/* 0: mask, 1: unmask */
reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
reg &= ~COMMON_INT_MASK_4;
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
reg &= ~INT_STA_MASK;
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
}
void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
{
u32 reg;
/* 0: mask, 1: unmask */
reg = COMMON_INT_MASK_4; reg = COMMON_INT_MASK_4;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
reg = INT_STA_MASK; reg = INT_STA_MASK;
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
} }
enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp) enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
if (reg & PLL_LOCK) if (reg & PLL_LOCK)
return PLL_LOCKED; return PLL_LOCKED;
else else
return PLL_UNLOCKED; return PLL_UNLOCKED;
} }
void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable) void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
{ {
u32 reg; u32 reg;
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
reg |= DP_PLL_PD; reg |= DP_PLL_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
reg &= ~DP_PLL_PD; reg &= ~DP_PLL_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
} }
} }
void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
enum analog_power_block block, enum analog_power_block block,
bool enable) bool enable)
{ {
u32 reg; u32 reg;
u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
phy_pd_addr = ANALOGIX_DP_PD;
switch (block) { switch (block) {
case AUX_BLOCK: case AUX_BLOCK:
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg |= AUX_PD; reg |= AUX_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~AUX_PD; reg &= ~AUX_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} }
break; break;
case CH0_BLOCK: case CH0_BLOCK:
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH0_PD; reg |= CH0_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH0_PD; reg &= ~CH0_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} }
break; break;
case CH1_BLOCK: case CH1_BLOCK:
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH1_PD; reg |= CH1_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH1_PD; reg &= ~CH1_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} }
break; break;
case CH2_BLOCK: case CH2_BLOCK:
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH2_PD; reg |= CH2_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH2_PD; reg &= ~CH2_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} }
break; break;
case CH3_BLOCK: case CH3_BLOCK:
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH3_PD; reg |= CH3_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH3_PD; reg &= ~CH3_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} }
break; break;
case ANALOG_TOTAL: case ANALOG_TOTAL:
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg |= DP_PHY_PD; reg |= DP_PHY_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~DP_PHY_PD; reg &= ~DP_PHY_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} }
break; break;
case POWER_ALL: case POWER_ALL:
if (enable) { if (enable) {
reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
CH1_PD | CH0_PD; CH1_PD | CH0_PD;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); writel(reg, dp->reg_base + phy_pd_addr);
} else { } else {
writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD); writel(0x00, dp->reg_base + phy_pd_addr);
} }
break; break;
default: default:
...@@ -288,25 +328,25 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, ...@@ -288,25 +328,25 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
} }
} }
void exynos_dp_init_analog_func(struct exynos_dp_device *dp) void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
int timeout_loop = 0; int timeout_loop = 0;
exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
reg = PLL_LOCK_CHG; reg = PLL_LOCK_CHG;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
/* Power up PLL */ /* Power up PLL */
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
exynos_dp_set_pll_power_down(dp, 0); analogix_dp_set_pll_power_down(dp, 0);
while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
timeout_loop++; timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get pll lock status\n"); dev_err(dp->dev, "failed to get pll lock status\n");
...@@ -317,13 +357,13 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp) ...@@ -317,13 +357,13 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
} }
/* Enable Serdes FIFO function and Link symbol clock domain module */ /* Enable Serdes FIFO function and Link symbol clock domain module */
reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
| AUX_FUNC_EN_N); | AUX_FUNC_EN_N);
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
} }
void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp) void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
...@@ -331,27 +371,36 @@ void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp) ...@@ -331,27 +371,36 @@ void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
return; return;
reg = HOTPLUG_CHG | HPD_LOST | PLUG; reg = HOTPLUG_CHG | HPD_LOST | PLUG;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
reg = INT_HPD; reg = INT_HPD;
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
} }
void exynos_dp_init_hpd(struct exynos_dp_device *dp) void analogix_dp_init_hpd(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
if (gpio_is_valid(dp->hpd_gpio)) if (gpio_is_valid(dp->hpd_gpio))
return; return;
exynos_dp_clear_hotplug_interrupts(dp); analogix_dp_clear_hotplug_interrupts(dp);
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
reg &= ~(F_HPD | HPD_CTRL); reg &= ~(F_HPD | HPD_CTRL);
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
}
void analogix_dp_force_hpd(struct analogix_dp_device *dp)
{
u32 reg;
reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
reg = (F_HPD | HPD_CTRL);
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
} }
enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp) enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
...@@ -363,7 +412,7 @@ enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp) ...@@ -363,7 +412,7 @@ enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
return DP_IRQ_TYPE_HP_CABLE_OUT; return DP_IRQ_TYPE_HP_CABLE_OUT;
} else { } else {
/* Parse hotplug interrupt status register */ /* Parse hotplug interrupt status register */
reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
if (reg & PLUG) if (reg & PLUG)
return DP_IRQ_TYPE_HP_CABLE_IN; return DP_IRQ_TYPE_HP_CABLE_IN;
...@@ -378,42 +427,48 @@ enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp) ...@@ -378,42 +427,48 @@ enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
} }
} }
void exynos_dp_reset_aux(struct exynos_dp_device *dp) void analogix_dp_reset_aux(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
/* Disable AUX channel module */ /* Disable AUX channel module */
reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
reg |= AUX_FUNC_EN_N; reg |= AUX_FUNC_EN_N;
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
} }
void exynos_dp_init_aux(struct exynos_dp_device *dp) void analogix_dp_init_aux(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
/* Clear inerrupts related to AUX channel */ /* Clear inerrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR; reg = RPLY_RECEIV | AUX_ERR;
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
exynos_dp_reset_aux(dp); analogix_dp_reset_aux(dp);
/* Disable AUX transaction H/W retry */ /* Disable AUX transaction H/W retry */
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)| if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL); AUX_HW_RETRY_COUNT_SEL(3) |
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
else
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
AUX_HW_RETRY_COUNT_SEL(0) |
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
reg = DEFER_CTRL_EN | DEFER_COUNT(1); reg = DEFER_CTRL_EN | DEFER_COUNT(1);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
/* Enable AUX channel module */ /* Enable AUX channel module */
reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
reg &= ~AUX_FUNC_EN_N; reg &= ~AUX_FUNC_EN_N;
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
} }
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp) int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
...@@ -421,7 +476,7 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp) ...@@ -421,7 +476,7 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
if (gpio_get_value(dp->hpd_gpio)) if (gpio_get_value(dp->hpd_gpio))
return 0; return 0;
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
if (reg & HPD_STATUS) if (reg & HPD_STATUS)
return 0; return 0;
} }
...@@ -429,50 +484,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp) ...@@ -429,50 +484,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
return -EINVAL; return -EINVAL;
} }
void exynos_dp_enable_sw_function(struct exynos_dp_device *dp) void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg &= ~SW_FUNC_EN_N; reg &= ~SW_FUNC_EN_N;
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
} }
int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp) int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
{ {
int reg; int reg;
int retval = 0; int retval = 0;
int timeout_loop = 0; int timeout_loop = 0;
/* Enable AUX CH operation */ /* Enable AUX CH operation */
reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
reg |= AUX_EN; reg |= AUX_EN;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
/* Is AUX CH command reply received? */ /* Is AUX CH command reply received? */
reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
while (!(reg & RPLY_RECEIV)) { while (!(reg & RPLY_RECEIV)) {
timeout_loop++; timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "AUX CH command reply failed!\n"); dev_err(dp->dev, "AUX CH command reply failed!\n");
return -ETIMEDOUT; return -ETIMEDOUT;
} }
reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
usleep_range(10, 11); usleep_range(10, 11);
} }
/* Clear interrupt source for AUX CH command reply */ /* Clear interrupt source for AUX CH command reply */
writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
/* Clear interrupt source for AUX CH access error */ /* Clear interrupt source for AUX CH access error */
reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
if (reg & AUX_ERR) { if (reg & AUX_ERR) {
writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA); writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
return -EREMOTEIO; return -EREMOTEIO;
} }
/* Check AUX CH error access status */ /* Check AUX CH error access status */
reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA); reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
if ((reg & AUX_STATUS_MASK) != 0) { if ((reg & AUX_STATUS_MASK) != 0) {
dev_err(dp->dev, "AUX CH error happens: %d\n\n", dev_err(dp->dev, "AUX CH error happens: %d\n\n",
reg & AUX_STATUS_MASK); reg & AUX_STATUS_MASK);
...@@ -482,9 +537,9 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp) ...@@ -482,9 +537,9 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
return retval; return retval;
} }
int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr, unsigned int reg_addr,
unsigned char data) unsigned char data)
{ {
u32 reg; u32 reg;
int i; int i;
...@@ -493,19 +548,19 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, ...@@ -493,19 +548,19 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
/* Clear AUX CH data buffer */ /* Clear AUX CH data buffer */
reg = BUF_CLR; reg = BUF_CLR;
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
/* Select DPCD device address */ /* Select DPCD device address */
reg = AUX_ADDR_7_0(reg_addr); reg = AUX_ADDR_7_0(reg_addr);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
reg = AUX_ADDR_15_8(reg_addr); reg = AUX_ADDR_15_8(reg_addr);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
reg = AUX_ADDR_19_16(reg_addr); reg = AUX_ADDR_19_16(reg_addr);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
/* Write data buffer */ /* Write data buffer */
reg = (unsigned int)data; reg = (unsigned int)data;
writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
/* /*
* Set DisplayPort transaction and write 1 byte * Set DisplayPort transaction and write 1 byte
...@@ -513,23 +568,22 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, ...@@ -513,23 +568,22 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
* If Bit 3 is 0, I2C transaction. * If Bit 3 is 0, I2C transaction.
*/ */
reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0) if (retval == 0)
break; break;
else
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
__func__);
} }
return retval; return retval;
} }
int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr, unsigned int reg_addr,
unsigned char *data) unsigned char *data)
{ {
u32 reg; u32 reg;
int i; int i;
...@@ -538,15 +592,15 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, ...@@ -538,15 +592,15 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
/* Clear AUX CH data buffer */ /* Clear AUX CH data buffer */
reg = BUF_CLR; reg = BUF_CLR;
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
/* Select DPCD device address */ /* Select DPCD device address */
reg = AUX_ADDR_7_0(reg_addr); reg = AUX_ADDR_7_0(reg_addr);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
reg = AUX_ADDR_15_8(reg_addr); reg = AUX_ADDR_15_8(reg_addr);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
reg = AUX_ADDR_19_16(reg_addr); reg = AUX_ADDR_19_16(reg_addr);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
/* /*
* Set DisplayPort transaction and read 1 byte * Set DisplayPort transaction and read 1 byte
...@@ -554,28 +608,27 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, ...@@ -554,28 +608,27 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
* If Bit 3 is 0, I2C transaction. * If Bit 3 is 0, I2C transaction.
*/ */
reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0) if (retval == 0)
break; break;
else
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
__func__);
} }
/* Read data buffer */ /* Read data buffer */
reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
*data = (unsigned char)(reg & 0xff); *data = (unsigned char)(reg & 0xff);
return retval; return retval;
} }
int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr, unsigned int reg_addr,
unsigned int count, unsigned int count,
unsigned char data[]) unsigned char data[])
{ {
u32 reg; u32 reg;
unsigned int start_offset; unsigned int start_offset;
...@@ -586,7 +639,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, ...@@ -586,7 +639,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
/* Clear AUX CH data buffer */ /* Clear AUX CH data buffer */
reg = BUF_CLR; reg = BUF_CLR;
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
start_offset = 0; start_offset = 0;
while (start_offset < count) { while (start_offset < count) {
...@@ -599,17 +652,18 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, ...@@ -599,17 +652,18 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
/* Select DPCD device address */ /* Select DPCD device address */
reg = AUX_ADDR_7_0(reg_addr + start_offset); reg = AUX_ADDR_7_0(reg_addr + start_offset);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
reg = AUX_ADDR_15_8(reg_addr + start_offset); reg = AUX_ADDR_15_8(reg_addr + start_offset);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
reg = AUX_ADDR_19_16(reg_addr + start_offset); reg = AUX_ADDR_19_16(reg_addr + start_offset);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
for (cur_data_idx = 0; cur_data_idx < cur_data_count; for (cur_data_idx = 0; cur_data_idx < cur_data_count;
cur_data_idx++) { cur_data_idx++) {
reg = data[start_offset + cur_data_idx]; reg = data[start_offset + cur_data_idx];
writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 writel(reg, dp->reg_base +
+ 4 * cur_data_idx); ANALOGIX_DP_BUF_DATA_0 +
4 * cur_data_idx);
} }
/* /*
...@@ -619,15 +673,15 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, ...@@ -619,15 +673,15 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
*/ */
reg = AUX_LENGTH(cur_data_count) | reg = AUX_LENGTH(cur_data_count) |
AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0) if (retval == 0)
break; break;
else
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
__func__); __func__);
} }
start_offset += cur_data_count; start_offset += cur_data_count;
...@@ -636,10 +690,10 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, ...@@ -636,10 +690,10 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
return retval; return retval;
} }
int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
unsigned int reg_addr, unsigned int reg_addr,
unsigned int count, unsigned int count,
unsigned char data[]) unsigned char data[])
{ {
u32 reg; u32 reg;
unsigned int start_offset; unsigned int start_offset;
...@@ -650,7 +704,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, ...@@ -650,7 +704,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
/* Clear AUX CH data buffer */ /* Clear AUX CH data buffer */
reg = BUF_CLR; reg = BUF_CLR;
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
start_offset = 0; start_offset = 0;
while (start_offset < count) { while (start_offset < count) {
...@@ -664,11 +718,11 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, ...@@ -664,11 +718,11 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
/* Select DPCD device address */ /* Select DPCD device address */
reg = AUX_ADDR_7_0(reg_addr + start_offset); reg = AUX_ADDR_7_0(reg_addr + start_offset);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
reg = AUX_ADDR_15_8(reg_addr + start_offset); reg = AUX_ADDR_15_8(reg_addr + start_offset);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
reg = AUX_ADDR_19_16(reg_addr + start_offset); reg = AUX_ADDR_19_16(reg_addr + start_offset);
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
/* /*
* Set DisplayPort transaction and read * Set DisplayPort transaction and read
...@@ -677,20 +731,20 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, ...@@ -677,20 +731,20 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
*/ */
reg = AUX_LENGTH(cur_data_count) | reg = AUX_LENGTH(cur_data_count) |
AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0) if (retval == 0)
break; break;
else
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
__func__); __func__);
} }
for (cur_data_idx = 0; cur_data_idx < cur_data_count; for (cur_data_idx = 0; cur_data_idx < cur_data_count;
cur_data_idx++) { cur_data_idx++) {
reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+ 4 * cur_data_idx); + 4 * cur_data_idx);
data[start_offset + cur_data_idx] = data[start_offset + cur_data_idx] =
(unsigned char)reg; (unsigned char)reg;
...@@ -702,21 +756,21 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, ...@@ -702,21 +756,21 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
return retval; return retval;
} }
int exynos_dp_select_i2c_device(struct exynos_dp_device *dp, int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
unsigned int device_addr, unsigned int device_addr,
unsigned int reg_addr) unsigned int reg_addr)
{ {
u32 reg; u32 reg;
int retval; int retval;
/* Set EDID device address */ /* Set EDID device address */
reg = device_addr; reg = device_addr;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
/* Set offset from base address of EDID device */ /* Set offset from base address of EDID device */
writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0); writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
/* /*
* Set I2C transaction and write address * Set I2C transaction and write address
...@@ -725,20 +779,20 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp, ...@@ -725,20 +779,20 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
*/ */
reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
AUX_TX_COMM_WRITE; AUX_TX_COMM_WRITE;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval != 0) if (retval != 0)
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
return retval; return retval;
} }
int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
unsigned int device_addr, unsigned int device_addr,
unsigned int reg_addr, unsigned int reg_addr,
unsigned int *data) unsigned int *data)
{ {
u32 reg; u32 reg;
int i; int i;
...@@ -747,10 +801,11 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, ...@@ -747,10 +801,11 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
/* Clear AUX CH data buffer */ /* Clear AUX CH data buffer */
reg = BUF_CLR; reg = BUF_CLR;
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
/* Select EDID device */ /* Select EDID device */
retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr); retval = analogix_dp_select_i2c_device(dp, device_addr,
reg_addr);
if (retval != 0) if (retval != 0)
continue; continue;
...@@ -761,29 +816,28 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, ...@@ -761,29 +816,28 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
*/ */
reg = AUX_TX_COMM_I2C_TRANSACTION | reg = AUX_TX_COMM_I2C_TRANSACTION |
AUX_TX_COMM_READ; AUX_TX_COMM_READ;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0) if (retval == 0)
break; break;
else
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
__func__);
} }
/* Read data */ /* Read data */
if (retval == 0) if (retval == 0)
*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
return retval; return retval;
} }
int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
unsigned int device_addr, unsigned int device_addr,
unsigned int reg_addr, unsigned int reg_addr,
unsigned int count, unsigned int count,
unsigned char edid[]) unsigned char edid[])
{ {
u32 reg; u32 reg;
unsigned int i, j; unsigned int i, j;
...@@ -795,19 +849,19 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, ...@@ -795,19 +849,19 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
for (j = 0; j < 3; j++) { for (j = 0; j < 3; j++) {
/* Clear AUX CH data buffer */ /* Clear AUX CH data buffer */
reg = BUF_CLR; reg = BUF_CLR;
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
/* Set normal AUX CH command */ /* Set normal AUX CH command */
reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
reg &= ~ADDR_ONLY; reg &= ~ADDR_ONLY;
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
/* /*
* If Rx sends defer, Tx sends only reads * If Rx sends defer, Tx sends only reads
* request without sending address * request without sending address
*/ */
if (!defer) if (!defer)
retval = exynos_dp_select_i2c_device(dp, retval = analogix_dp_select_i2c_device(dp,
device_addr, reg_addr + i); device_addr, reg_addr + i);
else else
defer = 0; defer = 0;
...@@ -822,28 +876,27 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, ...@@ -822,28 +876,27 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_I2C_TRANSACTION |
AUX_TX_COMM_READ; AUX_TX_COMM_READ;
writel(reg, dp->reg_base + writel(reg, dp->reg_base +
EXYNOS_DP_AUX_CH_CTL_1); ANALOGIX_DP_AUX_CH_CTL_1);
/* Start AUX transaction */ /* Start AUX transaction */
retval = exynos_dp_start_aux_transaction(dp); retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0) if (retval == 0)
break; break;
else
dev_dbg(dp->dev, dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
"%s: Aux Transaction fail!\n", __func__);
__func__);
} }
/* Check if Rx sends defer */ /* Check if Rx sends defer */
reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
if (reg == AUX_RX_COMM_AUX_DEFER || if (reg == AUX_RX_COMM_AUX_DEFER ||
reg == AUX_RX_COMM_I2C_DEFER) { reg == AUX_RX_COMM_I2C_DEFER) {
dev_err(dp->dev, "Defer: %d\n\n", reg); dev_err(dp->dev, "Defer: %d\n\n", reg);
defer = 1; defer = 1;
} }
} }
for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+ 4 * cur_data_idx); + 4 * cur_data_idx);
edid[i + cur_data_idx] = (unsigned char)reg; edid[i + cur_data_idx] = (unsigned char)reg;
} }
...@@ -852,268 +905,273 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, ...@@ -852,268 +905,273 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
return retval; return retval;
} }
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype) void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
{ {
u32 reg; u32 reg;
reg = bwtype; reg = bwtype;
if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS)) if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
} }
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype) void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET); reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
*bwtype = reg; *bwtype = reg;
} }
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count) void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
{ {
u32 reg; u32 reg;
reg = count; reg = count;
writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
} }
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count) void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
*count = reg; *count = reg;
} }
void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable) void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
bool enable)
{ {
u32 reg; u32 reg;
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
reg |= ENHANCED; reg |= ENHANCED;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
reg &= ~ENHANCED; reg &= ~ENHANCED;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
} }
} }
void exynos_dp_set_training_pattern(struct exynos_dp_device *dp, void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
enum pattern_set pattern) enum pattern_set pattern)
{ {
u32 reg; u32 reg;
switch (pattern) { switch (pattern) {
case PRBS7: case PRBS7:
reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
break; break;
case D10_2: case D10_2:
reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
break; break;
case TRAINING_PTN1: case TRAINING_PTN1:
reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
break; break;
case TRAINING_PTN2: case TRAINING_PTN2:
reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
break; break;
case DP_NONE: case DP_NONE:
reg = SCRAMBLING_ENABLE | reg = SCRAMBLING_ENABLE |
LINK_QUAL_PATTERN_SET_DISABLE | LINK_QUAL_PATTERN_SET_DISABLE |
SW_TRAINING_PATTERN_SET_NORMAL; SW_TRAINING_PATTERN_SET_NORMAL;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
break; break;
default: default:
break; break;
} }
} }
void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level) void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
u32 level)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
reg &= ~PRE_EMPHASIS_SET_MASK; reg &= ~PRE_EMPHASIS_SET_MASK;
reg |= level << PRE_EMPHASIS_SET_SHIFT; reg |= level << PRE_EMPHASIS_SET_SHIFT;
writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level) void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
u32 level)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
reg &= ~PRE_EMPHASIS_SET_MASK; reg &= ~PRE_EMPHASIS_SET_MASK;
reg |= level << PRE_EMPHASIS_SET_SHIFT; reg |= level << PRE_EMPHASIS_SET_SHIFT;
writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level) void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
u32 level)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
reg &= ~PRE_EMPHASIS_SET_MASK; reg &= ~PRE_EMPHASIS_SET_MASK;
reg |= level << PRE_EMPHASIS_SET_SHIFT; reg |= level << PRE_EMPHASIS_SET_SHIFT;
writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level) void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
u32 level)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
reg &= ~PRE_EMPHASIS_SET_MASK; reg &= ~PRE_EMPHASIS_SET_MASK;
reg |= level << PRE_EMPHASIS_SET_SHIFT; reg |= level << PRE_EMPHASIS_SET_SHIFT;
writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp, void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
u32 training_lane) u32 training_lane)
{ {
u32 reg; u32 reg;
reg = training_lane; reg = training_lane;
writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp, void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
u32 training_lane) u32 training_lane)
{ {
u32 reg; u32 reg;
reg = training_lane; reg = training_lane;
writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp, void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
u32 training_lane) u32 training_lane)
{ {
u32 reg; u32 reg;
reg = training_lane; reg = training_lane;
writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
} }
void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp, void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
u32 training_lane) u32 training_lane)
{ {
u32 reg; u32 reg;
reg = training_lane; reg = training_lane;
writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
} }
u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp) u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
return reg; return reg;
} }
u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp) u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
return reg; return reg;
} }
u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp) u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
return reg; return reg;
} }
u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp) u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
return reg; return reg;
} }
void exynos_dp_reset_macro(struct exynos_dp_device *dp) void analogix_dp_reset_macro(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST); reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
reg |= MACRO_RST; reg |= MACRO_RST;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
/* 10 us is the minimum reset time. */ /* 10 us is the minimum reset time. */
usleep_range(10, 20); usleep_range(10, 20);
reg &= ~MACRO_RST; reg &= ~MACRO_RST;
writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
} }
void exynos_dp_init_video(struct exynos_dp_device *dp) void analogix_dp_init_video(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
reg = 0x0; reg = 0x0;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
reg = CHA_CRI(4) | CHA_CTRL; reg = CHA_CRI(4) | CHA_CTRL;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
reg = 0x0; reg = 0x0;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
reg = VID_HRES_TH(2) | VID_VRES_TH(0); reg = VID_HRES_TH(2) | VID_VRES_TH(0);
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
} }
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp) void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
/* Configure the input color depth, color space, dynamic range */ /* Configure the input color depth, color space, dynamic range */
reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) | reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
(dp->video_info->color_depth << IN_BPC_SHIFT) | (dp->video_info.color_depth << IN_BPC_SHIFT) |
(dp->video_info->color_space << IN_COLOR_F_SHIFT); (dp->video_info.color_space << IN_COLOR_F_SHIFT);
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
reg &= ~IN_YC_COEFFI_MASK; reg &= ~IN_YC_COEFFI_MASK;
if (dp->video_info->ycbcr_coeff) if (dp->video_info.ycbcr_coeff)
reg |= IN_YC_COEFFI_ITU709; reg |= IN_YC_COEFFI_ITU709;
else else
reg |= IN_YC_COEFFI_ITU601; reg |= IN_YC_COEFFI_ITU601;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
} }
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp) int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
if (!(reg & DET_STA)) { if (!(reg & DET_STA)) {
dev_dbg(dp->dev, "Input stream clock not detected.\n"); dev_dbg(dp->dev, "Input stream clock not detected.\n");
return -EINVAL; return -EINVAL;
} }
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
if (reg & CHA_STA) { if (reg & CHA_STA) {
...@@ -1124,90 +1182,89 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp) ...@@ -1124,90 +1182,89 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
return 0; return 0;
} }
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp, void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
enum clock_recovery_m_value_type type, enum clock_recovery_m_value_type type,
u32 m_value, u32 m_value, u32 n_value)
u32 n_value)
{ {
u32 reg; u32 reg;
if (type == REGISTER_M) { if (type == REGISTER_M) {
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
reg |= FIX_M_VID; reg |= FIX_M_VID;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
reg = m_value & 0xff; reg = m_value & 0xff;
writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
reg = (m_value >> 8) & 0xff; reg = (m_value >> 8) & 0xff;
writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
reg = (m_value >> 16) & 0xff; reg = (m_value >> 16) & 0xff;
writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
reg = n_value & 0xff; reg = n_value & 0xff;
writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
reg = (n_value >> 8) & 0xff; reg = (n_value >> 8) & 0xff;
writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
reg = (n_value >> 16) & 0xff; reg = (n_value >> 16) & 0xff;
writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
reg &= ~FIX_M_VID; reg &= ~FIX_M_VID;
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0); writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1); writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2); writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
} }
} }
void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type) void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
{ {
u32 reg; u32 reg;
if (type == VIDEO_TIMING_FROM_CAPTURE) { if (type == VIDEO_TIMING_FROM_CAPTURE) {
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~FORMAT_SEL; reg &= ~FORMAT_SEL;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg |= FORMAT_SEL; reg |= FORMAT_SEL;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
} }
} }
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable) void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
{ {
u32 reg; u32 reg;
if (enable) { if (enable) {
reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
reg &= ~VIDEO_MODE_MASK; reg &= ~VIDEO_MODE_MASK;
reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
} else { } else {
reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
reg &= ~VIDEO_MODE_MASK; reg &= ~VIDEO_MODE_MASK;
reg |= VIDEO_MODE_SLAVE_MODE; reg |= VIDEO_MODE_SLAVE_MODE;
writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
} }
} }
void exynos_dp_start_video(struct exynos_dp_device *dp) void analogix_dp_start_video(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
reg |= VIDEO_EN; reg |= VIDEO_EN;
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
} }
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp) int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
if (!(reg & STRM_VALID)) { if (!(reg & STRM_VALID)) {
dev_dbg(dp->dev, "Input video stream is not detected.\n"); dev_dbg(dp->dev, "Input video stream is not detected.\n");
return -EINVAL; return -EINVAL;
...@@ -1216,48 +1273,48 @@ int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp) ...@@ -1216,48 +1273,48 @@ int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
return 0; return 0;
} }
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp) void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
reg |= MASTER_VID_FUNC_EN_N; reg |= MASTER_VID_FUNC_EN_N;
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~INTERACE_SCAN_CFG; reg &= ~INTERACE_SCAN_CFG;
reg |= (dp->video_info->interlaced << 2); reg |= (dp->video_info.interlaced << 2);
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~VSYNC_POLARITY_CFG; reg &= ~VSYNC_POLARITY_CFG;
reg |= (dp->video_info->v_sync_polarity << 1); reg |= (dp->video_info.v_sync_polarity << 1);
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~HSYNC_POLARITY_CFG; reg &= ~HSYNC_POLARITY_CFG;
reg |= (dp->video_info->h_sync_polarity << 0); reg |= (dp->video_info.h_sync_polarity << 0);
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
} }
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp) void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
reg &= ~SCRAMBLING_DISABLE; reg &= ~SCRAMBLING_DISABLE;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
} }
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp) void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
reg |= SCRAMBLING_DISABLE; reg |= SCRAMBLING_DISABLE;
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
} }
/* /*
* Register definition file for Samsung DP driver * Register definition file for Analogix DP core driver
* *
* Copyright (C) 2012 Samsung Electronics Co., Ltd. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
...@@ -9,96 +9,104 @@ ...@@ -9,96 +9,104 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef _EXYNOS_DP_REG_H #ifndef _ANALOGIX_DP_REG_H
#define _EXYNOS_DP_REG_H #define _ANALOGIX_DP_REG_H
#define EXYNOS_DP_TX_SW_RESET 0x14 #define ANALOGIX_DP_TX_SW_RESET 0x14
#define EXYNOS_DP_FUNC_EN_1 0x18 #define ANALOGIX_DP_FUNC_EN_1 0x18
#define EXYNOS_DP_FUNC_EN_2 0x1C #define ANALOGIX_DP_FUNC_EN_2 0x1C
#define EXYNOS_DP_VIDEO_CTL_1 0x20 #define ANALOGIX_DP_VIDEO_CTL_1 0x20
#define EXYNOS_DP_VIDEO_CTL_2 0x24 #define ANALOGIX_DP_VIDEO_CTL_2 0x24
#define EXYNOS_DP_VIDEO_CTL_3 0x28 #define ANALOGIX_DP_VIDEO_CTL_3 0x28
#define EXYNOS_DP_VIDEO_CTL_8 0x3C #define ANALOGIX_DP_VIDEO_CTL_8 0x3C
#define EXYNOS_DP_VIDEO_CTL_10 0x44 #define ANALOGIX_DP_VIDEO_CTL_10 0x44
#define EXYNOS_DP_LANE_MAP 0x35C #define ANALOGIX_DP_PLL_REG_1 0xfc
#define ANALOGIX_DP_PLL_REG_2 0x9e4
#define EXYNOS_DP_ANALOG_CTL_1 0x370 #define ANALOGIX_DP_PLL_REG_3 0x9e8
#define EXYNOS_DP_ANALOG_CTL_2 0x374 #define ANALOGIX_DP_PLL_REG_4 0x9ec
#define EXYNOS_DP_ANALOG_CTL_3 0x378 #define ANALOGIX_DP_PLL_REG_5 0xa00
#define EXYNOS_DP_PLL_FILTER_CTL_1 0x37C
#define EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 #define ANALOGIX_DP_PD 0x12c
#define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 #define ANALOGIX_DP_LANE_MAP 0x35C
#define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 #define ANALOGIX_DP_ANALOG_CTL_1 0x370
#define EXYNOS_DP_COMMON_INT_STA_2 0x3C8 #define ANALOGIX_DP_ANALOG_CTL_2 0x374
#define EXYNOS_DP_COMMON_INT_STA_3 0x3CC #define ANALOGIX_DP_ANALOG_CTL_3 0x378
#define EXYNOS_DP_COMMON_INT_STA_4 0x3D0 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C
#define EXYNOS_DP_INT_STA 0x3DC #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380
#define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0
#define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390
#define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8
#define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4
#define EXYNOS_DP_INT_STA_MASK 0x3F8 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8
#define EXYNOS_DP_INT_CTL 0x3FC #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC
#define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0
#define EXYNOS_DP_SYS_CTL_1 0x600 #define ANALOGIX_DP_INT_STA 0x3DC
#define EXYNOS_DP_SYS_CTL_2 0x604 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0
#define EXYNOS_DP_SYS_CTL_3 0x608 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4
#define EXYNOS_DP_SYS_CTL_4 0x60C #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8
#define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC
#define EXYNOS_DP_PKT_SEND_CTL 0x640 #define ANALOGIX_DP_INT_STA_MASK 0x3F8
#define EXYNOS_DP_HDCP_CTL 0x648 #define ANALOGIX_DP_INT_CTL 0x3FC
#define EXYNOS_DP_LINK_BW_SET 0x680 #define ANALOGIX_DP_SYS_CTL_1 0x600
#define EXYNOS_DP_LANE_COUNT_SET 0x684 #define ANALOGIX_DP_SYS_CTL_2 0x604
#define EXYNOS_DP_TRAINING_PTN_SET 0x688 #define ANALOGIX_DP_SYS_CTL_3 0x608
#define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C #define ANALOGIX_DP_SYS_CTL_4 0x60C
#define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690
#define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694 #define ANALOGIX_DP_PKT_SEND_CTL 0x640
#define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698 #define ANALOGIX_DP_HDCP_CTL 0x648
#define EXYNOS_DP_DEBUG_CTL 0x6C0 #define ANALOGIX_DP_LINK_BW_SET 0x680
#define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4 #define ANALOGIX_DP_LANE_COUNT_SET 0x684
#define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688
#define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C
#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690
#define EXYNOS_DP_M_VID_0 0x700 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694
#define EXYNOS_DP_M_VID_1 0x704 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698
#define EXYNOS_DP_M_VID_2 0x708
#define EXYNOS_DP_N_VID_0 0x70C #define ANALOGIX_DP_DEBUG_CTL 0x6C0
#define EXYNOS_DP_N_VID_1 0x710 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4
#define EXYNOS_DP_N_VID_2 0x714 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8
#define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0
#define EXYNOS_DP_PLL_CTL 0x71C
#define EXYNOS_DP_PHY_PD 0x720 #define ANALOGIX_DP_M_VID_0 0x700
#define EXYNOS_DP_PHY_TEST 0x724 #define ANALOGIX_DP_M_VID_1 0x704
#define ANALOGIX_DP_M_VID_2 0x708
#define EXYNOS_DP_VIDEO_FIFO_THRD 0x730 #define ANALOGIX_DP_N_VID_0 0x70C
#define EXYNOS_DP_AUDIO_MARGIN 0x73C #define ANALOGIX_DP_N_VID_1 0x710
#define ANALOGIX_DP_N_VID_2 0x714
#define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764
#define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778 #define ANALOGIX_DP_PLL_CTL 0x71C
#define EXYNOS_DP_AUX_CH_STA 0x780 #define ANALOGIX_DP_PHY_PD 0x720
#define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788 #define ANALOGIX_DP_PHY_TEST 0x724
#define EXYNOS_DP_AUX_RX_COMM 0x78C
#define EXYNOS_DP_BUFFER_DATA_CTL 0x790 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730
#define EXYNOS_DP_AUX_CH_CTL_1 0x794 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C
#define EXYNOS_DP_AUX_ADDR_7_0 0x798
#define EXYNOS_DP_AUX_ADDR_15_8 0x79C #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764
#define EXYNOS_DP_AUX_ADDR_19_16 0x7A0 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778
#define EXYNOS_DP_AUX_CH_CTL_2 0x7A4 #define ANALOGIX_DP_AUX_CH_STA 0x780
#define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788
#define EXYNOS_DP_BUF_DATA_0 0x7C0 #define ANALOGIX_DP_AUX_RX_COMM 0x78C
#define ANALOGIX_DP_BUFFER_DATA_CTL 0x790
#define EXYNOS_DP_SOC_GENERAL_CTL 0x800 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794
#define ANALOGIX_DP_AUX_ADDR_7_0 0x798
/* EXYNOS_DP_TX_SW_RESET */ #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C
#define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0
#define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4
#define ANALOGIX_DP_BUF_DATA_0 0x7C0
#define ANALOGIX_DP_SOC_GENERAL_CTL 0x800
/* ANALOGIX_DP_TX_SW_RESET */
#define RESET_DP_TX (0x1 << 0) #define RESET_DP_TX (0x1 << 0)
/* EXYNOS_DP_FUNC_EN_1 */ /* ANALOGIX_DP_FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7) #define MASTER_VID_FUNC_EN_N (0x1 << 7)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5) #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4) #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
...@@ -107,17 +115,17 @@ ...@@ -107,17 +115,17 @@
#define CRC_FUNC_EN_N (0x1 << 1) #define CRC_FUNC_EN_N (0x1 << 1)
#define SW_FUNC_EN_N (0x1 << 0) #define SW_FUNC_EN_N (0x1 << 0)
/* EXYNOS_DP_FUNC_EN_2 */ /* ANALOGIX_DP_FUNC_EN_2 */
#define SSC_FUNC_EN_N (0x1 << 7) #define SSC_FUNC_EN_N (0x1 << 7)
#define AUX_FUNC_EN_N (0x1 << 2) #define AUX_FUNC_EN_N (0x1 << 2)
#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
/* EXYNOS_DP_VIDEO_CTL_1 */ /* ANALOGIX_DP_VIDEO_CTL_1 */
#define VIDEO_EN (0x1 << 7) #define VIDEO_EN (0x1 << 7)
#define HDCP_VIDEO_MUTE (0x1 << 6) #define HDCP_VIDEO_MUTE (0x1 << 6)
/* EXYNOS_DP_VIDEO_CTL_1 */ /* ANALOGIX_DP_VIDEO_CTL_1 */
#define IN_D_RANGE_MASK (0x1 << 7) #define IN_D_RANGE_MASK (0x1 << 7)
#define IN_D_RANGE_SHIFT (7) #define IN_D_RANGE_SHIFT (7)
#define IN_D_RANGE_CEA (0x1 << 7) #define IN_D_RANGE_CEA (0x1 << 7)
...@@ -134,7 +142,7 @@ ...@@ -134,7 +142,7 @@
#define IN_COLOR_F_YCBCR422 (0x1 << 0) #define IN_COLOR_F_YCBCR422 (0x1 << 0)
#define IN_COLOR_F_RGB (0x0 << 0) #define IN_COLOR_F_RGB (0x0 << 0)
/* EXYNOS_DP_VIDEO_CTL_3 */ /* ANALOGIX_DP_VIDEO_CTL_3 */
#define IN_YC_COEFFI_MASK (0x1 << 7) #define IN_YC_COEFFI_MASK (0x1 << 7)
#define IN_YC_COEFFI_SHIFT (7) #define IN_YC_COEFFI_SHIFT (7)
#define IN_YC_COEFFI_ITU709 (0x1 << 7) #define IN_YC_COEFFI_ITU709 (0x1 << 7)
...@@ -144,17 +152,21 @@ ...@@ -144,17 +152,21 @@
#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
/* EXYNOS_DP_VIDEO_CTL_8 */ /* ANALOGIX_DP_VIDEO_CTL_8 */
#define VID_HRES_TH(x) (((x) & 0xf) << 4) #define VID_HRES_TH(x) (((x) & 0xf) << 4)
#define VID_VRES_TH(x) (((x) & 0xf) << 0) #define VID_VRES_TH(x) (((x) & 0xf) << 0)
/* EXYNOS_DP_VIDEO_CTL_10 */ /* ANALOGIX_DP_VIDEO_CTL_10 */
#define FORMAT_SEL (0x1 << 4) #define FORMAT_SEL (0x1 << 4)
#define INTERACE_SCAN_CFG (0x1 << 2) #define INTERACE_SCAN_CFG (0x1 << 2)
#define VSYNC_POLARITY_CFG (0x1 << 1) #define VSYNC_POLARITY_CFG (0x1 << 1)
#define HSYNC_POLARITY_CFG (0x1 << 0) #define HSYNC_POLARITY_CFG (0x1 << 0)
/* EXYNOS_DP_LANE_MAP */ /* ANALOGIX_DP_PLL_REG_1 */
#define REF_CLK_24M (0x1 << 1)
#define REF_CLK_27M (0x0 << 1)
/* ANALOGIX_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
...@@ -172,30 +184,30 @@ ...@@ -172,30 +184,30 @@
#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
/* EXYNOS_DP_ANALOG_CTL_1 */ /* ANALOGIX_DP_ANALOG_CTL_1 */
#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
/* EXYNOS_DP_ANALOG_CTL_2 */ /* ANALOGIX_DP_ANALOG_CTL_2 */
#define SEL_24M (0x1 << 3) #define SEL_24M (0x1 << 3)
#define TX_DVDD_BIT_1_0625V (0x4 << 0) #define TX_DVDD_BIT_1_0625V (0x4 << 0)
/* EXYNOS_DP_ANALOG_CTL_3 */ /* ANALOGIX_DP_ANALOG_CTL_3 */
#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
#define VCO_BIT_600_MICRO (0x5 << 0) #define VCO_BIT_600_MICRO (0x5 << 0)
/* EXYNOS_DP_PLL_FILTER_CTL_1 */ /* ANALOGIX_DP_PLL_FILTER_CTL_1 */
#define PD_RING_OSC (0x1 << 6) #define PD_RING_OSC (0x1 << 6)
#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
#define TX_CUR1_2X (0x1 << 2) #define TX_CUR1_2X (0x1 << 2)
#define TX_CUR_16_MA (0x3 << 0) #define TX_CUR_16_MA (0x3 << 0)
/* EXYNOS_DP_TX_AMP_TUNING_CTL */ /* ANALOGIX_DP_TX_AMP_TUNING_CTL */
#define CH3_AMP_400_MV (0x0 << 24) #define CH3_AMP_400_MV (0x0 << 24)
#define CH2_AMP_400_MV (0x0 << 16) #define CH2_AMP_400_MV (0x0 << 16)
#define CH1_AMP_400_MV (0x0 << 8) #define CH1_AMP_400_MV (0x0 << 8)
#define CH0_AMP_400_MV (0x0 << 0) #define CH0_AMP_400_MV (0x0 << 0)
/* EXYNOS_DP_AUX_HW_RETRY_CTL */ /* ANALOGIX_DP_AUX_HW_RETRY_CTL */
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
...@@ -204,7 +216,7 @@ ...@@ -204,7 +216,7 @@
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
/* EXYNOS_DP_COMMON_INT_STA_1 */ /* ANALOGIX_DP_COMMON_INT_STA_1 */
#define VSYNC_DET (0x1 << 7) #define VSYNC_DET (0x1 << 7)
#define PLL_LOCK_CHG (0x1 << 6) #define PLL_LOCK_CHG (0x1 << 6)
#define SPDIF_ERR (0x1 << 5) #define SPDIF_ERR (0x1 << 5)
...@@ -214,19 +226,19 @@ ...@@ -214,19 +226,19 @@
#define VID_CLK_CHG (0x1 << 1) #define VID_CLK_CHG (0x1 << 1)
#define SW_INT (0x1 << 0) #define SW_INT (0x1 << 0)
/* EXYNOS_DP_COMMON_INT_STA_2 */ /* ANALOGIX_DP_COMMON_INT_STA_2 */
#define ENC_EN_CHG (0x1 << 6) #define ENC_EN_CHG (0x1 << 6)
#define HW_BKSV_RDY (0x1 << 3) #define HW_BKSV_RDY (0x1 << 3)
#define HW_SHA_DONE (0x1 << 2) #define HW_SHA_DONE (0x1 << 2)
#define HW_AUTH_STATE_CHG (0x1 << 1) #define HW_AUTH_STATE_CHG (0x1 << 1)
#define HW_AUTH_DONE (0x1 << 0) #define HW_AUTH_DONE (0x1 << 0)
/* EXYNOS_DP_COMMON_INT_STA_3 */ /* ANALOGIX_DP_COMMON_INT_STA_3 */
#define AFIFO_UNDER (0x1 << 7) #define AFIFO_UNDER (0x1 << 7)
#define AFIFO_OVER (0x1 << 6) #define AFIFO_OVER (0x1 << 6)
#define R0_CHK_FLAG (0x1 << 5) #define R0_CHK_FLAG (0x1 << 5)
/* EXYNOS_DP_COMMON_INT_STA_4 */ /* ANALOGIX_DP_COMMON_INT_STA_4 */
#define PSR_ACTIVE (0x1 << 7) #define PSR_ACTIVE (0x1 << 7)
#define PSR_INACTIVE (0x1 << 6) #define PSR_INACTIVE (0x1 << 6)
#define SPDIF_BI_PHASE_ERR (0x1 << 5) #define SPDIF_BI_PHASE_ERR (0x1 << 5)
...@@ -234,29 +246,29 @@ ...@@ -234,29 +246,29 @@
#define HPD_LOST (0x1 << 1) #define HPD_LOST (0x1 << 1)
#define PLUG (0x1 << 0) #define PLUG (0x1 << 0)
/* EXYNOS_DP_INT_STA */ /* ANALOGIX_DP_INT_STA */
#define INT_HPD (0x1 << 6) #define INT_HPD (0x1 << 6)
#define HW_TRAINING_FINISH (0x1 << 5) #define HW_TRAINING_FINISH (0x1 << 5)
#define RPLY_RECEIV (0x1 << 1) #define RPLY_RECEIV (0x1 << 1)
#define AUX_ERR (0x1 << 0) #define AUX_ERR (0x1 << 0)
/* EXYNOS_DP_INT_CTL */ /* ANALOGIX_DP_INT_CTL */
#define SOFT_INT_CTRL (0x1 << 2) #define SOFT_INT_CTRL (0x1 << 2)
#define INT_POL1 (0x1 << 1) #define INT_POL1 (0x1 << 1)
#define INT_POL0 (0x1 << 0) #define INT_POL0 (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_1 */ /* ANALOGIX_DP_SYS_CTL_1 */
#define DET_STA (0x1 << 2) #define DET_STA (0x1 << 2)
#define FORCE_DET (0x1 << 1) #define FORCE_DET (0x1 << 1)
#define DET_CTRL (0x1 << 0) #define DET_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_2 */ /* ANALOGIX_DP_SYS_CTL_2 */
#define CHA_CRI(x) (((x) & 0xf) << 4) #define CHA_CRI(x) (((x) & 0xf) << 4)
#define CHA_STA (0x1 << 2) #define CHA_STA (0x1 << 2)
#define FORCE_CHA (0x1 << 1) #define FORCE_CHA (0x1 << 1)
#define CHA_CTRL (0x1 << 0) #define CHA_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_3 */ /* ANALOGIX_DP_SYS_CTL_3 */
#define HPD_STATUS (0x1 << 6) #define HPD_STATUS (0x1 << 6)
#define F_HPD (0x1 << 5) #define F_HPD (0x1 << 5)
#define HPD_CTRL (0x1 << 4) #define HPD_CTRL (0x1 << 4)
...@@ -265,13 +277,13 @@ ...@@ -265,13 +277,13 @@
#define F_VALID (0x1 << 1) #define F_VALID (0x1 << 1)
#define VALID_CTRL (0x1 << 0) #define VALID_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_4 */ /* ANALOGIX_DP_SYS_CTL_4 */
#define FIX_M_AUD (0x1 << 4) #define FIX_M_AUD (0x1 << 4)
#define ENHANCED (0x1 << 3) #define ENHANCED (0x1 << 3)
#define FIX_M_VID (0x1 << 2) #define FIX_M_VID (0x1 << 2)
#define M_VID_UPDATE_CTRL (0x3 << 0) #define M_VID_UPDATE_CTRL (0x3 << 0)
/* EXYNOS_DP_TRAINING_PTN_SET */ /* ANALOGIX_DP_TRAINING_PTN_SET */
#define SCRAMBLER_TYPE (0x1 << 9) #define SCRAMBLER_TYPE (0x1 << 9)
#define HW_LINK_TRAINING_PATTERN (0x1 << 8) #define HW_LINK_TRAINING_PATTERN (0x1 << 8)
#define SCRAMBLING_DISABLE (0x1 << 5) #define SCRAMBLING_DISABLE (0x1 << 5)
...@@ -285,24 +297,24 @@ ...@@ -285,24 +297,24 @@
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
#define PRE_EMPHASIS_SET_MASK (0x3 << 3) #define PRE_EMPHASIS_SET_MASK (0x3 << 3)
#define PRE_EMPHASIS_SET_SHIFT (3) #define PRE_EMPHASIS_SET_SHIFT (3)
/* EXYNOS_DP_DEBUG_CTL */ /* ANALOGIX_DP_DEBUG_CTL */
#define PLL_LOCK (0x1 << 4) #define PLL_LOCK (0x1 << 4)
#define F_PLL_LOCK (0x1 << 3) #define F_PLL_LOCK (0x1 << 3)
#define PLL_LOCK_CTRL (0x1 << 2) #define PLL_LOCK_CTRL (0x1 << 2)
#define PN_INV (0x1 << 0) #define PN_INV (0x1 << 0)
/* EXYNOS_DP_PLL_CTL */ /* ANALOGIX_DP_PLL_CTL */
#define DP_PLL_PD (0x1 << 7) #define DP_PLL_PD (0x1 << 7)
#define DP_PLL_RESET (0x1 << 6) #define DP_PLL_RESET (0x1 << 6)
#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) #define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) #define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
/* EXYNOS_DP_PHY_PD */ /* ANALOGIX_DP_PHY_PD */
#define DP_PHY_PD (0x1 << 5) #define DP_PHY_PD (0x1 << 5)
#define AUX_PD (0x1 << 4) #define AUX_PD (0x1 << 4)
#define CH3_PD (0x1 << 3) #define CH3_PD (0x1 << 3)
...@@ -310,28 +322,28 @@ ...@@ -310,28 +322,28 @@
#define CH1_PD (0x1 << 1) #define CH1_PD (0x1 << 1)
#define CH0_PD (0x1 << 0) #define CH0_PD (0x1 << 0)
/* EXYNOS_DP_PHY_TEST */ /* ANALOGIX_DP_PHY_TEST */
#define MACRO_RST (0x1 << 5) #define MACRO_RST (0x1 << 5)
#define CH1_TEST (0x1 << 1) #define CH1_TEST (0x1 << 1)
#define CH0_TEST (0x1 << 0) #define CH0_TEST (0x1 << 0)
/* EXYNOS_DP_AUX_CH_STA */ /* ANALOGIX_DP_AUX_CH_STA */
#define AUX_BUSY (0x1 << 4) #define AUX_BUSY (0x1 << 4)
#define AUX_STATUS_MASK (0xf << 0) #define AUX_STATUS_MASK (0xf << 0)
/* EXYNOS_DP_AUX_CH_DEFER_CTL */ /* ANALOGIX_DP_AUX_CH_DEFER_CTL */
#define DEFER_CTRL_EN (0x1 << 7) #define DEFER_CTRL_EN (0x1 << 7)
#define DEFER_COUNT(x) (((x) & 0x7f) << 0) #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
/* EXYNOS_DP_AUX_RX_COMM */ /* ANALOGIX_DP_AUX_RX_COMM */
#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
/* EXYNOS_DP_BUFFER_DATA_CTL */ /* ANALOGIX_DP_BUFFER_DATA_CTL */
#define BUF_CLR (0x1 << 7) #define BUF_CLR (0x1 << 7)
#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
/* EXYNOS_DP_AUX_CH_CTL_1 */ /* ANALOGIX_DP_AUX_CH_CTL_1 */
#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
#define AUX_TX_COMM_MASK (0xf << 0) #define AUX_TX_COMM_MASK (0xf << 0)
#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
...@@ -340,20 +352,20 @@ ...@@ -340,20 +352,20 @@
#define AUX_TX_COMM_WRITE (0x0 << 0) #define AUX_TX_COMM_WRITE (0x0 << 0)
#define AUX_TX_COMM_READ (0x1 << 0) #define AUX_TX_COMM_READ (0x1 << 0)
/* EXYNOS_DP_AUX_ADDR_7_0 */ /* ANALOGIX_DP_AUX_ADDR_7_0 */
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
/* EXYNOS_DP_AUX_ADDR_15_8 */ /* ANALOGIX_DP_AUX_ADDR_15_8 */
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
/* EXYNOS_DP_AUX_ADDR_19_16 */ /* ANALOGIX_DP_AUX_ADDR_19_16 */
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
/* EXYNOS_DP_AUX_CH_CTL_2 */ /* ANALOGIX_DP_AUX_CH_CTL_2 */
#define ADDR_ONLY (0x1 << 1) #define ADDR_ONLY (0x1 << 1)
#define AUX_EN (0x1 << 0) #define AUX_EN (0x1 << 0)
/* EXYNOS_DP_SOC_GENERAL_CTL */ /* ANALOGIX_DP_SOC_GENERAL_CTL */
#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) #define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
#define AUDIO_MODE_MASTER_MODE (0x0 << 8) #define AUDIO_MODE_MASTER_MODE (0x0 << 8)
#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
...@@ -363,4 +375,4 @@ ...@@ -363,4 +375,4 @@
#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
#define VIDEO_MODE_MASTER_MODE (0x0 << 0) #define VIDEO_MODE_MASTER_MODE (0x0 << 0)
#endif /* _EXYNOS_DP_REG_H */ #endif /* _ANALOGIX_DP_REG_H */
...@@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI ...@@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI
This enables support for Exynos MIPI-DSI device. This enables support for Exynos MIPI-DSI device.
config DRM_EXYNOS_DP config DRM_EXYNOS_DP
bool "Display Port" bool "EXYNOS specific extensions for Analogix DP driver"
depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON
select DRM_ANALOGIX_DP
default DRM_EXYNOS default DRM_EXYNOS
select DRM_PANEL select DRM_PANEL
help help
......
...@@ -12,7 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o ...@@ -12,7 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o
exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp.o
exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER) += exynos_mixer.o exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER) += exynos_mixer.o
exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o
......
/*
* Samsung SoC DP (Display Port) interface driver.
*
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/of_graph.h>
#include <linux/component.h>
#include <video/of_display_timing.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_panel.h>
#include <drm/bridge/analogix_dp.h>
#include <drm/exynos_drm.h>
#include "exynos_drm_crtc.h"
#define to_dp(nm) container_of(nm, struct exynos_dp_device, nm)
struct exynos_dp_device {
struct drm_encoder encoder;
struct drm_connector connector;
struct drm_bridge *ptn_bridge;
struct drm_device *drm_dev;
struct device *dev;
struct videomode vm;
struct analogix_dp_plat_data plat_data;
};
int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
bool enable)
{
struct exynos_dp_device *dp = to_dp(plat_data);
struct drm_encoder *encoder = &dp->encoder;
struct exynos_drm_crtc *crtc;
if (!encoder)
return -1;
crtc = to_exynos_crtc(encoder->crtc);
if (crtc && crtc->ops && crtc->ops->clock_enable)
crtc->ops->clock_enable(crtc, enable);
return 0;
}
static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
{
return exynos_dp_crtc_clock_enable(plat_data, true);
}
static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
{
return exynos_dp_crtc_clock_enable(plat_data, false);
}
static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
{
struct exynos_dp_device *dp = to_dp(plat_data);
struct drm_connector *connector = &dp->connector;
struct drm_display_mode *mode;
int num_modes = 0;
if (dp->plat_data.panel)
return num_modes;
mode = drm_mode_create(connector->dev);
if (!mode) {
DRM_ERROR("failed to create a new display mode.\n");
return num_modes;
}
drm_display_mode_from_videomode(&dp->vm, mode);
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_probed_add(connector, mode);
return num_modes + 1;
}
static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
struct drm_bridge *bridge,
struct drm_connector *connector)
{
struct exynos_dp_device *dp = to_dp(plat_data);
struct drm_encoder *encoder = &dp->encoder;
int ret;
drm_connector_register(connector);
/* Pre-empt DP connector creation if there's a bridge */
if (dp->ptn_bridge) {
bridge->next = dp->ptn_bridge;
dp->ptn_bridge->encoder = encoder;
ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
if (ret) {
DRM_ERROR("Failed to attach bridge to drm\n");
bridge->next = NULL;
return ret;
}
}
return 0;
}
static void exynos_dp_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
}
static void exynos_dp_nop(struct drm_encoder *encoder)
{
/* do nothing */
}
static const struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
.mode_set = exynos_dp_mode_set,
.enable = exynos_dp_nop,
.disable = exynos_dp_nop,
};
static const struct drm_encoder_funcs exynos_dp_encoder_funcs = {
.destroy = drm_encoder_cleanup,
};
static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
{
int ret;
ret = of_get_videomode(dp->dev->of_node, &dp->vm, OF_USE_NATIVE_MODE);
if (ret) {
DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
return ret;
}
return 0;
}
static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
struct drm_encoder *encoder = &dp->encoder;
struct drm_device *drm_dev = data;
int pipe, ret;
/*
* Just like the probe function said, we don't need the
* device drvrate anymore, we should leave the charge to
* analogix dp driver, set the device drvdata to NULL.
*/
dev_set_drvdata(dev, NULL);
dp->dev = dev;
dp->drm_dev = drm_dev;
dp->plat_data.dev_type = EXYNOS_DP;
dp->plat_data.power_on = exynos_dp_poweron;
dp->plat_data.power_off = exynos_dp_poweroff;
dp->plat_data.attach = exynos_dp_bridge_attach;
dp->plat_data.get_modes = exynos_dp_get_modes;
if (!dp->plat_data.panel && !dp->ptn_bridge) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
return ret;
}
pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
EXYNOS_DISPLAY_TYPE_LCD);
if (pipe < 0)
return pipe;
encoder->possible_crtcs = 1 << pipe;
DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
dp->plat_data.encoder = encoder;
return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
}
static void exynos_dp_unbind(struct device *dev, struct device *master,
void *data)
{
return analogix_dp_unbind(dev, master, data);
}
static const struct component_ops exynos_dp_ops = {
.bind = exynos_dp_bind,
.unbind = exynos_dp_unbind,
};
static int exynos_dp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = NULL, *endpoint = NULL;
struct exynos_dp_device *dp;
dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
GFP_KERNEL);
if (!dp)
return -ENOMEM;
/*
* We just use the drvdata until driver run into component
* add function, and then we would set drvdata to null, so
* that analogix dp driver would take charge of the drvdata.
*/
platform_set_drvdata(pdev, dp);
/* This is for the backward compatibility. */
np = of_parse_phandle(dev->of_node, "panel", 0);
if (np) {
dp->plat_data.panel = of_drm_find_panel(np);
of_node_put(np);
if (!dp->plat_data.panel)
return -EPROBE_DEFER;
goto out;
}
endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
if (endpoint) {
np = of_graph_get_remote_port_parent(endpoint);
if (np) {
/* The remote port can be either a panel or a bridge */
dp->plat_data.panel = of_drm_find_panel(np);
if (!dp->plat_data.panel) {
dp->ptn_bridge = of_drm_find_bridge(np);
if (!dp->ptn_bridge) {
of_node_put(np);
return -EPROBE_DEFER;
}
}
of_node_put(np);
} else {
DRM_ERROR("no remote endpoint device node found.\n");
return -EINVAL;
}
} else {
DRM_ERROR("no port endpoint subnode found.\n");
return -EINVAL;
}
out:
return component_add(&pdev->dev, &exynos_dp_ops);
}
static int exynos_dp_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &exynos_dp_ops);
return 0;
}
#ifdef CONFIG_PM
static int exynos_dp_suspend(struct device *dev)
{
return analogix_dp_suspend(dev);
}
static int exynos_dp_resume(struct device *dev)
{
return analogix_dp_resume(dev);
}
#endif
static const struct dev_pm_ops exynos_dp_pm_ops = {
SET_RUNTIME_PM_OPS(exynos_dp_suspend, exynos_dp_resume, NULL)
};
static const struct of_device_id exynos_dp_match[] = {
{ .compatible = "samsung,exynos5-dp" },
{},
};
MODULE_DEVICE_TABLE(of, exynos_dp_match);
struct platform_driver dp_driver = {
.probe = exynos_dp_probe,
.remove = exynos_dp_remove,
.driver = {
.name = "exynos-dp",
.owner = THIS_MODULE,
.pm = &exynos_dp_pm_ops,
.of_match_table = exynos_dp_match,
},
};
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
MODULE_LICENSE("GPL v2");
...@@ -16,6 +16,15 @@ config DRM_ROCKCHIP ...@@ -16,6 +16,15 @@ config DRM_ROCKCHIP
2D or 3D acceleration; acceleration is performed by other 2D or 3D acceleration; acceleration is performed by other
IP found on the SoC. IP found on the SoC.
config ROCKCHIP_ANALOGIX_DP
tristate "Rockchip specific extensions for Analogix DP driver"
depends on DRM_ROCKCHIP
select DRM_ANALOGIX_DP
help
This selects support for Rockchip SoC specific extensions
for the Analogix Core DP driver. If you want to enable DP
on RK3288 based SoC, you should selet this option.
config ROCKCHIP_DW_HDMI config ROCKCHIP_DW_HDMI
tristate "Rockchip specific extensions for Synopsys DW HDMI" tristate "Rockchip specific extensions for Synopsys DW HDMI"
depends on DRM_ROCKCHIP depends on DRM_ROCKCHIP
......
...@@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ ...@@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
rockchip_drm_gem.o rockchip_drm_vop.o rockchip_drm_gem.o rockchip_drm_vop.o
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
......
/*
* Rockchip SoC DP (Display Port) interface driver.
*
* Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
* Author: Andy Yan <andy.yan@rock-chips.com>
* Yakir Yang <ykk@rock-chips.com>
* Jeff Chen <jeff.chen@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/of_graph.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/clk.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
#include <drm/bridge/analogix_dp.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_vop.h"
#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
/* dp grf register offset */
#define GRF_SOC_CON6 0x025c
#define GRF_EDP_LCD_SEL_MASK BIT(5)
#define GRF_EDP_SEL_VOP_LIT BIT(5)
#define GRF_EDP_SEL_VOP_BIG 0
struct rockchip_dp_device {
struct drm_device *drm_dev;
struct device *dev;
struct drm_encoder encoder;
struct drm_display_mode mode;
struct clk *pclk;
struct regmap *grf;
struct reset_control *rst;
struct analogix_dp_plat_data plat_data;
};
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
reset_control_assert(dp->rst);
usleep_range(10, 20);
reset_control_deassert(dp->rst);
return 0;
}
static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
{
struct rockchip_dp_device *dp = to_dp(plat_data);
int ret;
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
dev_err(dp->dev, "failed to enable pclk %d\n", ret);
return ret;
}
ret = rockchip_dp_pre_init(dp);
if (ret < 0) {
dev_err(dp->dev, "failed to dp pre init %d\n", ret);
return ret;
}
return 0;
}
static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
{
struct rockchip_dp_device *dp = to_dp(plat_data);
clk_disable_unprepare(dp->pclk);
return 0;
}
static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
/* do nothing */
return true;
}
static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted)
{
/* do nothing */
}
static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
{
struct rockchip_dp_device *dp = to_dp(encoder);
int ret;
u32 val;
/*
* FIXME(Yakir): driver should configure the CRTC output video
* mode with the display information which indicated the monitor
* support colorimetry.
*
* But don't know why the CRTC driver seems could only output the
* RGBaaa rightly. For example, if connect the "innolux,n116bge"
* eDP screen, EDID would indicated that screen only accepted the
* 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
* screen would show a blue picture (RGB888 show a green picture).
* But if I configure CTRC to RGBaaa, and eDP driver still keep
* RGB666 input video mode, then screen would works prefect.
*/
ret = rockchip_drm_crtc_mode_config(encoder->crtc,
DRM_MODE_CONNECTOR_eDP,
ROCKCHIP_OUT_MODE_AAAA);
if (ret < 0) {
dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
return;
}
ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
if (ret < 0)
return;
if (ret)
val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
else
val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
if (ret != 0) {
dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
return;
}
}
static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
{
/* do nothing */
}
static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
.mode_set = rockchip_dp_drm_encoder_mode_set,
.enable = rockchip_dp_drm_encoder_enable,
.disable = rockchip_dp_drm_encoder_nop,
};
static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
{
drm_encoder_cleanup(encoder);
}
static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
.destroy = rockchip_dp_drm_encoder_destroy,
};
static int rockchip_dp_init(struct rockchip_dp_device *dp)
{
struct device *dev = dp->dev;
struct device_node *np = dev->of_node;
int ret;
dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(dp->grf)) {
dev_err(dev, "failed to get rockchip,grf property\n");
return PTR_ERR(dp->grf);
}
dp->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(dp->pclk)) {
dev_err(dev, "failed to get pclk property\n");
return PTR_ERR(dp->pclk);
}
dp->rst = devm_reset_control_get(dev, "dp");
if (IS_ERR(dp->rst)) {
dev_err(dev, "failed to get dp reset control\n");
return PTR_ERR(dp->rst);
}
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
dev_err(dp->dev, "failed to enable pclk %d\n", ret);
return ret;
}
ret = rockchip_dp_pre_init(dp);
if (ret < 0) {
dev_err(dp->dev, "failed to pre init %d\n", ret);
return ret;
}
return 0;
}
static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
struct drm_encoder *encoder = &dp->encoder;
struct drm_device *drm_dev = dp->drm_dev;
struct device *dev = dp->dev;
int ret;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
dev->of_node);
DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
if (ret) {
DRM_ERROR("failed to initialize encoder with drm\n");
return ret;
}
drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
return 0;
}
static int rockchip_dp_bind(struct device *dev, struct device *master,
void *data)
{
struct rockchip_dp_device *dp = dev_get_drvdata(dev);
struct drm_device *drm_dev = data;
int ret;
/*
* Just like the probe function said, we don't need the
* device drvrate anymore, we should leave the charge to
* analogix dp driver, set the device drvdata to NULL.
*/
dev_set_drvdata(dev, NULL);
ret = rockchip_dp_init(dp);
if (ret < 0)
return ret;
dp->drm_dev = drm_dev;
ret = rockchip_dp_drm_create_encoder(dp);
if (ret) {
DRM_ERROR("failed to create drm encoder\n");
return ret;
}
dp->plat_data.encoder = &dp->encoder;
dp->plat_data.dev_type = RK3288_DP;
dp->plat_data.power_on = rockchip_dp_poweron;
dp->plat_data.power_off = rockchip_dp_powerdown;
return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
}
static void rockchip_dp_unbind(struct device *dev, struct device *master,
void *data)
{
return analogix_dp_unbind(dev, master, data);
}
static const struct component_ops rockchip_dp_component_ops = {
.bind = rockchip_dp_bind,
.unbind = rockchip_dp_unbind,
};
static int rockchip_dp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *panel_node, *port, *endpoint;
struct rockchip_dp_device *dp;
struct drm_panel *panel;
port = of_graph_get_port_by_id(dev->of_node, 1);
if (!port) {
dev_err(dev, "can't find output port\n");
return -EINVAL;
}
endpoint = of_get_child_by_name(port, "endpoint");
of_node_put(port);
if (!endpoint) {
dev_err(dev, "no output endpoint found\n");
return -EINVAL;
}
panel_node = of_graph_get_remote_port_parent(endpoint);
of_node_put(endpoint);
if (!panel_node) {
dev_err(dev, "no output node found\n");
return -EINVAL;
}
panel = of_drm_find_panel(panel_node);
if (!panel) {
DRM_ERROR("failed to find panel\n");
of_node_put(panel_node);
return -EPROBE_DEFER;
}
of_node_put(panel_node);
dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
if (!dp)
return -ENOMEM;
dp->dev = dev;
dp->plat_data.panel = panel;
/*
* We just use the drvdata until driver run into component
* add function, and then we would set drvdata to null, so
* that analogix dp driver could take charge of the drvdata.
*/
platform_set_drvdata(pdev, dp);
return component_add(dev, &rockchip_dp_component_ops);
}
static int rockchip_dp_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &rockchip_dp_component_ops);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int rockchip_dp_suspend(struct device *dev)
{
return analogix_dp_suspend(dev);
}
static int rockchip_dp_resume(struct device *dev)
{
return analogix_dp_resume(dev);
}
#endif
static const struct dev_pm_ops rockchip_dp_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
};
static const struct of_device_id rockchip_dp_dt_ids[] = {
{.compatible = "rockchip,rk3288-dp",},
{}
};
MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
static struct platform_driver rockchip_dp_driver = {
.probe = rockchip_dp_probe,
.remove = rockchip_dp_remove,
.driver = {
.name = "rockchip-dp",
.owner = THIS_MODULE,
.pm = &rockchip_dp_pm_ops,
.of_match_table = of_match_ptr(rockchip_dp_dt_ids),
},
};
module_platform_driver(rockchip_dp_driver);
MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
MODULE_LICENSE("GPL v2");
/*
* Analogix DP (Display Port) Core interface driver.
*
* Copyright (C) 2015 Rockchip Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _ANALOGIX_DP_H_
#define _ANALOGIX_DP_H_
#include <drm/drm_crtc.h>
enum analogix_dp_devtype {
EXYNOS_DP,
RK3288_DP,
};
struct analogix_dp_plat_data {
enum analogix_dp_devtype dev_type;
struct drm_panel *panel;
struct drm_encoder *encoder;
struct drm_connector *connector;
int (*power_on)(struct analogix_dp_plat_data *);
int (*power_off)(struct analogix_dp_plat_data *);
int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
struct drm_connector *);
int (*get_modes)(struct analogix_dp_plat_data *);
};
int analogix_dp_resume(struct device *dev);
int analogix_dp_suspend(struct device *dev);
int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
struct analogix_dp_plat_data *plat_data);
void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
#endif /* _ANALOGIX_DP_H_ */
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