Commit d0830f6c authored by Kevin McKinney's avatar Kevin McKinney Committed by Greg Kroah-Hartman

Staging: bcm: Remove condition check on macro REL_4_1 because it is not used.

This patch removes the conditional check on
macro REL_4_1, and the corresponding controlled
text because it is not used.
Signed-off-by: default avatarKevin McKinney <klmckinney1@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 37531643
...@@ -251,87 +251,6 @@ typedef struct _PER_TARANG_DATA { ...@@ -251,87 +251,6 @@ typedef struct _PER_TARANG_DATA {
ULONG RxCntrlMsgBitMask; ULONG RxCntrlMsgBitMask;
} PER_TARANG_DATA, *PPER_TARANG_DATA; } PER_TARANG_DATA, *PPER_TARANG_DATA;
#ifdef REL_4_1
typedef struct _TARGET_PARAMS {
B_UINT32 m_u32CfgVersion;
/* Scanning Related Params */
B_UINT32 m_u32CenterFrequency;
B_UINT32 m_u32BandAScan;
B_UINT32 m_u32BandBScan;
B_UINT32 m_u32BandCScan;
/* QoS Params */
B_UINT32 m_u32minGrantsize; /* size of minimum grant is 0 or 6 */
B_UINT32 m_u32PHSEnable;
/* HO Params */
B_UINT32 m_u32HoEnable;
B_UINT32 m_u32HoReserved1;
B_UINT32 m_u32HoReserved2;
/* Power Control Params */
B_UINT32 m_u32MimoEnable;
B_UINT32 m_u32SecurityEnable;
/*
* bit 1: 1 Idlemode enable;
* bit 2: 1 Sleepmode Enable
*/
B_UINT32 m_u32PowerSavingModesEnable;
/* PowerSaving Mode Options:
* bit 0 = 1: CPE mode - to keep pcmcia if alive;
* bit 1 = 1: CINR reporing in Idlemode Msg
* bit 2 = 1: Default PSC Enable in sleepmode
*/
B_UINT32 m_u32PowerSavingModeOptions;
B_UINT32 m_u32ArqEnable;
/* From Version #3, the HARQ section renamed as general */
B_UINT32 m_u32HarqEnable;
/* EEPROM Param Location */
B_UINT32 m_u32EEPROMFlag;
/* BINARY TYPE - 4th MSByte:
* Interface Type - 3rd MSByte:
* Vendor Type - 2nd MSByte
*/
/* Unused - LSByte */
B_UINT32 m_u32Customize;
B_UINT32 m_u32ConfigBW; /* In Hz */
B_UINT32 m_u32ShutDownTimer;
B_UINT32 m_u32RadioParameter;
B_UINT32 m_u32PhyParameter1;
B_UINT32 m_u32PhyParameter2;
B_UINT32 m_u32PhyParameter3;
/* in eval mode only;
* lower 16bits = basic cid for testing;
* then bit 16 is test cqich,
* bit 17 test init rang;
* bit 18 test periodic rang
* bit 19 is test harq ack/nack
*/
B_UINT32 m_u32TestOptions;
B_UINT32 m_u32MaxMACDataperDLFrame;
B_UINT32 m_u32MaxMACDataperULFrame;
B_UINT32 m_u32Corr2MacFlags;
/* adding driver params. */
B_UINT32 HostDrvrConfig1;
B_UINT32 HostDrvrConfig2;
B_UINT32 HostDrvrConfig3;
B_UINT32 HostDrvrConfig4;
B_UINT32 HostDrvrConfig5;
B_UINT32 HostDrvrConfig6;
B_UINT32 m_u32SegmentedPUSCenable;
/* BAMC enable - but 4.x does not support this feature
* This is added just to sync 4.x and 5.x CFGs
*/
B_UINT32 m_u32BandAMCEnable;
} STARGETPARAMS, *PSTARGETPARAMS;
#endif
struct bcm_targetdsx_buffer { struct bcm_targetdsx_buffer {
ULONG ulTargetDsxBuffer; ULONG ulTargetDsxBuffer;
B_UINT16 tid; B_UINT16 tid;
......
...@@ -252,11 +252,7 @@ typedef enum _E_PHS_DSC_ACTION { ...@@ -252,11 +252,7 @@ typedef enum _E_PHS_DSC_ACTION {
#define IDLE_MODE_WAKEUP_NOTIFIER_ADDRESS 0x1FC02FA8 #define IDLE_MODE_WAKEUP_NOTIFIER_ADDRESS 0x1FC02FA8
#define IDLE_MODE_MAX_RETRY_COUNT 1000 #define IDLE_MODE_MAX_RETRY_COUNT 1000
#ifdef REL_4_1
#define CONFIG_BEGIN_ADDR 0xBF60B004
#else
#define CONFIG_BEGIN_ADDR 0xBF60B000 #define CONFIG_BEGIN_ADDR 0xBF60B000
#endif
#define FIRMWARE_BEGIN_ADDR 0xBFC00000 #define FIRMWARE_BEGIN_ADDR 0xBFC00000
......
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