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Commit d27895a1 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'imx-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt 

i.MX device tree update for 5.9:

- New board support: Protonic PRTI6Q/WD2/VT7/RVT and MYiR MYS-6ULX SBC.
- Update IIM, OCOTP and SD/MMC device node name to match .yaml bindings.
- Make tempmon node as child of anatop node according to hardware
  architecture.
- The vf610-zii device update: configure fiber port to 1000BaseX, add
  switch watchdog, MDIO speed and preamble.
- A series from Fabio Estevam to update imx6qdl-sabresd and
  imx6q-tbs2910 for using MDIO node and reset-assert-us.
- Align L2 cache-controller device node name with .yaml schema.
- Enable SATA support for imx6qp-sabreauto and imx6qp-sabresd board.
- A series of patches from Shengjiu Wang to enable various audio
  support on i.MX6 devices.
- Add Gateworks System Controller support for imx6qdl-gw devices.
- Change default #pwm-cells setting to <3> in the SoC dtsi files.
- Other small random changes.

* tag 'imx-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (43 commits)
  ARM: dts: vf610-zii-ssmb-spu3: Add node for switch watchdog
  ARM: dts: vf610-zii-ssmb-dtu: Add no-sdio/no-sd properties
  ARM: dts: imx6q-tbs2910: Pass reset-assert-us
  ARM: dts: imx6q-tbs2910: Add an mdio node
  ARM: dts: imx6qdl-sabresd: Pass reset-assert-us
  ARM: dts: imx6qdl-sabresd: Add an mdio node
  ARM: dts: imx6qdl-gw: add Gateworks System Controller support
  ARM: dts: imx6ull: add MYiR MYS-6ULX SBC
  ARM: dts: vf610-zii-spb4: Add node for switch watchdog
  ARM: dts: colibri-imx6: remove pinctrl-names orphan
  ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files
  ARM: dts: vf610-zii-scu4-aib: Configure fibre ports to 1000BaseX
  ARM: dts: vf610-zii-dev-rev-c: Configure fiber port to 1000BaseX
  ARM: dts: ZII: update MDIO speed and preamble
  ARM: dts: vfxxx: Add node for CAAM
  ARM: dts: imx6qp-sabresd: enable sata
  ARM: dts: imx6qp-sabreauto: enable sata
  ARM: dts: add Protonic RVT board
  ARM: dts: add Protonic VT7 board
  ARM: dts: add Protonic WD2 board
  ...

Link: https://lore.kernel.org/r/20200720085536.24138-3-shawnguo@kernel.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 8fc5082a 983467be
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Showing with 4466 additions and 267 deletions
arch/arm/boot/dts/Makefile
View file @ d27895a1
......@@ -455,6 +455,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-pico-hobbit.dtb \
imx6dl-pico-nymph.dtb \
imx6dl-pico-pi.dtb \
imx6dl-prtrvt.dtb \
imx6dl-prtvt7.dtb \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
......@@ -543,6 +545,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-pico-nymph.dtb \
imx6q-pico-pi.dtb \
imx6q-pistachio.dtb \
imx6q-prti6q.dtb \
imx6q-prtwd2.dtb \
imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
......@@ -592,6 +596,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb \
imx6sx-sdb-mqs.dtb \
imx6sx-softing-vining-2000.dtb \
imx6sx-udoo-neo-basic.dtb \
imx6sx-udoo-neo-extended.dtb \
......@@ -617,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
......
arch/arm/boot/dts/imx1.dtsi
View file @ d27895a1
......@@ -125,7 +125,7 @@ uart2: serial@207000 {
};
pwm: pwm@208000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
......
arch/arm/boot/dts/imx23.dtsi
View file @ d27895a1
......@@ -442,7 +442,7 @@ pxp@8002a000 {
status = "disabled";
};
ocotp@8002c000 {
efuse@8002c000 {
compatible = "fsl,imx23-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm/boot/dts/imx25.dtsi
View file @ d27895a1
......@@ -411,7 +411,7 @@ gpio4: gpio@53f9c000 {
pwm2: pwm@53fa0000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
#pwm-cells = <3>;
reg = <0x53fa0000 0x4000>;
clocks = <&clks 106>, <&clks 52>;
clock-names = "ipg", "per";
......@@ -430,7 +430,7 @@ gpio3: gpio@53fa4000 {
pwm3: pwm@53fa8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
#pwm-cells = <3>;
reg = <0x53fa8000 0x4000>;
clocks = <&clks 107>, <&clks 52>;
clock-names = "ipg", "per";
......@@ -453,7 +453,7 @@ rngb: rngb@53fb0000 {
interrupts = <22>;
};
esdhc1: esdhc@53fb4000 {
esdhc1: mmc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <9>;
......@@ -462,7 +462,7 @@ esdhc1: esdhc@53fb4000 {
status = "disabled";
};
esdhc2: esdhc@53fb8000 {
esdhc2: mmc@53fb8000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb8000 0x4000>;
interrupts = <8>;
......@@ -488,7 +488,7 @@ slcdc@53fc0000 {
pwm4: pwm@53fc8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
#pwm-cells = <3>;
reg = <0x53fc8000 0x4000>;
clocks = <&clks 108>, <&clks 52>;
clock-names = "ipg", "per";
......@@ -535,14 +535,14 @@ wdog@53fdc000 {
pwm1: pwm@53fe0000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
#pwm-cells = <3>;
reg = <0x53fe0000 0x4000>;
clocks = <&clks 105>, <&clks 52>;
clock-names = "ipg", "per";
interrupts = <26>;
};
iim: iim@53ff0000 {
iim: efuse@53ff0000 {
compatible = "fsl,imx25-iim", "fsl,imx27-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
......
arch/arm/boot/dts/imx27.dtsi
View file @ d27895a1
......@@ -134,7 +134,7 @@ gpt3: timer@10005000 {
};
pwm: pwm@10006000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx27-pwm";
reg = <0x10006000 0x1000>;
interrupts = <23>;
......@@ -265,7 +265,7 @@ i2c1: i2c@10012000 {
status = "disabled";
};
sdhci1: sdhci@10013000 {
sdhci1: mmc@10013000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10013000 0x1000>;
interrupts = <11>;
......@@ -277,7 +277,7 @@ sdhci1: sdhci@10013000 {
status = "disabled";
};
sdhci2: sdhci@10014000 {
sdhci2: mmc@10014000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <10>;
......@@ -431,7 +431,7 @@ i2c2: i2c@1001d000 {
status = "disabled";
};
sdhci3: sdhci@1001e000 {
sdhci3: mmc@1001e000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x1001e000 0x1000>;
interrupts = <9>;
......@@ -540,7 +540,7 @@ clks: ccm@10027000{
#clock-cells = <1>;
};
iim: iim@10028000 {
iim: efuse@10028000 {
compatible = "fsl,imx27-iim";
reg = <0x10028000 0x1000>;
interrupts = <62>;
......
arch/arm/boot/dts/imx28.dtsi
View file @ d27895a1
......@@ -1011,7 +1011,7 @@ pxp: pxp@8002a000 {
status = "disabled";
};
ocotp: ocotp@8002c000 {
ocotp: efuse@8002c000 {
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm/boot/dts/imx31.dtsi
View file @ d27895a1
......@@ -173,7 +173,7 @@ spba@50000000 {
reg = <0x50000000 0x100000>;
ranges;
sdhci1: sdhci@50004000 {
sdhci1: mmc@50004000 {
compatible = "fsl,imx31-mmc";
reg = <0x50004000 0x4000>;
interrupts = <9>;
......@@ -184,7 +184,7 @@ sdhci1: sdhci@50004000 {
status = "disabled";
};
sdhci2: sdhci@50008000 {
sdhci2: mmc@50008000 {
compatible = "fsl,imx31-mmc";
reg = <0x50008000 0x4000>;
interrupts = <8>;
......@@ -217,7 +217,7 @@ spi2: spi@50010000 {
status = "disabled";
};
iim: iim@5001c000 {
iim: efuse@5001c000 {
compatible = "fsl,imx31-iim", "fsl,imx27-iim";
reg = <0x5001c000 0x1000>;
interrupts = <19>;
......@@ -327,7 +327,7 @@ pwm: pwm@53fe0000 {
interrupts = <26>;
clocks = <&clks 10>, <&clks 42>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
};
......
arch/arm/boot/dts/imx35.dtsi
View file @ d27895a1
......@@ -59,7 +59,7 @@ soc {
interrupt-parent = <&avic>;
ranges;
L2: l2-cache@30000000 {
L2: cache-controller@30000000 {
compatible = "arm,l210-cache";
reg = <0x30000000 0x1000>;
cache-unified;
......@@ -231,7 +231,7 @@ gpio3: gpio@53fa4000 {
#interrupt-cells = <2>;
};
esdhc1: esdhc@53fb4000 {
esdhc1: mmc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
......@@ -240,7 +240,7 @@ esdhc1: esdhc@53fb4000 {
status = "disabled";
};
esdhc2: esdhc@53fb8000 {
esdhc2: mmc@53fb8000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb8000 0x4000>;
interrupts = <8>;
......@@ -249,7 +249,7 @@ esdhc2: esdhc@53fb8000 {
status = "disabled";
};
esdhc3: esdhc@53fbc000 {
esdhc3: mmc@53fbc000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fbc000 0x4000>;
interrupts = <9>;
......@@ -320,7 +320,7 @@ can2: can@53fe8000 {
status = "disabled";
};
iim@53ff0000 {
efuse@53ff0000 {
compatible = "fsl,imx35-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
......
arch/arm/boot/dts/imx50.dtsi
View file @ d27895a1
......@@ -115,7 +115,7 @@ spba@50000000 {
reg = <0x50000000 0x40000>;
ranges;
esdhc1: esdhc@50004000 {
esdhc1: mmc@50004000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
......@@ -127,7 +127,7 @@ esdhc1: esdhc@50004000 {
status = "disabled";
};
esdhc2: esdhc@50008000 {
esdhc2: mmc@50008000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
......@@ -176,7 +176,7 @@ ssi2: ssi@50014000 {
status = "disabled";
};
esdhc3: esdhc@50020000 {
esdhc3: mmc@50020000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
......@@ -188,7 +188,7 @@ esdhc3: esdhc@50020000 {
status = "disabled";
};
esdhc4: esdhc@50024000 {
esdhc4: mmc@50024000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
......@@ -289,7 +289,7 @@ iomuxc: iomuxc@53fa8000 {
};
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
......@@ -299,7 +299,7 @@ pwm1: pwm@53fb4000 {
};
pwm2: pwm@53fb8000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
......
arch/arm/boot/dts/imx51-ts4800.dts
View file @ d27895a1
......@@ -113,6 +113,7 @@ &ipu_di0_disp1 {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_backlight>;
status = "okay";
......
arch/arm/boot/dts/imx51.dtsi
View file @ d27895a1
......@@ -185,7 +185,7 @@ spba@70000000 {
reg = <0x70000000 0x40000>;
ranges;
esdhc1: esdhc@70004000 {
esdhc1: mmc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
......@@ -196,7 +196,7 @@ esdhc1: esdhc@70004000 {
status = "disabled";
};
esdhc2: esdhc@70008000 {
esdhc2: mmc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
......@@ -245,7 +245,7 @@ ssi2: ssi@70014000 {
status = "disabled";
};
esdhc3: esdhc@70020000 {
esdhc3: mmc@70020000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
......@@ -257,7 +257,7 @@ esdhc3: esdhc@70020000 {
status = "disabled";
};
esdhc4: esdhc@70024000 {
esdhc4: mmc@70024000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
......@@ -400,7 +400,7 @@ iomuxc: iomuxc@73fa8000 {
};
pwm1: pwm@73fb4000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
......@@ -410,7 +410,7 @@ pwm1: pwm@73fb4000 {
};
pwm2: pwm@73fb8000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
......@@ -466,7 +466,7 @@ aipstz2: bridge@83f00000 {
reg = <0x83f00000 0x60>;
};
iim: iim@83f98000 {
iim: efuse@83f98000 {
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
......
arch/arm/boot/dts/imx53-kp.dtsi
View file @ d27895a1
......@@ -162,6 +162,14 @@ MX53_PAD_EIM_D20__GPIO3_20 0x1e4
>;
};
&pwm1 {
#pwm-cells = <2>;
};
&pwm2 {
#pwm-cells = <2>;
};
&uart1 {
status = "okay";
};
......
arch/arm/boot/dts/imx53-m53evk.dts
View file @ d27895a1
......@@ -321,6 +321,7 @@ &ipu_di1_disp1 {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx53-ppd.dts
View file @ d27895a1
......@@ -176,7 +176,7 @@ pwm_bl: backlight {
power-supply = <&reg_3v3_lcd>;
};
leds {
leds-brightness {
compatible = "pwm-leds";
alarm-brightness {
......@@ -185,6 +185,32 @@ alarm-brightness {
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_alarmled_pins>;
alarm1 {
label = "alarm:red";
gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
};
alarm2 {
label = "alarm:yellow";
gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
};
alarm3 {
label = "alarm:blue";
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
};
alarm4 {
label = "alarm:silenced";
gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
......@@ -598,12 +624,14 @@ &pmu {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
......@@ -909,18 +937,10 @@ MX53_PAD_NANDF_CS2__GPIO6_15 0x0
MX53_PAD_NANDF_CS3__GPIO6_16 0x0
/* POWER_AND_BOOT_STATUS_INDICATOR */
MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4
/* ACTIVATE_ALARM_LIGHT_RED */
MX53_PAD_PATA_DIOR__GPIO7_3 0x0
/* ACTIVATE_ALARM_LIGHT_YELLOW */
MX53_PAD_PATA_DA_1__GPIO7_7 0x0
/* ACTIVATE_ALARM_LIGHT_CYAN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x0
/* RUNNING_ON_BATTERY_INDICATOR_GREEN */
MX53_PAD_GPIO_16__GPIO7_11 0x0
/* BATTERY_STATUS_INDICATOR_AMBER */
MX53_PAD_GPIO_17__GPIO7_12 0x0
/* AUDIO_ALARMS_SILENCED_INDICATOR */
MX53_PAD_GPIO_18__GPIO7_13 0x0
>;
};
......@@ -1080,4 +1100,17 @@ pinctrl_usb_otg: usbotggrp {
MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180
>;
};
pinctrl_alarmled_pins: qmx6alarmledgrp {
fsl,pins = <
/* ACTIVATE_ALARM_LIGHT_RED */
MX53_PAD_PATA_DIOR__GPIO7_3 0x0
/* ACTIVATE_ALARM_LIGHT_YELLOW */
MX53_PAD_PATA_DA_1__GPIO7_7 0x0
/* ACTIVATE_ALARM_LIGHT_CYAN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x0
/* AUDIO_ALARMS_SILENCED_INDICATOR */
MX53_PAD_GPIO_18__GPIO7_13 0x0
>;
};
};
arch/arm/boot/dts/imx53-tqma53.dtsi
View file @ d27895a1
......@@ -209,6 +209,14 @@ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
};
};
&pwm1 {
#pwm-cells = <2>;
};
&pwm2 {
#pwm-cells = <2>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
......
arch/arm/boot/dts/imx53-tx53.dtsi
View file @ d27895a1
......@@ -542,7 +542,6 @@ &nfc {
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
#pwm-cells = <3>;
};
&sdma {
......
arch/arm/boot/dts/imx53.dtsi
View file @ d27895a1
......@@ -236,7 +236,7 @@ spba@50000000 {
reg = <0x50000000 0x40000>;
ranges;
esdhc1: esdhc@50004000 {
esdhc1: mmc@50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
......@@ -248,7 +248,7 @@ esdhc1: esdhc@50004000 {
status = "disabled";
};
esdhc2: esdhc@50008000 {
esdhc2: mmc@50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
......@@ -301,7 +301,7 @@ ssi2: ssi@50014000 {
status = "disabled";
};
esdhc3: esdhc@50020000 {
esdhc3: mmc@50020000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
......@@ -313,7 +313,7 @@ esdhc3: esdhc@50020000 {
status = "disabled";
};
esdhc4: esdhc@50024000 {
esdhc4: mmc@50024000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
......@@ -525,7 +525,7 @@ port@2 {
};
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
......@@ -535,7 +535,7 @@ pwm1: pwm@53fb4000 {
};
pwm2: pwm@53fb8000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
......@@ -667,7 +667,7 @@ aipstz2: bridge@63f00000 {
reg = <0x63f00000 0x60>;
};
iim: iim@63f98000 {
iim: efuse@63f98000 {
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
reg = <0x63f98000 0x4000>;
interrupts = <69>;
......
arch/arm/boot/dts/imx6dl-aristainetos_4.dts
View file @ d27895a1
......@@ -79,5 +79,6 @@ &ipu1_di0_disp0 {
};
&pwm1 {
#pwm-cells = <2>;
status = "okay";
};
arch/arm/boot/dts/imx6dl-aristainetos_7.dts
View file @ d27895a1
......@@ -69,5 +69,6 @@ &ipu1_di0_disp0 {
};
&pwm3 {
#pwm-cells = <2>;
status = "okay";
};
arch/arm/boot/dts/imx6dl-mamoj.dts
View file @ d27895a1
......@@ -303,6 +303,7 @@ &ipu1_di0_disp0 {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......
arch/arm/boot/dts/imx6dl-prtrvt.dts 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2014 Protonic Holland
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-prti6q.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Protonic RVT board";
compatible = "prt,prtrvt", "fsl,imx6dl";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x10000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-debug0 {
function = LED_FUNCTION_STATUS;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
nfc@0 {
compatible = "ti,trf7970a";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
spi-max-frequency = <2000000>;
interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>;
ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>,
<&gpio5 11 GPIO_ACTIVE_LOW>;
vin-supply = <&reg_3v3>;
vin-voltage-override = <3100000>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
en2-rf-quirk;
t5t-rmb-extra-byte-quirk;
status = "okay";
};
};
&i2c3 {
adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
/* nc */
channel@4 {
reg = <4>;
ti,gain = <3>;
ti,datarate = <3>;
};
/* nc */
channel@5 {
reg = <5>;
ti,gain = <3>;
ti,datarate = <3>;
};
/* can1_l */
channel@6 {
reg = <6>;
ti,gain = <3>;
ti,datarate = <3>;
};
/* can1_h */
channel@7 {
reg = <7>;
ti,gain = <3>;
ti,datarate = <3>;
};
};
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&pcie {
status = "okay";
};
&usbh1 {
status = "disabled";
};
&vpu {
status = "disabled";
};
&iomuxc {
pinctrl_can1phy: can1phy {
fsl,pins = <
/* CAN1_SR */
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
/* CAN1_TERM */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
/* CS */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
/* NFC_ASK_OOK */
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1
/* NFC_PWR_EN */
MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1
/* NFC_EN2 */
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1
/* NFC_EN */
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
/* NFC_MOD */
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
/* NFC_IRQ */
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
>;
};
};
arch/arm/boot/dts/imx6dl-prtvt7.dts 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2016 Protonic Holland
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-prti6q.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
model = "Protonic VT7";
compatible = "prt,prtvt7", "fsl,imx6dl";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm1 0 500000>;
brightness-levels = <0 20 81 248 1000>;
default-brightness-level = <20>;
num-interpolated-steps = <21>;
power-supply = <&reg_bl_12v0>;
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
};
keys {
compatible = "gpio-keys";
autorepeat;
esc {
label = "GPIO Key ESC";
linux,code = <KEY_ESC>;
gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>;
};
up {
label = "GPIO Key UP";
linux,code = <KEY_UP>;
gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>;
};
down {
label = "GPIO Key DOWN";
linux,code = <KEY_DOWN>;
gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>;
};
enter {
label = "GPIO Key Enter";
linux,code = <KEY_ENTER>;
gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>;
};
cycle {
label = "GPIO Key CYCLE";
linux,code = <KEY_CYCLEWINDOWS>;
gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>;
};
f1 {
label = "GPIO Key F1";
linux,code = <KEY_F1>;
gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>;
};
f2 {
label = "GPIO Key F2";
linux,code = <KEY_F2>;
gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>;
};
f3 {
label = "GPIO Key F3";
linux,code = <KEY_F3>;
gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>;
};
f4 {
label = "GPIO Key F4";
linux,code = <KEY_F4>;
gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>;
};
f5 {
label = "GPIO Key F5";
linux,code = <KEY_F5>;
gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>;
};
f6 {
label = "GPIO Key F6";
linux,code = <KEY_F6>;
gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>;
};
f7 {
label = "GPIO Key F7";
linux,code = <KEY_F7>;
gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>;
};
f8 {
label = "GPIO Key F8";
linux,code = <KEY_F8>;
gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>;
};
f9 {
label = "GPIO Key F9";
linux,code = <KEY_F9>;
gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>;
};
f10 {
label = "GPIO Key F10";
linux,code = <KEY_F10>;
gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-debug0 {
function = LED_FUNCTION_STATUS;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_bl_12v0: regulator-bl-12v0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_bl_12v0>;
regulator-name = "bl-12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "prti6q-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Line", "Line In Jack",
"Headphone", "Headphone Jack",
"Speaker", "External Speaker";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"External Speaker", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&ssi1>;
system-clock-frequency = <0>;
};
simple-audio-card,codec {
sound-dai = <&sgtl5000>;
bitclock-master;
frame-master;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
mux-ssi1 {
fsl,audmux-port = <0>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN 0
IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
IMX_AUDMUX_V2_PTCR_TFSDIR 0
IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
>;
};
mux-pins3 {
fsl,audmux-port = <2>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
0 IMX_AUDMUX_V2_PDCR_TXRXEN
>;
};
};
&can1 {
pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&i2c1 {
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
reg = <0xa>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec>;
#sound-dai-cells = <0>;
clocks = <&clks 201>;
VDDA-supply = <&reg_3v3>;
VDDIO-supply = <&reg_3v3>;
VDDD-supply = <&reg_1v8>;
};
};
&i2c3 {
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
gpio_pca: gpio@74 {
compatible = "nxp,pca9539";
reg = <0x74>;
interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
};
};
&ipu1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
status = "okay";
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&ssi1 {
#sound-dai-cells = <0>;
fsl,mode = "ac97-slave";
status = "okay";
};
&usbh1 {
status = "disabled";
};
&vpu {
status = "disabled";
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
>;
};
pinctrl_can1phy: can1phy {
fsl,pins = <
/* CAN1_SR */
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
/* CAN1_TERM */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_codec: codecgrp {
fsl,pins = <
/* AUDIO_nRESET */
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
/* ITU656_nRESET */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
/* ITU656_nPDN */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
>;
};
pinctrl_ipu1_disp: ipudisp1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
>;
};
pinctrl_reg_bl_12v0: 12blgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
};
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
View file @ d27895a1
......@@ -540,7 +540,6 @@ &pcie {
};
&pwm1 {
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "disabled";
......
arch/arm/boot/dts/imx6q-ba16.dtsi
View file @ d27895a1
......@@ -334,6 +334,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
View file @ d27895a1
......@@ -253,7 +253,6 @@ &pcie {
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
#pwm-cells = <3>;
status = "okay";
};
......
arch/arm/boot/dts/imx6q-display5.dtsi
View file @ d27895a1
......@@ -399,7 +399,6 @@ lvds0_out: endpoint {
};
&pwm2 {
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
......
arch/arm/boot/dts/imx6q-kp.dtsi
View file @ d27895a1
......@@ -378,12 +378,14 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
......
arch/arm/boot/dts/imx6q-mccmon6.dts
View file @ d27895a1
......@@ -237,7 +237,6 @@ lvds0_out: endpoint {
};
&pwm2 {
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
......
arch/arm/boot/dts/imx6q-novena.dts
View file @ d27895a1
......@@ -455,6 +455,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
status = "okay";
};
......
arch/arm/boot/dts/imx6q-pistachio.dts
View file @ d27895a1
......@@ -570,6 +570,7 @@ lvds0_out: endpoint {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6q-prti6q.dts 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2014 Protonic Holland
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-prti6q.dtsi"
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
model = "Protonic PRTI6Q board";
compatible = "prt,prti6q", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0xf0000000>;
};
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 16 64 255>;
num-interpolated-steps = <16>;
default-brightness-level = <1>;
power-supply = <&reg_3v3>;
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
};
can_osc: can-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-debug0 {
function = LED_FUNCTION_STATUS;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-debug1 {
function = LED_FUNCTION_SD;
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
};
};
panel {
compatible = "kyo,tcg121xglp";
backlight = <&backlight_lcd>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_npd>;
enable-active-high;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "regulator-WL12xx";
startup-delay-us = <70000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "prti6q-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Line", "Line In Jack",
"Headphone", "Headphone Jack",
"Speaker", "External Speaker";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"External Speaker", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&ssi1>;
system-clock-frequency = <0>;
};
simple-audio-card,codec {
sound-dai = <&sgtl5000>;
bitclock-master;
frame-master;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
spdif-out;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
mux-ssi1 {
fsl,audmux-port = <0>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN 0
IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
IMX_AUDMUX_V2_PTCR_TFSDIR 0
IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
>;
};
mux-pins3 {
fsl,audmux-port = <2>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
0 IMX_AUDMUX_V2_PDCR_TXRXEN
>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
status = "okay";
can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can3>;
clocks = <&can_osc>;
interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <5000000>;
};
adc@1 {
compatible = "ti,adc128s052";
reg = <1>;
spi-max-frequency = <2000000>;
vref-supply = <&reg_3v3>;
};
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-handle = <&rgmii_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Microchip KSZ9031RNX PHY */
rgmii_phy: ethernet-phy@4 {
reg = <4>;
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
reg = <0xa>;
#sound-dai-cells = <0>;
clocks = <&clks 201>;
VDDA-supply = <&reg_3v3>;
VDDIO-supply = <&reg_3v3>;
VDDD-supply = <&reg_1v8>;
};
};
/* DDC */
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
/* can2_l */
channel@4 {
reg = <4>;
ti,gain = <3>;
ti,datarate = <3>;
};
/* can2_h */
channel@5 {
reg = <5>;
ti,gain = <3>;
ti,datarate = <3>;
};
/* can1_l */
channel@6 {
reg = <6>;
ti,gain = <3>;
ti,datarate = <3>;
};
/* can1_h */
channel@7 {
reg = <7>;
ti,gain = <3>;
ti,datarate = <3>;
};
};
};
&pcie {
status = "okay";
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&ldb {
status = "okay";
lvds-channel@0 {
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&sata {
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
status = "okay";
};
&ssi1 {
#sound-dai-cells = <0>;
fsl,mode = "ac97-slave";
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>;
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
vmmc-supply = <&reg_wifi>;
cap-power-off-card;
keep-power-in-suspend;
status = "okay";
wifi {
compatible = "ti,wl1271";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
ref-clock-frequency = "38400000";
tcxo-clock-frequency = "19200000";
};
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008
>;
};
pinctrl_can3: can3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
/* CS */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
>;
};
pinctrl_ecspi2_cs: ecspi2csgrp {
fsl,pins = <
/* ADC128S022 CS */
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
/* Phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
/* NOTE: DDC is done via I2C2, so DON'T
* configure DDC pins for HDMI!
*/
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
/* DDC */
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg_id: usbotgidgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
/* WL12xx IRQ */
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
>;
};
pinctrl_wifi_npd: wifinpd {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
>;
};
};
arch/arm/boot/dts/imx6q-prtwd2.dts 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2018 Protonic Holland
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-prti6q.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Protonic WD2 board";
compatible = "prt,prtwd2", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_npd>;
reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
};
/* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
i2c@4 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <20>; /* ~10 kHz */
i2c-gpio,scl-output-only;
#address-cells = <1>;
#size-cells = <0>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>;
clock-names = "ipg", "ahb";
status = "okay";
fixed-link {
speed = <100>;
pause;
full-duplex;
};
};
&i2c3 {
adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
/* V in */
channel@4 {
reg = <4>;
ti,gain = <1>;
ti,datarate = <3>;
};
/* I charge */
channel@5 {
reg = <5>;
ti,gain = <1>;
ti,datarate = <3>;
};
/* V bus */
channel@6 {
reg = <6>;
ti,gain = <1>;
ti,datarate = <3>;
};
/* nc */
channel@7 {
reg = <7>;
ti,gain = <1>;
ti,datarate = <3>;
};
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth_chg>;
pinctrl_can1phy: can1phy {
fsl,pins = <
/* CAN1_SR */
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
/* MX6QDL_ENET_PINGRP4 */
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
/* Phy reset */
MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
/* nINTRP */
MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0
MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0
>;
};
pinctrl_usb_eth_chg: usbethchggrp {
fsl,pins = <
/* USB charging control */
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_wifi_npd: wifinpd {
fsl,pins = <
/* WL_REG_ON */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
>;
};
};
arch/arm/boot/dts/imx6q-tbs2910.dts
View file @ d27895a1
......@@ -99,8 +99,20 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
&hdmi {
......
arch/arm/boot/dts/imx6q-var-dt6customboard.dts
View file @ d27895a1
......@@ -203,6 +203,7 @@ lvds1_out: endpoint {
};
&pwm2 {
#pwm-cells = <2>;
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View file @ d27895a1
......@@ -371,6 +371,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "disabled";
......
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
View file @ d27895a1
......@@ -211,6 +211,7 @@ &pcie {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
View file @ d27895a1
......@@ -336,6 +336,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-colibri.dtsi
View file @ d27895a1
......@@ -312,6 +312,7 @@ &pwm2 {
/* Colibri PWM<A> */
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
......@@ -362,7 +363,6 @@ &uart3 {
};
&usbotg {
pinctrl-names = "default";
disable-over-current;
dr_mode = "peripheral";
status = "disabled";
......
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
View file @ d27895a1
......@@ -233,6 +233,7 @@ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
};
&pwm1 {
#pwm-cells = <2>;
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-emcon.dtsi
View file @ d27895a1
......@@ -737,14 +737,17 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
status = "okay";
};
&pwm3 {
#pwm-cells = <2>;
status = "okay";
};
&pwm4 {
#pwm-cells = <2>;
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -19,6 +20,53 @@ chosen {
bootargs = "console=ttymxc1,115200";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -102,6 +150,103 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -126,13 +271,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -387,6 +525,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
......
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -28,6 +29,53 @@ backlight {
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -165,6 +213,109 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@29 {
gw,mode = <1>;
reg = <0x29>;
label = "vdd_an1";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -189,13 +340,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -365,6 +509,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......@@ -504,6 +649,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -28,6 +29,53 @@ backlight {
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -158,6 +206,115 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_gps";
};
channel@29 {
gw,mode = <1>;
reg = <0x29>;
label = "vdd_an1";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -182,13 +339,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -356,6 +506,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......@@ -486,6 +637,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
......@@ -29,6 +30,53 @@ backlight {
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -195,6 +243,117 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_gps";
};
};
fan-controller@2c {
compatible = "gw,gsc-fan";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2c>;
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -219,13 +378,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -419,6 +571,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default", "state_dio";
pinctrl-0 = <&pinctrl_pwm4_backlight>;
pinctrl-1 = <&pinctrl_pwm4_dio>;
......@@ -571,6 +724,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw551x.dtsi
View file @ d27895a1
......@@ -47,6 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/tda1997x.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
......@@ -63,6 +64,53 @@ chosen {
bootargs = "console=ttymxc1,115200";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -167,6 +215,97 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8a";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0b";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -191,13 +330,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -464,6 +596,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw552x.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -20,6 +21,53 @@ chosen {
bootargs = "console=ttymxc1,115200";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -92,6 +140,103 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -116,13 +261,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -305,6 +443,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw553x.dtsi
View file @ d27895a1
......@@ -46,6 +46,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -61,6 +62,53 @@ chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -130,11 +178,101 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gpio: pca9555@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8a";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0b";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_an1";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
......@@ -428,6 +566,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw560x.dtsi
View file @ d27895a1
......@@ -88,6 +88,53 @@ backlight-keypad {
default-on;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -243,6 +290,115 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_gps";
};
channel@29 {
gw,mode = <1>;
reg = <0x29>;
label = "vdd_an2";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
......@@ -267,13 +423,6 @@ eeprom4: eeprom@53 {
pagesize = <16>;
};
pca9555: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
ds1672: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
......@@ -471,6 +620,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......@@ -608,6 +758,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
......
arch/arm/boot/dts/imx6qdl-gw5903.dtsi
View file @ d27895a1
......@@ -46,6 +46,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
chosen {
......@@ -71,6 +72,53 @@ backlight {
default-brightness-level = <100>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -183,11 +231,101 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9555: gpio@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
......@@ -365,6 +503,7 @@ timing0: g101evn010 {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-gw5904.dtsi
View file @ d27895a1
......@@ -46,6 +46,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -68,6 +69,53 @@ backlight {
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -205,11 +253,101 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9555: gpio@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
......@@ -401,6 +539,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......@@ -503,6 +642,7 @@ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
......
arch/arm/boot/dts/imx6qdl-gw5907.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -19,6 +20,53 @@ chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -102,11 +150,101 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gpio@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
......@@ -133,7 +271,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
......
arch/arm/boot/dts/imx6qdl-gw5910.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -22,6 +23,53 @@ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -111,11 +159,121 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gpio@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
gw,voltage-offset-microvolt = <800000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <22100 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_3p0";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_arm";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_soc";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_1p5";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_1p8";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_1p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_an1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
......
arch/arm/boot/dts/imx6qdl-gw5912.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -20,6 +21,53 @@ chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -106,11 +154,109 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gpio@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
fan-controller@a {
compatible = "gw,gsc-fan";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0a>;
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
......
arch/arm/boot/dts/imx6qdl-gw5913.dtsi
View file @ d27895a1
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
/* these are used by bootloader for disabling nodes */
......@@ -19,6 +20,53 @@ chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -87,11 +135,114 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gpio@23 {
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
gw,voltage-offset-microvolt = <800000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <22100 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_arm";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_soc";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_1p5";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_1p0";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_3p0";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_an1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
......
arch/arm/boot/dts/imx6qdl-icore.dtsi
View file @ d27895a1
......@@ -245,6 +245,7 @@ mipi_csi2_in: endpoint {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
View file @ d27895a1
......@@ -497,6 +497,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......@@ -509,6 +510,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
View file @ d27895a1
......@@ -736,12 +736,14 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
......@@ -754,6 +756,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
View file @ d27895a1
......@@ -639,6 +639,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......@@ -651,6 +652,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View file @ d27895a1
......@@ -596,6 +596,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......@@ -608,6 +609,7 @@ &pwm3 {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
View file @ d27895a1
......@@ -218,6 +218,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-prti6q.dtsi 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2014 Protonic Holland
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart4;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_h1_vbus: regulator-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "h1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg_vbus: regulator-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "otg-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&can1 {
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
temperature-sensor@70 {
compatible = "ti,tmp103";
reg = <0x70>;
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b008
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b008
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
>;
};
};
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View file @ d27895a1
......@@ -800,6 +800,7 @@ timing0: hsd100pxn1 {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View file @ d27895a1
......@@ -687,18 +687,21 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View file @ d27895a1
......@@ -203,9 +203,21 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@1 {
reg = <1>;
qca,clk-out-frequency = <125000000>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
&hdmi {
......@@ -729,6 +741,7 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-savageboard.dtsi
View file @ d27895a1
......@@ -140,6 +140,7 @@ lvds0_out: endpoint {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6qdl-tx6.dtsi
View file @ d27895a1
......@@ -738,14 +738,12 @@ MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
#pwm-cells = <3>;
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
#pwm-cells = <3>;
status = "okay";
};
......
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
View file @ d27895a1
......@@ -719,6 +719,8 @@ &fec {
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <12500000>;
suppress-preamble;
status = "okay";
switch: switch@0 {
......
arch/arm/boot/dts/imx6qdl.dtsi
View file @ d27895a1
......@@ -69,17 +69,6 @@ osc {
};
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
ldb: ldb {
#address-cells = <1>;
#size-cells = <0>;
......@@ -256,7 +245,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -510,7 +499,7 @@ aipstz@207c000 { /* AIPSTZ1 */
};
pwm1: pwm@2080000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
......@@ -521,7 +510,7 @@ pwm1: pwm@2080000 {
};
pwm2: pwm@2084000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
......@@ -532,7 +521,7 @@ pwm2: pwm@2084000 {
};
pwm3: pwm@2088000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
......@@ -543,7 +532,7 @@ pwm3: pwm@2088000 {
};
pwm4: pwm@208c000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
......@@ -795,6 +784,17 @@ reg_soc: regulator-vddsoc {
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
};
usbphy1: usbphy@20c9000 {
......@@ -871,8 +871,7 @@ gpc: gpc@20dc000 {
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&clks IMX6QDL_CLK_IPG>;
clock-names = "ipg";
......@@ -1057,7 +1056,7 @@ mlb@218c000 {
<0 126 IRQ_TYPE_LEVEL_HIGH>;
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1069,7 +1068,7 @@ usdhc1: usdhc@2190000 {
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1081,7 +1080,7 @@ usdhc2: usdhc@2194000 {
status = "disabled";
};
usdhc3: usdhc@2198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1093,7 +1092,7 @@ usdhc3: usdhc@2198000 {
status = "disabled";
};
usdhc4: usdhc@219c000 {
usdhc4: mmc@219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1162,7 +1161,7 @@ weim: weim@21b8000 {
status = "disabled";
};
ocotp: ocotp-ctrl@21bc000 {
ocotp: efuse@21bc000 {
compatible = "fsl,imx6q-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6QDL_CLK_IIM>;
......
arch/arm/boot/dts/imx6qp-sabreauto.dts
View file @ d27895a1
......@@ -50,6 +50,10 @@ &pcie {
status = "disabled";
};
&sata {
status = "okay";
};
&vgen3_reg {
regulator-always-on;
};
arch/arm/boot/dts/imx6qp-sabresd.dts
View file @ d27895a1
......@@ -53,3 +53,7 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
&pcie {
status = "disabled";
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6sl-evk.dts
View file @ d27895a1
......@@ -575,6 +575,7 @@ display_out: endpoint {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6sl.dtsi
View file @ d27895a1
......@@ -93,16 +93,6 @@ osc {
};
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&gpc>;
......@@ -136,7 +126,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -344,7 +334,7 @@ uart4: serial@2038000 {
};
pwm1: pwm@2080000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
......@@ -354,7 +344,7 @@ pwm1: pwm@2080000 {
};
pwm2: pwm@2084000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
......@@ -364,7 +354,7 @@ pwm2: pwm@2084000 {
};
pwm3: pwm@2088000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
......@@ -374,7 +364,7 @@ pwm3: pwm@2088000 {
};
pwm4: pwm@208c000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
......@@ -628,6 +618,16 @@ reg_soc: regulator-vddsoc {
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
};
usbphy1: usbphy@20c9000 {
......@@ -854,7 +854,7 @@ fec: ethernet@2188000 {
status = "disabled";
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
......@@ -866,7 +866,7 @@ usdhc1: usdhc@2190000 {
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
......@@ -878,7 +878,7 @@ usdhc2: usdhc@2194000 {
status = "disabled";
};
usdhc3: usdhc@2198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
......@@ -890,7 +890,7 @@ usdhc3: usdhc@2198000 {
status = "disabled";
};
usdhc4: usdhc@219c000 {
usdhc4: mmc@219c000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
......@@ -952,7 +952,7 @@ weim: weim@21b8000 {
status = "disabled";
};
ocotp: ocotp-ctrl@21bc000 {
ocotp: efuse@21bc000 {
compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCOTP>;
......
arch/arm/boot/dts/imx6sll-evk.dts
View file @ d27895a1
......@@ -260,6 +260,7 @@ display_out: endpoint {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6sll.dtsi
View file @ d27895a1
......@@ -105,16 +105,6 @@ ipp_di1: clock-ipp-di1 {
clock-output-names = "ipp_di1";
};
tempmon: temperature-sensor {
compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -136,7 +126,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -271,7 +261,7 @@ uart2: serial@2024000 {
status = "disabled";
};
ssi1: ssi-controller@2028000 {
ssi1: ssi@2028000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
......@@ -284,7 +274,7 @@ ssi1: ssi-controller@2028000 {
status = "disabled";
};
ssi2: ssi-controller@202c000 {
ssi2: ssi@202c000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
......@@ -297,7 +287,7 @@ ssi2: ssi-controller@202c000 {
status = "disabled";
};
ssi3: ssi-controller@2030000 {
ssi3: ssi@2030000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
......@@ -331,7 +321,7 @@ pwm1: pwm@2080000 {
clocks = <&clks IMX6SLL_CLK_PWM1>,
<&clks IMX6SLL_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm2: pwm@2084000 {
......@@ -341,7 +331,7 @@ pwm2: pwm@2084000 {
clocks = <&clks IMX6SLL_CLK_PWM2>,
<&clks IMX6SLL_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm3: pwm@2088000 {
......@@ -351,7 +341,7 @@ pwm3: pwm@2088000 {
clocks = <&clks IMX6SLL_CLK_PWM3>,
<&clks IMX6SLL_CLK_PWM3>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm4: pwm@208c000 {
......@@ -361,7 +351,7 @@ pwm4: pwm@208c000 {
clocks = <&clks IMX6SLL_CLK_PWM4>,
<&clks IMX6SLL_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
gpt1: timer@2098000 {
......@@ -531,6 +521,16 @@ reg_3p0: regulator-3p0@20c8120 {
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
tempmon: temperature-sensor {
compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
};
};
usbphy1: usb-phy@20c9000 {
......@@ -786,7 +786,7 @@ mmdc: memory-controller@21b0000 {
clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
ocotp: ocotp-ctrl@21bc000 {
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sll-ocotp", "syscon";
......
arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
View file @ d27895a1
......@@ -229,6 +229,7 @@ &pcie {
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
......
arch/arm/boot/dts/imx6sx-sabreauto.dts
View file @ d27895a1
......@@ -66,12 +66,68 @@ reg_can_stby: regulator-can-stby {
enable-active-high;
vin-supply = <&reg_can_en>;
};
reg_cs42888: cs42888_supply {
compatible = "regulator-fixed";
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound-cs42888 {
compatible = "fsl,imx6-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
audio-cpu = <&esai>;
audio-asrc = <&asrc>;
audio-codec = <&cs42888>;
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "Line In Jack",
"AIN1R", "Line In Jack",
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
};
};
&anaclk2 {
clock-frequency = <24576000>;
};
&clks {
assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
<&clks IMX6SX_PLL4_BYPASS>,
<&clks IMX6SX_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
<&clks IMX6SX_PLL4_BYPASS_SRC>;
assigned-clock-rates = <0>, <0>, <24576000>;
};
&esai {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai>;
assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
<&clks IMX6SX_CLK_ESAI_EXTAL>;
assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
......@@ -193,6 +249,21 @@ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_esai: esaigrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
......@@ -227,6 +298,12 @@ MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
......@@ -313,6 +390,17 @@ &i2c2 {
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&anaclk2 0>;
clock-names = "mclk";
VA-supply = <&reg_cs42888>;
VD-supply = <&reg_cs42888>;
VLS-supply = <&reg_cs42888>;
VLC-supply = <&reg_cs42888>;
};
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
......@@ -454,6 +542,14 @@ max7310_b: gpio@32 {
};
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
......
arch/arm/boot/dts/imx6sx-sdb-mqs.dts 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include "imx6sx-sdb.dts"
/ {
sound {
status = "disabled";
};
sound-mqs {
compatible = "fsl,imx6sx-sdb-mqs",
"fsl,imx-audio-mqs";
model = "mqs-audio";
audio-cpu = <&sai1>;
audio-asrc = <&asrc>;
audio-codec = <&mqs>;
};
};
&usdhc2 {
/* pin conflict with mqs*/
status = "disabled";
};
&mqs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mqs>;
clocks = <&clks IMX6SX_CLK_SAI1>;
clock-names = "mclk";
status = "okay";
};
&sai1 {
pinctrl-0 = <>;
status = "okay";
};
&ssi2 {
status = "disabled";
};
&sdma {
gpr = <&gpr>;
/* SDMA event remap for SAI1 */
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
};
arch/arm/boot/dts/imx6sx-sdb.dtsi
View file @ d27895a1
......@@ -179,6 +179,15 @@ panel_in: endpoint {
};
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif",
"fsl,imx6sx-sdb-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-out;
};
};
&audmux {
......@@ -281,6 +290,7 @@ display_out: endpoint {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......@@ -296,6 +306,14 @@ &sai1 {
status = "disabled";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&ssi2 {
status = "okay";
};
......@@ -505,6 +523,13 @@ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_mqs: mqsgrp {
fsl,pins = <
MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
......@@ -562,6 +587,12 @@ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
......
arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
View file @ d27895a1
......@@ -505,18 +505,21 @@ &pcie {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm6 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
......
arch/arm/boot/dts/imx6sx.dtsi
View file @ d27895a1
......@@ -134,14 +134,10 @@ anaclk2: clock-anaclk2 {
clock-output-names = "anaclk2";
};
tempmon: tempmon {
compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
mqs: mqs {
compatible = "fsl,imx6sx-mqs";
gpr = <&gpr>;
status = "disabled";
};
pmu {
......@@ -183,7 +179,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -335,6 +331,7 @@ uart1: serial@2020000 {
};
esai: esai@2024000 {
compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
......@@ -344,6 +341,9 @@ esai: esai@2024000 {
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "mem", "extal",
"fsys", "spba";
dmas = <&sdma 23 21 0>,
<&sdma 24 21 0>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -390,18 +390,28 @@ ssi3: ssi@2030000 {
};
asrc: asrc@2034000 {
compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
<&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_SPDIF>,
clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck", "spba";
dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
<&sdma 19 20 1>, <&sdma 20 20 1>,
<&sdma 21 20 1>, <&sdma 22 20 1>;
clock-names = "mem", "ipg", "asrck_0",
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
"asrck_d", "asrck_e", "asrck_f", "spba";
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
<&sdma 19 23 1>, <&sdma 20 23 1>,
<&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
};
......@@ -413,7 +423,7 @@ pwm1: pwm@2080000 {
clocks = <&clks IMX6SX_CLK_PWM1>,
<&clks IMX6SX_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm2: pwm@2084000 {
......@@ -423,7 +433,7 @@ pwm2: pwm@2084000 {
clocks = <&clks IMX6SX_CLK_PWM2>,
<&clks IMX6SX_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm3: pwm@2088000 {
......@@ -433,7 +443,7 @@ pwm3: pwm@2088000 {
clocks = <&clks IMX6SX_CLK_PWM3>,
<&clks IMX6SX_CLK_PWM3>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm4: pwm@208c000 {
......@@ -443,7 +453,7 @@ pwm4: pwm@208c000 {
clocks = <&clks IMX6SX_CLK_PWM4>,
<&clks IMX6SX_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
flexcan1: can@2090000 {
......@@ -696,6 +706,16 @@ reg_soc: regulator-vddsoc {
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
};
};
usbphy1: usbphy@20c9000 {
......@@ -943,7 +963,7 @@ mlb: mlb@218c000 {
status = "disabled";
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
......@@ -955,7 +975,7 @@ usdhc1: usdhc@2190000 {
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
......@@ -967,7 +987,7 @@ usdhc2: usdhc@2194000 {
status = "disabled";
};
usdhc3: usdhc@2198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
......@@ -979,7 +999,7 @@ usdhc3: usdhc@2198000 {
status = "disabled";
};
usdhc4: usdhc@219c000 {
usdhc4: mmc@219c000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1055,7 +1075,7 @@ weim: weim@21b8000 {
status = "disabled";
};
ocotp: ocotp-ctrl@21bc000 {
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sx-ocotp", "syscon";
......@@ -1337,7 +1357,7 @@ pwm5: pwm@22a4000 {
clocks = <&clks IMX6SX_CLK_PWM5>,
<&clks IMX6SX_CLK_PWM5>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm6: pwm@22a8000 {
......@@ -1347,7 +1367,7 @@ pwm6: pwm@22a8000 {
clocks = <&clks IMX6SX_CLK_PWM6>,
<&clks IMX6SX_CLK_PWM6>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm7: pwm@22ac000 {
......@@ -1357,7 +1377,7 @@ pwm7: pwm@22ac000 {
clocks = <&clks IMX6SX_CLK_PWM7>,
<&clks IMX6SX_CLK_PWM7>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm8: pwm@22b0000 {
......@@ -1367,7 +1387,7 @@ pwm8: pwm@22b0000 {
clocks = <&clks IMX6SX_CLK_PWM8>,
<&clks IMX6SX_CLK_PWM8>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
};
......
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
View file @ d27895a1
......@@ -228,6 +228,7 @@ display_out: endpoint {
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
View file @ d27895a1
......@@ -168,6 +168,7 @@ &pwm4 {
};
&pwm5 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-geam.dts
View file @ d27895a1
......@@ -195,6 +195,7 @@ timing0: timing0 {
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi
View file @ d27895a1
......@@ -155,6 +155,7 @@ lcdif_out: endpoint {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-isiot.dtsi
View file @ d27895a1
......@@ -187,6 +187,7 @@ timing0: timing0 {
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
View file @ d27895a1
......@@ -41,6 +41,7 @@ &lcdif {
};
&pwm7 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
View file @ d27895a1
......@@ -153,6 +153,7 @@ rtc@32 {
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-pico.dtsi
View file @ d27895a1
......@@ -175,6 +175,7 @@ display_out: endpoint {
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
......
arch/arm/boot/dts/imx6ul-tx6ul.dtsi
View file @ d27895a1
......@@ -549,7 +549,6 @@ ETQ570 {
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
#pwm-cells = <3>;
status = "okay";
};
......
arch/arm/boot/dts/imx6ul.dtsi
View file @ d27895a1
......@@ -131,16 +131,6 @@ ipp_di1: clock-di1 {
clock-output-names = "ipp_di1";
};
tempmon: tempmon {
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&gpc>;
......@@ -351,6 +341,31 @@ sai3: sai@2030000 {
dma-names = "rx", "tx";
status = "disabled";
};
asrc: asrc@2034000 {
compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
reg = <0x2034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
<&clks IMX6UL_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck_0",
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
"asrck_d", "asrck_e", "asrck_f", "spba";
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
};
tsc: tsc@2040000 {
......@@ -371,7 +386,7 @@ pwm1: pwm@2080000 {
clocks = <&clks IMX6UL_CLK_PWM1>,
<&clks IMX6UL_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -382,7 +397,7 @@ pwm2: pwm@2084000 {
clocks = <&clks IMX6UL_CLK_PWM2>,
<&clks IMX6UL_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -393,7 +408,7 @@ pwm3: pwm@2088000 {
clocks = <&clks IMX6UL_CLK_PWM3>,
<&clks IMX6UL_CLK_PWM3>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -404,7 +419,7 @@ pwm4: pwm@208c000 {
clocks = <&clks IMX6UL_CLK_PWM4>,
<&clks IMX6UL_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -612,6 +627,16 @@ reg_soc: regulator-vddsoc {
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
};
};
usbphy1: usbphy@20c9000 {
......@@ -734,7 +759,7 @@ pwm5: pwm@20f0000 {
clocks = <&clks IMX6UL_CLK_PWM5>,
<&clks IMX6UL_CLK_PWM5>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -745,7 +770,7 @@ pwm6: pwm@20f4000 {
clocks = <&clks IMX6UL_CLK_PWM6>,
<&clks IMX6UL_CLK_PWM6>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -756,7 +781,7 @@ pwm7: pwm@20f8000 {
clocks = <&clks IMX6UL_CLK_PWM7>,
<&clks IMX6UL_CLK_PWM7>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -767,7 +792,7 @@ pwm8: pwm@20fc000 {
clocks = <&clks IMX6UL_CLK_PWM8>,
<&clks IMX6UL_CLK_PWM8>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
};
......@@ -861,7 +886,7 @@ fec1: ethernet@2188000 {
status = "disabled";
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
......@@ -875,7 +900,7 @@ usdhc1: usdhc@2190000 {
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
......@@ -948,7 +973,7 @@ weim: weim@21b8000 {
status = "disabled";
};
ocotp: ocotp-ctrl@21bc000 {
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6ul-ocotp", "syscon";
......
arch/arm/boot/dts/imx6ull-colibri.dtsi
View file @ d27895a1
......@@ -145,25 +145,21 @@ &lcdif {
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
#pwm-cells = <3>;
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
#pwm-cells = <3>;
};
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
#pwm-cells = <3>;
};
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
#pwm-cells = <3>;
};
&sdma {
......
arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-myir-mys-6ulx.dtsi"
/ {
model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
};
&gpmi {
status = "okay";
};
arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi 0 → 100644
View file @ d27895a1
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "MYiR MYS-6ULX Single Board Computer";
compatible = "fsl,imx6ull";
chosen {
stdout-path = &uart1;
};
reg_vdd_5v: regulator-vdd-5v {
compatible = "regulator-fixed";
regulator-name = "VDD_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_vdd_5v>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-supply = <&reg_vdd_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_vdd_3v3>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
non-removable;
keep-power-in-suspend;
vmmc-supply = <&reg_vdd_3v3>;
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};
arch/arm/boot/dts/imx7s.dtsi
View file @ d27895a1
......@@ -147,16 +147,6 @@ replicator_in_port0: endpoint {
};
};
tempmon: tempmon {
compatible = "fsl,imx7d-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&intc>;
......@@ -536,7 +526,7 @@ csi_mux_to_csi: endpoint {
};
};
ocotp: ocotp-ctrl@30350000 {
ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx7d-ocotp", "syscon";
......@@ -586,6 +576,16 @@ reg_1p2: regulator-vdd1p2 {
anatop-max-voltage = <1300000>;
anatop-enable-bit = <0>;
};
tempmon: tempmon {
compatible = "fsl,imx7d-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
};
snvs: snvs@30370000 {
......@@ -1126,7 +1126,7 @@ usbmisc3: usbmisc@30b30200 {
reg = <0x30b30200 0x200>;
};
usdhc1: usdhc@30b40000 {
usdhc1: mmc@30b40000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1138,7 +1138,7 @@ usdhc1: usdhc@30b40000 {
status = "disabled";
};
usdhc2: usdhc@30b50000 {
usdhc2: mmc@30b50000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1150,7 +1150,7 @@ usdhc2: usdhc@30b50000 {
status = "disabled";
};
usdhc3: usdhc@30b60000 {
usdhc3: mmc@30b60000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm/boot/dts/imx7ulp.dtsi
View file @ d27895a1
......@@ -452,7 +452,7 @@ sim: sim@410a3000 {
reg = <0x410a3000 0x1000>;
};
ocotp: ocotp-ctrl@410a6000 {
ocotp: efuse@410a6000 {
compatible = "fsl,imx7ulp-ocotp", "syscon";
reg = <0x410a6000 0x4000>;
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
......
arch/arm/boot/dts/ls1021a.dtsi
View file @ d27895a1
......@@ -59,6 +59,7 @@ aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
rtc1 = &ftm_alarm0;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
......@@ -772,7 +773,7 @@ ptp_clock@2d10e00 {
fsl,tmr-prsc = <2>;
fsl,tmr-add = <0xaaaaaaab>;
fsl,tmr-fiper1 = <999999995>;
fsl,tmr-fiper2 = <99990>;
fsl,tmr-fiper2 = <999999995>;
fsl,max-adj = <499999999>;
fsl,extts-fifo;
};
......@@ -1002,5 +1003,19 @@ qdma: dma-controller@8390000 {
big-endian;
};
rcpm: power-controller@1ee2140 {
compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x8>;
#fsl,rcpm-wakeup-cells = <2>;
};
ftm_alarm0: timer0@29d0000 {
compatible = "fsl,ls1021a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
reg-names = "ftm";
fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
};
};
};
arch/arm/boot/dts/vf610-zii-cfu1.dts
View file @ d27895a1
......@@ -158,6 +158,8 @@ fixed-link {
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <12500000>;
suppress-preamble;
status = "okay";
switch0: switch0@0 {
......
arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
View file @ d27895a1
......@@ -164,7 +164,7 @@ port@4 {
port@9 {
reg = <9>;
label = "sff2";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff2>;
};
......
arch/arm/boot/dts/vf610-zii-dev.dtsi
View file @ d27895a1
......@@ -137,6 +137,8 @@ fixed-link {
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <12500000>;
suppress-preamble;
status = "okay";
};
};
......
arch/arm/boot/dts/vf610-zii-scu4-aib.dts
View file @ d27895a1
......@@ -186,7 +186,7 @@ ports {
port@2 {
reg = <2>;
label = "eth_fc_1000_2";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff1>;
};
......@@ -194,7 +194,7 @@ port@2 {
port@3 {
reg = <3>;
label = "eth_fc_1000_3";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff2>;
};
......@@ -202,7 +202,7 @@ port@3 {
port@4 {
reg = <4>;
label = "eth_fc_1000_4";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff3>;
};
......@@ -210,7 +210,7 @@ port@4 {
port@5 {
reg = <5>;
label = "eth_fc_1000_5";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff4>;
};
......@@ -218,7 +218,7 @@ port@5 {
port@6 {
reg = <6>;
label = "eth_fc_1000_6";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff5>;
};
......@@ -226,7 +226,7 @@ port@6 {
port@7 {
reg = <7>;
label = "eth_fc_1000_7";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff6>;
};
......@@ -234,7 +234,7 @@ port@7 {
port@9 {
reg = <9>;
label = "eth_fc_1000_1";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff0>;
};
......@@ -269,7 +269,7 @@ ports {
port@2 {
reg = <2>;
label = "eth_fc_1000_8";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff7>;
};
......@@ -277,7 +277,7 @@ port@2 {
port@3 {
reg = <3>;
label = "eth_fc_1000_9";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff8>;
};
......@@ -285,7 +285,7 @@ port@3 {
port@4 {
reg = <4>;
label = "eth_fc_1000_10";
phy-mode = "sgmii";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff9>;
};
......
arch/arm/boot/dts/vf610-zii-spb4.dts
View file @ d27895a1
......@@ -119,6 +119,8 @@ fixed-link {
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <12500000>;
suppress-preamble;
status = "okay";
switch0: switch0@0 {
......@@ -207,6 +209,18 @@ eeprom@52 {
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
};
};
&snvsrtc {
status = "disabled";
};
......@@ -324,6 +338,13 @@ VF610_PAD_PTB15__I2C0_SDA 0x37ff
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
VF610_PAD_PTB16__I2C1_SCL 0x37ff
VF610_PAD_PTB17__I2C1_SDA 0x37ff
>;
};
pinctrl_leds_debug: pinctrl-leds-debug {
fsl,pins = <
VF610_PAD_PTD3__GPIO_82 0x31c2
......
arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
View file @ d27895a1
......@@ -81,6 +81,8 @@ &esdhc0 {
non-removable;
no-1-8-v;
keep-power-in-suspend;
no-sdio;
no-sd;
status = "okay";
};
......@@ -88,6 +90,7 @@ &esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
no-sdio;
status = "okay";
};
......@@ -105,6 +108,8 @@ fixed-link {
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <12500000>;
suppress-preamble;
status = "okay";
switch0: switch0@0 {
......
arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
View file @ d27895a1
......@@ -133,6 +133,8 @@ fixed-link {
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <12500000>;
suppress-preamble;
status = "okay";
switch0: switch0@0 {
......@@ -226,6 +228,18 @@ eeprom@52 {
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
};
};
&snvsrtc {
status = "disabled";
};
......
arch/arm/boot/dts/vf610.dtsi
View file @ d27895a1
......@@ -10,7 +10,7 @@ &a5_cpu {
};
&aips0 {
L2: l2-cache@40006000 {
L2: cache-controller@40006000 {
compatible = "arm,pl310-cache";
reg = <0x40006000 0x1000>;
cache-unified;
......
arch/arm/boot/dts/vfxxx.dtsi
View file @ d27895a1
......@@ -729,6 +729,28 @@ i2c3: i2c@400e7000 {
dma-names = "rx","tx";
status = "disabled";
};
crypto: crypto@400f0000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x400f0000 0x9000>;
ranges = <0 0x400f0000 0x9000>;
clocks = <&clks VF610_CLK_CAAM>;
clock-names = "ipg";
sec_jr0: jr0@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
};
drivers/clk/imx/clk-imx8mp.c
View file @ d27895a1
......@@ -680,6 +680,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0);
hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
......
drivers/clk/imx/clk-vf610.c
View file @ d27895a1
......@@ -438,6 +438,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
clk[VF610_CLK_CAAM] = imx_clk_gate2("caam", "ipg_bus", CCM_CCGR11, CCM_CCGRx_CGn(0));
imx_check_clocks(clk, ARRAY_SIZE(clk));
......
include/dt-bindings/clock/vf610-clock.h
View file @ d27895a1
......@@ -195,6 +195,7 @@
#define VF610_CLK_WKPU 186
#define VF610_CLK_TCON0 187
#define VF610_CLK_TCON1 188
#define VF610_CLK_END 189
#define VF610_CLK_CAAM 189
#define VF610_CLK_END 190
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
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