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Commit d294ad82 authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch 'net-ll_temac-cleanup-for-clearing-static-warnings' 

Haoyue Xu says:

====================
net: ll_temac: Cleanup for clearing static warnings

Most static warnings are detected by Checkpatch.pl, mainly about:
(1) #1: About the comments.
(2) #2: About function name in a string.
(3) #3: About the open parenthesis.
(4) #4: About the else branch.
(6) #6: About trailing statements.
(7) #5,#7: About blank lines and spaces.
====================

Link: https://lore.kernel.org/r/20220917103843.526877-1-xuhaoyue1@hisilicon.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents d57aae2e 7fe85bb3
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Showing with 139 additions and 123 deletions
drivers/net/ethernet/xilinx/ll_temac.h
View file @ d294ad82
...@@ -21,36 +21,45 @@ ...@@ -21,36 +21,45 @@
/* Configuration options */ /* Configuration options */
/* Accept all incoming packets. /* Accept all incoming packets.
* This option defaults to disabled (cleared) */ * This option defaults to disabled (cleared)
*/
#define XTE_OPTION_PROMISC (1 << 0) #define XTE_OPTION_PROMISC (1 << 0)
/* Jumbo frame support for Tx & Rx. /* Jumbo frame support for Tx & Rx.
* This option defaults to disabled (cleared) */ * This option defaults to disabled (cleared)
*/
#define XTE_OPTION_JUMBO (1 << 1) #define XTE_OPTION_JUMBO (1 << 1)
/* VLAN Rx & Tx frame support. /* VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */ * This option defaults to disabled (cleared)
*/
#define XTE_OPTION_VLAN (1 << 2) #define XTE_OPTION_VLAN (1 << 2)
/* Enable recognition of flow control frames on Rx /* Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */ * This option defaults to enabled (set)
*/
#define XTE_OPTION_FLOW_CONTROL (1 << 4) #define XTE_OPTION_FLOW_CONTROL (1 << 4)
/* Strip FCS and PAD from incoming frames. /* Strip FCS and PAD from incoming frames.
* Note: PAD from VLAN frames is not stripped. * Note: PAD from VLAN frames is not stripped.
* This option defaults to disabled (set) */ * This option defaults to disabled (set)
*/
#define XTE_OPTION_FCS_STRIP (1 << 5) #define XTE_OPTION_FCS_STRIP (1 << 5)
/* Generate FCS field and add PAD automatically for outgoing frames. /* Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to enabled (set) */ * This option defaults to enabled (set)
*/
#define XTE_OPTION_FCS_INSERT (1 << 6) #define XTE_OPTION_FCS_INSERT (1 << 6)
/* Enable Length/Type error checking for incoming frames. When this option is /* Enable Length/Type error checking for incoming frames. When this option is
set, the MAC will filter frames that have a mismatched type/length field * set, the MAC will filter frames that have a mismatched type/length field
and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these * and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
types of frames are encountered. When this option is cleared, the MAC will * types of frames are encountered. When this option is cleared, the MAC will
allow these types of frames to be received. * allow these types of frames to be received.
This option defaults to enabled (set) */ * This option defaults to enabled (set)
*/
#define XTE_OPTION_LENTYPE_ERR (1 << 7) #define XTE_OPTION_LENTYPE_ERR (1 << 7)
/* Enable the transmitter. /* Enable the transmitter.
* This option defaults to enabled (set) */ * This option defaults to enabled (set)
*/
#define XTE_OPTION_TXEN (1 << 11) #define XTE_OPTION_TXEN (1 << 11)
/* Enable the receiver /* Enable the receiver
* This option defaults to enabled (set) */ * This option defaults to enabled (set)
*/
#define XTE_OPTION_RXEN (1 << 12) #define XTE_OPTION_RXEN (1 << 12)
/* Default options set when device is initialized or reset */ /* Default options set when device is initialized or reset */
...@@ -68,18 +77,18 @@ This option defaults to enabled (set) */ ...@@ -68,18 +77,18 @@ This option defaults to enabled (set) */
#define TX_TAILDESC_PTR 0x04 /* rw */ #define TX_TAILDESC_PTR 0x04 /* rw */
#define TX_CHNL_CTRL 0x05 /* rw */ #define TX_CHNL_CTRL 0x05 /* rw */
/* /*
0:7 24:31 IRQTimeout * 0:7 24:31 IRQTimeout
8:15 16:23 IRQCount * 8:15 16:23 IRQCount
16:20 11:15 Reserved * 16:20 11:15 Reserved
21 10 0 * 21 10 0
22 9 UseIntOnEnd * 22 9 UseIntOnEnd
23 8 LdIRQCnt * 23 8 LdIRQCnt
24 7 IRQEn * 24 7 IRQEn
25:28 3:6 Reserved * 25:28 3:6 Reserved
29 2 IrqErrEn * 29 2 IrqErrEn
30 1 IrqDlyEn * 30 1 IrqDlyEn
31 0 IrqCoalEn * 31 0 IrqCoalEn
*/ */
#define CHNL_CTRL_IRQ_IOE (1 << 9) #define CHNL_CTRL_IRQ_IOE (1 << 9)
#define CHNL_CTRL_IRQ_EN (1 << 7) #define CHNL_CTRL_IRQ_EN (1 << 7)
#define CHNL_CTRL_IRQ_ERR_EN (1 << 2) #define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
...@@ -87,35 +96,35 @@ This option defaults to enabled (set) */ ...@@ -87,35 +96,35 @@ This option defaults to enabled (set) */
#define CHNL_CTRL_IRQ_COAL_EN (1 << 0) #define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
#define TX_IRQ_REG 0x06 /* rw */ #define TX_IRQ_REG 0x06 /* rw */
/* /*
0:7 24:31 DltTmrValue * 0:7 24:31 DltTmrValue
8:15 16:23 ClscCntrValue * 8:15 16:23 ClscCntrValue
16:17 14:15 Reserved * 16:17 14:15 Reserved
18:21 10:13 ClscCnt * 18:21 10:13 ClscCnt
22:23 8:9 DlyCnt * 22:23 8:9 DlyCnt
24:28 3::7 Reserved * 24:28 3::7 Reserved
29 2 ErrIrq * 29 2 ErrIrq
30 1 DlyIrq * 30 1 DlyIrq
31 0 CoalIrq * 31 0 CoalIrq
*/ */
#define TX_CHNL_STS 0x07 /* r */ #define TX_CHNL_STS 0x07 /* r */
/* /*
0:9 22:31 Reserved * 0:9 22:31 Reserved
10 21 TailPErr * 10 21 TailPErr
11 20 CmpErr * 11 20 CmpErr
12 19 AddrErr * 12 19 AddrErr
13 18 NxtPErr * 13 18 NxtPErr
14 17 CurPErr * 14 17 CurPErr
15 16 BsyWr * 15 16 BsyWr
16:23 8:15 Reserved * 16:23 8:15 Reserved
24 7 Error * 24 7 Error
25 6 IOE * 25 6 IOE
26 5 SOE * 26 5 SOE
27 4 Cmplt * 27 4 Cmplt
28 3 SOP * 28 3 SOP
29 2 EOP * 29 2 EOP
30 1 EngBusy * 30 1 EngBusy
31 0 Reserved * 31 0 Reserved
*/ */
#define RX_NXTDESC_PTR 0x08 /* r */ #define RX_NXTDESC_PTR 0x08 /* r */
#define RX_CURBUF_ADDR 0x09 /* r */ #define RX_CURBUF_ADDR 0x09 /* r */
...@@ -124,17 +133,17 @@ This option defaults to enabled (set) */ ...@@ -124,17 +133,17 @@ This option defaults to enabled (set) */
#define RX_TAILDESC_PTR 0x0c /* rw */ #define RX_TAILDESC_PTR 0x0c /* rw */
#define RX_CHNL_CTRL 0x0d /* rw */ #define RX_CHNL_CTRL 0x0d /* rw */
/* /*
0:7 24:31 IRQTimeout * 0:7 24:31 IRQTimeout
8:15 16:23 IRQCount * 8:15 16:23 IRQCount
16:20 11:15 Reserved * 16:20 11:15 Reserved
21 10 0 * 21 10 0
22 9 UseIntOnEnd * 22 9 UseIntOnEnd
23 8 LdIRQCnt * 23 8 LdIRQCnt
24 7 IRQEn * 24 7 IRQEn
25:28 3:6 Reserved * 25:28 3:6 Reserved
29 2 IrqErrEn * 29 2 IrqErrEn
30 1 IrqDlyEn * 30 1 IrqDlyEn
31 0 IrqCoalEn * 31 0 IrqCoalEn
*/ */
#define RX_IRQ_REG 0x0e /* rw */ #define RX_IRQ_REG 0x0e /* rw */
#define IRQ_COAL (1 << 0) #define IRQ_COAL (1 << 0)
...@@ -142,13 +151,13 @@ This option defaults to enabled (set) */ ...@@ -142,13 +151,13 @@ This option defaults to enabled (set) */
#define IRQ_ERR (1 << 2) #define IRQ_ERR (1 << 2)
#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */ #define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
/* /*
0:7 24:31 DltTmrValue * 0:7 24:31 DltTmrValue
8:15 16:23 ClscCntrValue * 8:15 16:23 ClscCntrValue
16:17 14:15 Reserved * 16:17 14:15 Reserved
18:21 10:13 ClscCnt * 18:21 10:13 ClscCnt
22:23 8:9 DlyCnt * 22:23 8:9 DlyCnt
24:28 3::7 Reserved * 24:28 3::7 Reserved
*/ */
#define RX_CHNL_STS 0x0f /* r */ #define RX_CHNL_STS 0x0f /* r */
#define CHNL_STS_ENGBUSY (1 << 1) #define CHNL_STS_ENGBUSY (1 << 1)
#define CHNL_STS_EOP (1 << 2) #define CHNL_STS_EOP (1 << 2)
...@@ -165,23 +174,23 @@ This option defaults to enabled (set) */ ...@@ -165,23 +174,23 @@ This option defaults to enabled (set) */
#define CHNL_STS_CMPERR (1 << 20) #define CHNL_STS_CMPERR (1 << 20)
#define CHNL_STS_TAILERR (1 << 21) #define CHNL_STS_TAILERR (1 << 21)
/* /*
0:9 22:31 Reserved * 0:9 22:31 Reserved
10 21 TailPErr * 10 21 TailPErr
11 20 CmpErr * 11 20 CmpErr
12 19 AddrErr * 12 19 AddrErr
13 18 NxtPErr * 13 18 NxtPErr
14 17 CurPErr * 14 17 CurPErr
15 16 BsyWr * 15 16 BsyWr
16:23 8:15 Reserved * 16:23 8:15 Reserved
24 7 Error * 24 7 Error
25 6 IOE * 25 6 IOE
26 5 SOE * 26 5 SOE
27 4 Cmplt * 27 4 Cmplt
28 3 SOP * 28 3 SOP
29 2 EOP * 29 2 EOP
30 1 EngBusy * 30 1 EngBusy
31 0 Reserved * 31 0 Reserved
*/ */
#define DMA_CONTROL_REG 0x10 /* rw */ #define DMA_CONTROL_REG 0x10 /* rw */
#define DMA_CONTROL_RST (1 << 0) #define DMA_CONTROL_RST (1 << 0)
......
drivers/net/ethernet/xilinx/ll_temac_main.c
View file @ d294ad82
...@@ -117,7 +117,7 @@ int temac_indirect_busywait(struct temac_local *lp) ...@@ -117,7 +117,7 @@ int temac_indirect_busywait(struct temac_local *lp)
spin_until_cond(hard_acs_rdy_or_timeout(lp, timeout)); spin_until_cond(hard_acs_rdy_or_timeout(lp, timeout));
if (WARN_ON(!hard_acs_rdy(lp))) if (WARN_ON(!hard_acs_rdy(lp)))
return -ETIMEDOUT; return -ETIMEDOUT;
else
return 0; return 0;
} }
...@@ -307,12 +307,10 @@ static void temac_dma_bd_release(struct net_device *ndev) ...@@ -307,12 +307,10 @@ static void temac_dma_bd_release(struct net_device *ndev)
for (i = 0; i < lp->rx_bd_num; i++) { for (i = 0; i < lp->rx_bd_num; i++) {
if (!lp->rx_skb[i]) if (!lp->rx_skb[i])
break; break;
else {
dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys, dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE); XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
dev_kfree_skb(lp->rx_skb[i]); dev_kfree_skb(lp->rx_skb[i]);
} }
}
if (lp->rx_bd_v) if (lp->rx_bd_v)
dma_free_coherent(ndev->dev.parent, dma_free_coherent(ndev->dev.parent,
sizeof(*lp->rx_bd_v) * lp->rx_bd_num, sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
...@@ -430,7 +428,8 @@ static void temac_do_set_mac_address(struct net_device *ndev) ...@@ -430,7 +428,8 @@ static void temac_do_set_mac_address(struct net_device *ndev)
(ndev->dev_addr[2] << 16) | (ndev->dev_addr[2] << 16) |
(ndev->dev_addr[3] << 24)); (ndev->dev_addr[3] << 24));
/* There are reserved bits in EUAW1 /* There are reserved bits in EUAW1
* so don't affect them Set MAC bits [47:32] in EUAW1 */ * so don't affect them Set MAC bits [47:32] in EUAW1
*/
temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET, temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,
(ndev->dev_addr[4] & 0x000000ff) | (ndev->dev_addr[4] & 0x000000ff) |
(ndev->dev_addr[5] << 8)); (ndev->dev_addr[5] << 8));
...@@ -530,66 +529,66 @@ static struct temac_option { ...@@ -530,66 +529,66 @@ static struct temac_option {
{ {
.opt = XTE_OPTION_JUMBO, .opt = XTE_OPTION_JUMBO,
.reg = XTE_RXC1_OFFSET, .reg = XTE_RXC1_OFFSET,
.m_or =XTE_RXC1_RXJMBO_MASK, .m_or = XTE_RXC1_RXJMBO_MASK,
}, },
/* Turn on VLAN packet support for both Rx and Tx */ /* Turn on VLAN packet support for both Rx and Tx */
{ {
.opt = XTE_OPTION_VLAN, .opt = XTE_OPTION_VLAN,
.reg = XTE_TXC_OFFSET, .reg = XTE_TXC_OFFSET,
.m_or =XTE_TXC_TXVLAN_MASK, .m_or = XTE_TXC_TXVLAN_MASK,
}, },
{ {
.opt = XTE_OPTION_VLAN, .opt = XTE_OPTION_VLAN,
.reg = XTE_RXC1_OFFSET, .reg = XTE_RXC1_OFFSET,
.m_or =XTE_RXC1_RXVLAN_MASK, .m_or = XTE_RXC1_RXVLAN_MASK,
}, },
/* Turn on FCS stripping on receive packets */ /* Turn on FCS stripping on receive packets */
{ {
.opt = XTE_OPTION_FCS_STRIP, .opt = XTE_OPTION_FCS_STRIP,
.reg = XTE_RXC1_OFFSET, .reg = XTE_RXC1_OFFSET,
.m_or =XTE_RXC1_RXFCS_MASK, .m_or = XTE_RXC1_RXFCS_MASK,
}, },
/* Turn on FCS insertion on transmit packets */ /* Turn on FCS insertion on transmit packets */
{ {
.opt = XTE_OPTION_FCS_INSERT, .opt = XTE_OPTION_FCS_INSERT,
.reg = XTE_TXC_OFFSET, .reg = XTE_TXC_OFFSET,
.m_or =XTE_TXC_TXFCS_MASK, .m_or = XTE_TXC_TXFCS_MASK,
}, },
/* Turn on length/type field checking on receive packets */ /* Turn on length/type field checking on receive packets */
{ {
.opt = XTE_OPTION_LENTYPE_ERR, .opt = XTE_OPTION_LENTYPE_ERR,
.reg = XTE_RXC1_OFFSET, .reg = XTE_RXC1_OFFSET,
.m_or =XTE_RXC1_RXLT_MASK, .m_or = XTE_RXC1_RXLT_MASK,
}, },
/* Turn on flow control */ /* Turn on flow control */
{ {
.opt = XTE_OPTION_FLOW_CONTROL, .opt = XTE_OPTION_FLOW_CONTROL,
.reg = XTE_FCC_OFFSET, .reg = XTE_FCC_OFFSET,
.m_or =XTE_FCC_RXFLO_MASK, .m_or = XTE_FCC_RXFLO_MASK,
}, },
/* Turn on flow control */ /* Turn on flow control */
{ {
.opt = XTE_OPTION_FLOW_CONTROL, .opt = XTE_OPTION_FLOW_CONTROL,
.reg = XTE_FCC_OFFSET, .reg = XTE_FCC_OFFSET,
.m_or =XTE_FCC_TXFLO_MASK, .m_or = XTE_FCC_TXFLO_MASK,
}, },
/* Turn on promiscuous frame filtering (all frames are received ) */ /* Turn on promiscuous frame filtering (all frames are received ) */
{ {
.opt = XTE_OPTION_PROMISC, .opt = XTE_OPTION_PROMISC,
.reg = XTE_AFM_OFFSET, .reg = XTE_AFM_OFFSET,
.m_or =XTE_AFM_EPPRM_MASK, .m_or = XTE_AFM_EPPRM_MASK,
}, },
/* Enable transmitter if not already enabled */ /* Enable transmitter if not already enabled */
{ {
.opt = XTE_OPTION_TXEN, .opt = XTE_OPTION_TXEN,
.reg = XTE_TXC_OFFSET, .reg = XTE_TXC_OFFSET,
.m_or =XTE_TXC_TXEN_MASK, .m_or = XTE_TXC_TXEN_MASK,
}, },
/* Enable receiver? */ /* Enable receiver? */
{ {
.opt = XTE_OPTION_RXEN, .opt = XTE_OPTION_RXEN,
.reg = XTE_RXC1_OFFSET, .reg = XTE_RXC1_OFFSET,
.m_or =XTE_RXC1_RXEN_MASK, .m_or = XTE_RXC1_RXEN_MASK,
}, },
{} {}
}; };
...@@ -641,7 +640,7 @@ static void temac_device_reset(struct net_device *ndev) ...@@ -641,7 +640,7 @@ static void temac_device_reset(struct net_device *ndev)
udelay(1); udelay(1);
if (--timeout == 0) { if (--timeout == 0) {
dev_err(&ndev->dev, dev_err(&ndev->dev,
"temac_device_reset RX reset timeout!!\n"); "%s RX reset timeout!!\n", __func__);
break; break;
} }
} }
...@@ -653,7 +652,7 @@ static void temac_device_reset(struct net_device *ndev) ...@@ -653,7 +652,7 @@ static void temac_device_reset(struct net_device *ndev)
udelay(1); udelay(1);
if (--timeout == 0) { if (--timeout == 0) {
dev_err(&ndev->dev, dev_err(&ndev->dev,
"temac_device_reset TX reset timeout!!\n"); "%s TX reset timeout!!\n", __func__);
break; break;
} }
} }
...@@ -672,7 +671,7 @@ static void temac_device_reset(struct net_device *ndev) ...@@ -672,7 +671,7 @@ static void temac_device_reset(struct net_device *ndev)
udelay(1); udelay(1);
if (--timeout == 0) { if (--timeout == 0) {
dev_err(&ndev->dev, dev_err(&ndev->dev,
"temac_device_reset DMA reset timeout!!\n"); "%s DMA reset timeout!!\n", __func__);
break; break;
} }
} }
...@@ -680,7 +679,7 @@ static void temac_device_reset(struct net_device *ndev) ...@@ -680,7 +679,7 @@ static void temac_device_reset(struct net_device *ndev)
if (temac_dma_bd_init(ndev)) { if (temac_dma_bd_init(ndev)) {
dev_err(&ndev->dev, dev_err(&ndev->dev,
"temac_device_reset descriptor allocation failed\n"); "%s descriptor allocation failed\n", __func__);
} }
spin_lock_irqsave(lp->indirect_lock, flags); spin_lock_irqsave(lp->indirect_lock, flags);
...@@ -691,7 +690,8 @@ static void temac_device_reset(struct net_device *ndev) ...@@ -691,7 +690,8 @@ static void temac_device_reset(struct net_device *ndev)
spin_unlock_irqrestore(lp->indirect_lock, flags); spin_unlock_irqrestore(lp->indirect_lock, flags);
/* Sync default options with HW /* Sync default options with HW
* but leave receiver and transmitter disabled. */ * but leave receiver and transmitter disabled.
*/
temac_setoptions(ndev, temac_setoptions(ndev,
lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN)); lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
...@@ -723,9 +723,15 @@ static void temac_adjust_link(struct net_device *ndev) ...@@ -723,9 +723,15 @@ static void temac_adjust_link(struct net_device *ndev)
mii_speed &= ~XTE_EMCFG_LINKSPD_MASK; mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
switch (phy->speed) { switch (phy->speed) {
case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break; case SPEED_1000:
case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break; mii_speed |= XTE_EMCFG_LINKSPD_1000;
case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break; break;
case SPEED_100:
mii_speed |= XTE_EMCFG_LINKSPD_100;
break;
case SPEED_10:
mii_speed |= XTE_EMCFG_LINKSPD_10;
break;
} }
/* Write new speed setting out to TEMAC */ /* Write new speed setting out to TEMAC */
...@@ -1007,7 +1013,6 @@ static void ll_temac_recv(struct net_device *ndev) ...@@ -1007,7 +1013,6 @@ static void ll_temac_recv(struct net_device *ndev)
if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) && if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
(skb->protocol == htons(ETH_P_IP)) && (skb->protocol == htons(ETH_P_IP)) &&
(skb->len > 64)) { (skb->len > 64)) {
/* Convert from device endianness (be32) to cpu /* Convert from device endianness (be32) to cpu
* endianness, and if necessary swap the bytes * endianness, and if necessary swap the bytes
* (back) for proper IP checksum byte order * (back) for proper IP checksum byte order
......
drivers/net/ethernet/xilinx/ll_temac_mdio.c
View file @ d294ad82
...@@ -29,7 +29,8 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg) ...@@ -29,7 +29,8 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
/* Write the PHY address to the MIIM Access Initiator register. /* Write the PHY address to the MIIM Access Initiator register.
* When the transfer completes, the PHY register value will appear * When the transfer completes, the PHY register value will appear
* in the LSW0 register */ * in the LSW0 register
*/
spin_lock_irqsave(lp->indirect_lock, flags); spin_lock_irqsave(lp->indirect_lock, flags);
temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg); temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET); rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET);
...@@ -88,7 +89,8 @@ int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev) ...@@ -88,7 +89,8 @@ int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev)
} }
/* Enable the MDIO bus by asserting the enable bit and writing /* Enable the MDIO bus by asserting the enable bit and writing
* in the clock config */ * in the clock config
*/
temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
bus = devm_mdiobus_alloc(&pdev->dev); bus = devm_mdiobus_alloc(&pdev->dev);
......
drivers/net/ethernet/xilinx/xilinx_axienet_main.c
View file @ d294ad82
...@@ -1375,7 +1375,7 @@ static int axienet_ethtools_get_regs_len(struct net_device *ndev) ...@@ -1375,7 +1375,7 @@ static int axienet_ethtools_get_regs_len(struct net_device *ndev)
static void axienet_ethtools_get_regs(struct net_device *ndev, static void axienet_ethtools_get_regs(struct net_device *ndev,
struct ethtool_regs *regs, void *ret) struct ethtool_regs *regs, void *ret)
{ {
u32 *data = (u32 *) ret; u32 *data = (u32 *)ret;
size_t len = sizeof(u32) * AXIENET_REGS_N; size_t len = sizeof(u32) * AXIENET_REGS_N;
struct axienet_local *lp = netdev_priv(ndev); struct axienet_local *lp = netdev_priv(ndev);
......
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
View file @ d294ad82
...@@ -126,7 +126,7 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, ...@@ -126,7 +126,7 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
return ret; return ret;
} }
axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val); axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val);
axienet_iow(lp, XAE_MDIO_MCR_OFFSET, axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) & (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) | XAE_MDIO_MCR_PHYAD_MASK) |
......
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