Commit d2fa7cc4 authored by David S. Miller's avatar David S. Miller

Merge branch 'cxgb4-next'

Hariprasad Shenai says:

====================
Add support to dump cim ibq, obq and qinfo, etc

This patch series adds support to dump cim_ibq, cim_obq, sge_qinfo, pm_stats
and clk debugfs entries.

The patches series is created against 'net-next' tree.
And includes patches on cxgb4 driver.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b8665c6c b58b6676
......@@ -1029,6 +1029,8 @@ int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter,
u64 *pbar2_qoffset,
unsigned int *pbar2_qid);
unsigned int qtimer_val(const struct adapter *adap,
const struct sge_rspq *q);
int t4_init_sge_params(struct adapter *adapter);
int t4_init_tp_params(struct adapter *adap);
int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
......@@ -1052,6 +1054,12 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
u64 *parity);
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
u64 *parity);
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
size_t n);
int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
size_t n);
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp);
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
......
......@@ -2500,7 +2500,7 @@ static int closest_thres(const struct sge *s, int thres)
/*
* Return a queue's interrupt hold-off time in us. 0 means no timer.
*/
static unsigned int qtimer_val(const struct adapter *adap,
unsigned int qtimer_val(const struct adapter *adap,
const struct sge_rspq *q)
{
unsigned int idx = q->intr_params >> 1;
......
......@@ -2511,6 +2511,60 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
}
}
/**
* t4_pmtx_get_stats - returns the HW stats from PMTX
* @adap: the adapter
* @cnt: where to store the count statistics
* @cycles: where to store the cycle statistics
*
* Returns performance statistics from PMTX.
*/
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
{
int i;
u32 data[2];
for (i = 0; i < PM_NSTATS; i++) {
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
if (is_t4(adap->params.chip)) {
cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
} else {
t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
PM_TX_DBG_DATA_A, data, 2,
PM_TX_DBG_STAT_MSB_A);
cycles[i] = (((u64)data[0] << 32) | data[1]);
}
}
}
/**
* t4_pmrx_get_stats - returns the HW stats from PMRX
* @adap: the adapter
* @cnt: where to store the count statistics
* @cycles: where to store the cycle statistics
*
* Returns performance statistics from PMRX.
*/
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
{
int i;
u32 data[2];
for (i = 0; i < PM_NSTATS; i++) {
t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
if (is_t4(adap->params.chip)) {
cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
} else {
t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
PM_RX_DBG_DATA_A, data, 2,
PM_RX_DBG_STAT_MSB_A);
cycles[i] = (((u64)data[0] << 32) | data[1]);
}
}
}
/**
* get_mps_bg_map - return the buffer groups associated with a port
* @adap: the adapter
......@@ -4525,6 +4579,91 @@ void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
}
}
/**
* t4_read_cim_ibq - read the contents of a CIM inbound queue
* @adap: the adapter
* @qid: the queue index
* @data: where to store the queue contents
* @n: capacity of @data in 32-bit words
*
* Reads the contents of the selected CIM queue starting at address 0 up
* to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
* error and the number of 32-bit words actually read on success.
*/
int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
{
int i, err, attempts;
unsigned int addr;
const unsigned int nwords = CIM_IBQ_SIZE * 4;
if (qid > 5 || (n & 3))
return -EINVAL;
addr = qid * nwords;
if (n > nwords)
n = nwords;
/* It might take 3-10ms before the IBQ debug read access is allowed.
* Wait for 1 Sec with a delay of 1 usec.
*/
attempts = 1000000;
for (i = 0; i < n; i++, addr++) {
t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
IBQDBGEN_F);
err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
attempts, 1);
if (err)
return err;
*data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
}
t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
return i;
}
/**
* t4_read_cim_obq - read the contents of a CIM outbound queue
* @adap: the adapter
* @qid: the queue index
* @data: where to store the queue contents
* @n: capacity of @data in 32-bit words
*
* Reads the contents of the selected CIM queue starting at address 0 up
* to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
* error and the number of 32-bit words actually read on success.
*/
int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
{
int i, err;
unsigned int addr, v, nwords;
int cim_num_obq = is_t4(adap->params.chip) ?
CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
if ((qid > (cim_num_obq - 1)) || (n & 3))
return -EINVAL;
t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
QUENUMSELECT_V(qid));
v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
nwords = CIMQSIZE_G(v) * 64; /* same */
if (n > nwords)
n = nwords;
for (i = 0; i < n; i++, addr++) {
t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
OBQDBGEN_F);
err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
2, 1);
if (err)
return err;
*data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
}
t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
return i;
}
/**
* t4_cim_read - read a block from CIM internal address space
* @adap: the adapter
......
......@@ -48,6 +48,7 @@ enum {
NMTUS = 16, /* size of MTU table */
NCCTRL_WIN = 32, /* # of congestion control windows */
L2T_SIZE = 4096, /* # of L2T entries */
PM_NSTATS = 5, /* # of PM stats */
MBOX_LEN = 64, /* mailbox size in bytes */
TRACE_LEN = 112, /* length of trace data and mask */
FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
......@@ -60,6 +61,8 @@ enum {
CIM_NUM_OBQ = 6, /* # of CIM OBQs */
CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
};
enum {
......
......@@ -1203,12 +1203,35 @@
#define TIMERRESOLUTION_M 0xffU
#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
#define TIMESTAMPRESOLUTION_S 8
#define TIMESTAMPRESOLUTION_M 0xffU
#define TIMESTAMPRESOLUTION_G(x) \
(((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
#define DELAYEDACKRESOLUTION_S 0
#define DELAYEDACKRESOLUTION_M 0xffU
#define DELAYEDACKRESOLUTION_G(x) \
(((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
#define TP_SHIFT_CNT_A 0x7dc0
#define TP_RXT_MIN_A 0x7d98
#define TP_RXT_MAX_A 0x7d9c
#define TP_PERS_MIN_A 0x7da0
#define TP_PERS_MAX_A 0x7da4
#define TP_KEEP_IDLE_A 0x7da8
#define TP_KEEP_INTVL_A 0x7dac
#define TP_INIT_SRTT_A 0x7db0
#define TP_DACK_TIMER_A 0x7db4
#define TP_FINWAIT2_TIMER_A 0x7db8
#define INITSRTT_S 0
#define INITSRTT_M 0xffffU
#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
#define PERSMAX_S 0
#define PERSMAX_M 0x3fffffffU
#define PERSMAX_V(x) ((x) << PERSMAX_S)
#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
#define SYNSHIFTMAX_S 24
#define SYNSHIFTMAX_M 0xffU
......@@ -1380,6 +1403,12 @@
#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
#define PM_RX_INT_CAUSE_A 0x8fdc
#define PM_RX_STAT_CONFIG_A 0x8fc8
#define PM_RX_STAT_COUNT_A 0x8fcc
#define PM_RX_STAT_LSB_A 0x8fd0
#define PM_RX_DBG_CTRL_A 0x8fd0
#define PM_RX_DBG_DATA_A 0x8fd4
#define PM_RX_DBG_STAT_MSB_A 0x10013
#define PMRX_FRAMING_ERROR_F 0x003ffff0U
......@@ -1404,6 +1433,12 @@
#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
#define PM_TX_INT_CAUSE_A 0x8ffc
#define PM_TX_STAT_CONFIG_A 0x8fe8
#define PM_TX_STAT_COUNT_A 0x8fec
#define PM_TX_STAT_LSB_A 0x8ff0
#define PM_TX_DBG_CTRL_A 0x8ff0
#define PM_TX_DBG_DATA_A 0x8ff4
#define PM_TX_DBG_STAT_MSB_A 0x1001a
#define PCMD_LEN_OVFL0_S 31
#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
......@@ -2538,6 +2573,39 @@
#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
#define HOSTWRITE_F HOSTWRITE_V(1U)
#define CIM_IBQ_DBG_CFG_A 0x7b60
#define IBQDBGADDR_S 16
#define IBQDBGADDR_M 0xfffU
#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
#define IBQDBGBUSY_S 1
#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
#define IBQDBGEN_S 0
#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
#define IBQDBGEN_F IBQDBGEN_V(1U)
#define CIM_OBQ_DBG_CFG_A 0x7b64
#define OBQDBGADDR_S 16
#define OBQDBGADDR_M 0xfffU
#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
#define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
#define OBQDBGBUSY_S 1
#define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
#define OBQDBGBUSY_F OBQDBGBUSY_V(1U)
#define OBQDBGEN_S 0
#define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
#define OBQDBGEN_F OBQDBGEN_V(1U)
#define CIM_IBQ_DBG_DATA_A 0x7b68
#define CIM_OBQ_DBG_DATA_A 0x7b6c
#define UPDBGLARDEN_S 1
#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment