PPC32: Add support for the IBM405LP-based "Beech" board

arch/ppc/platforms/4xx/Kconfig

@@ -13,6 +13,9 @@ choice
 config ASH
 	bool "Ash"
 
+config BEECH
+	bool "Beech"
+
 config CEDAR
 	bool "Cedar"
 
@@ -75,7 +78,7 @@ config IBM405_ERR51
 
 config IBM_OCP
 	bool
-	depends on ASH || CEDAR || CPCI405 || EP405 || REDWOOD_4 || REDWOOD_5 || WALNUT
+	depends on ASH || BEECH || CEDAR || CPCI405 || EP405 || REDWOOD_4 || REDWOOD_5 || WALNUT
 	default y
 
 config NP405L
@@ -110,7 +113,7 @@ config EMBEDDEDBOOT
 
 config IBM_OPENBIOS
 	bool
-	depends on ASH || CEDAR || REDWOOD_4 || REDWOOD_5 || WALNUT
+	depends on ASH || BEECH || CEDAR || REDWOOD_4 || REDWOOD_5 || WALNUT
 	default y
 
 config 405_DMA

arch/ppc/platforms/4xx/Makefile

@@ -2,6 +2,7 @@
 # Makefile for the PowerPC 4xx linux kernel.
 
 obj-$(CONFIG_ASH)		+= ash.o
+obj-$(CONFIG_BEECH)		+= beech.o 
 obj-$(CONFIG_CEDAR)		+= cedar.o
 obj-$(CONFIG_CPCI405)		+= cpci405.o
 obj-$(CONFIG_EP405)		+= ep405.o

arch/ppc/platforms/4xx/beech.c

+/*
+ * arch/ppc/platforms/beech.c  Platform setup for the IBM Beech board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (C) 2002, International Business Machines Corporation
+ * All Rights Reserved
+ *
+ * Bishop Brock
+ * IBM Research, Austin Center for Low-Power Computing
+ * bcbrock@us.ibm.com
+ * March, 2002
+ *
+ */
+
+#include <linux/blk.h>
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/rtc.h>
+#include <linux/string.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+
+static void beech_ebc_setup(void);
+static void beech_fpga_setup(void);
+
+/* 
+   Beech board physical memory map:
+
+   Main Memory (Initialized by the BIOS)
+   =======================================================================
+
+   SDRAM (64 MB)     0x00000000 - 0x04000000
+
+   OPB Space: (Mapped virtual = physical in ppc4xx_setup.c)
+   =======================================================================
+
+   UART0               	      0xEF600300
+   UART1               	      0xEF600400
+   IIC                 	      0xEF600500
+   OPB Arbiter         	      0xEF600600
+   GPIO Controller     	      0xEF600700
+   CODEC Interface            0xEF600900
+   Touch Panel Controller     0xEF600A00
+   DES Controller             0xEF600B00
+
+   
+   EBC Space: (Mapped virtual = physical in ppc4xx_map_io(); EBC setup
+               for PCMCIA left to 4xx_pccf)
+   Space             EBC Bank    Physical Addresses  EBC Base Address
+   =========================================================================
+
+   PCMCIA (32 MB)        x       F0000000 - F1FFFFFF  F0000000 
+
+   Expansion             2       F8000000 - F8FFFFFF  F8000000
+   Linux Flash (16 MB)           F9000000 - F9FFFFFF
+
+   NVRAM (32 KB)         1       FFE00000 - FFE07FFF  FFE00000
+   
+
+   Ethernet(I/O)	 1	 FFE20300 - FFE2030F  FFE00000
+           (MEM)	 	 FFE40000 - FFE40FFF
+
+   FPGA_REG_4            1       FFE60000 - FFE60000  FFE00000
+   FPGA_REG_0            1       FFE80000 - FFE80000  FFE00000
+   FPGA_REG_1            1       FFEA0000 - FFEA0000  FFE00000
+   FPGA_REG_2            1       FFEC0000 - FFEC0000  FFE00000
+   FPGA_REG_3            1       FFEE0000 - FFEE0000  FFE00000
+
+   SRAM (512 KB)         0       FFF00000 - FFF7FFFF  FFF00000
+
+   Boot Flash  (512 KB)  0       FFF80000 - FFFFFFFF  FFF00000
+
+   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+   NB: On Beech 1, address ranges for Bank 2 were reversed
+
+*/
+
+void __init
+beech_setup_arch(void)
+{
+	ppc4xx_setup_arch();
+
+	TODC_INIT(TODC_TYPE_DCR146818, NULL, NULL, NULL, 8);
+
+	/* Set up Beech FPGA. */
+
+	beech_fpga_setup();
+}
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
+{
+	ppc4xx_init(r3, r4, r5, r6, r7);
+
+	ppc_md.setup_arch = beech_setup_arch;
+
+#ifdef CONFIG_PPC_RTC
+	ppc_md.time_init = todc_time_init;
+	ppc_md.set_rtc_time = todc_set_rtc_time;
+	ppc_md.get_rtc_time = todc_get_rtc_time;
+	ppc_md.nvram_read_val = todc_dcr146818_read_val;
+	ppc_md.nvram_write_val = todc_dcr146818_write_val;
+#endif
+	/* Disable the LCD controller, which may have been left on by the
+	   BIOS.  Then do initialization of the EBC. */
+
+	mtdcri(DCRN_LCD0, DER, 0);
+	beech_ebc_setup();
+}
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ + Non-standard board support follows
+ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+
+/****************************************************************************
+ * EBC Setup
+ ****************************************************************************/
+
+/* The EBC is set up for Beech.  This may simply replicate the setup already
+   done by the IBM BIOS for Beech (possibly with some address map changes), or
+   may be the first initialization if the board is booting from another BIOS.
+   Virtually all that is required to boot Linux on Beech is that the BIOS
+   enable the memory controller, load a Linux image from flash, and run it.
+
+   For optimal dynamic frequency scaling the EBC settings will also vary as the
+   frequency varies.
+*/
+
+static void __init
+beech_ebc_setup(void)
+{
+	ebc0_bnap_t ap;
+	ebc0_bncr_t cr;
+
+	/* Set EBC bank 0 for the SRAM and boot flash.
+
+	   Access parameters assume 120ns AMD flash @ 66.66 MHz maximum bus
+	   speed = 8 cycle access with 2 turnaround cycles (30 ns).
+
+	   These parameters will work for the SRAM as well, which is a 70 ns
+	   part. 
+
+	   NB: IBM BIOS sets this bank to burst, however bursting will never
+	   happen in Linux because this region is mapped non-cacheable and
+	   guarded, so it is set non-burst here. */
+
+	cr.reg = (BEECH_BANK0_PADDR & 0xfff00000) |
+	    (mfdcri(DCRN_EBC0, BnCR(0)) & EBC0_BnCR_MASK);
+	cr.fields.bs = BEECH_BANK0_EBC_SIZE;
+	cr.fields.bu = EBC0_BnCR_BU_RW;
+	cr.fields.bw = EBC0_BnCR_BW_16;
+	mtdcri(DCRN_EBC0, BnCR(0), cr.reg);
+
+	ap.reg = mfdcri(DCRN_EBC0, BnAP(0)) & EBC0_BnAP_MASK;
+	ap.fields.twt = 8;
+	ap.fields.th = 2;
+	mtdcri(DCRN_EBC0, BnAP(0), ap.reg);
+
+	/*  EBC bank 1 is used for many purposes: NVRAM, Ethernet, and FPGA
+	   registers. This is a 1 MB, 16-bit bank. The access parameters must
+	   handle the worst case of all of the devices. 
+
+	   The Ethernet chip needs 20 ns setup of the addresses to the I/O
+	   write signal (generated from the chip select), a minimum 150 ns
+	   cycle, and 30 ns of turnaround.  These settings will work for the
+	   other devices as well.
+	 */
+
+	cr.reg = (BEECH_BANK1_PADDR & 0xfff00000) |
+	    (mfdcri(DCRN_EBC0, BnCR(1)) & EBC0_BnCR_MASK);
+	cr.fields.bs = BEECH_BANK1_EBC_SIZE;
+	cr.fields.bu = EBC0_BnCR_BU_RW;
+	cr.fields.bw = EBC0_BnCR_BW_16;
+	mtdcri(DCRN_EBC0, BnCR(1), cr.reg);
+
+	ap.reg = mfdcri(DCRN_EBC0, BnAP(1)) & EBC0_BnAP_MASK;
+	ap.fields.twt = 10;
+	ap.fields.csn = 2;
+	ap.fields.th = 2;
+	mtdcri(DCRN_EBC0, BnAP(1), ap.reg);
+
+	/* Set EBC bank 2 for the big (Linux) flash.  There is 16 MB of flash,
+	   but the CPLD decodes a 32 MB region.
+
+	   Access parameters assume 90ns AMD flash @ 66.66 MHz maximum bus
+	   speed = 6 cycle access with 2 turnaround cycles (30 ns).
+
+	   NB: IBM BIOS sets this bank to burst, however bursting will never
+	   happen in Linux because this region is mapped non-cacheable and
+	   guarded, so it is set non-burst here. */
+
+	cr.reg = (BEECH_BANK2_PADDR & 0xfff00000) |
+	    (mfdcri(DCRN_EBC0, BnCR(2)) & EBC0_BnCR_MASK);
+	cr.fields.bs = BEECH_BANK2_EBC_SIZE;
+	cr.fields.bu = EBC0_BnCR_BU_RW;
+	cr.fields.bw = EBC0_BnCR_BW_8;
+	mtdcri(DCRN_EBC0, BnCR(2), cr.reg);
+
+	ap.reg = mfdcri(DCRN_EBC0, BnAP(2)) & EBC0_BnAP_MASK;
+	ap.fields.twt = 6;
+	ap.fields.th = 2;
+	mtdcri(DCRN_EBC0, BnAP(2), ap.reg);
+}
+
+/****************************************************************************
+ * FPGA Setup
+ ****************************************************************************/
+
+/* The Beech FPGA is set up for Linux. */
+
+static void __init
+beech_fpga_setup(void)
+{
+	volatile u8 *fpga_reg_2;
+
+	fpga_reg_2 = (volatile u8 *)
+	    ioremap(BEECH_FPGA_REG_2_PADDR, BEECH_FPGA_REG_2_SIZE);
+
+	/* Set RTS/CTS mode for UART 1 */
+
+	*fpga_reg_2 |= FPGA_REG_2_DEFAULT_UART1_N;
+}
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */

arch/ppc/platforms/4xx/beech.h

+/*
+ * include/asm-ppc/platforms/beech.h   Platform definitions for the IBM Beech
+ *                                     board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (C) 2002, International Business Machines Corporation
+ * All Rights Reserved.
+ *
+ * Bishop Brock
+ * IBM Research, Austin Center for Low-Power Computing
+ * bcbrock@us.ibm.com
+ * March, 2002
+ * 
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_BEECH_H__
+#define __ASM_BEECH_H__
+
+#include <platforms/4xx/ibm405lp.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Data structure defining board information maintained by the standard boot
+ * ROM on the IBM Beech board. An effort has been made to
+ * keep the field names consistent with the 8xx 'bd_t' board info
+ * structures.  
+ */
+
+typedef struct board_info {
+	unsigned char bi_s_version[4];	/* Version of this structure */
+	unsigned long bi_tbfreq;	/* Frequency of SysTmrClk */
+	unsigned char bi_r_version[30];	/* Version of the IBM ROM */
+	unsigned int bi_memsize;	/* DRAM installed, in bytes */
+	unsigned long sysclock_period;	/* SysClk period in ns */
+	unsigned long sys_speed;	/* SysCLk frequency in Hz */
+	unsigned long bi_intfreq;	/* Processor speed, in Hz */
+	unsigned long vco_speed;	/* PLL VCO speed, in Hz */
+	unsigned long bi_busfreq;	/* PLB Bus speed, in Hz */
+	unsigned long opb_speed;	/* OPB Bus speed, in Hz */
+	unsigned long ebc_speed;	/* EBC Bus speed, in Hz */
+} bd_t;
+
+/* See beech.c for a concise diagram of the Beech physical memory map. */
+
+#define PPC4xx_ONB_IO_PADDR    ((uint)0xef600000)
+#define PPC4xx_ONB_IO_VADDR    PPC4xx_ONB_IO_PADDR
+#define PPC4xx_ONB_IO_SIZE     ((uint)4*1024)
+
+/* EBC Bank 0 controls the boot flash and SRAM */
+
+#define BEECH_BANK0_PADDR      ((uint)0xfff00000)
+#define BEECH_BANK0_EBC_SIZE   EBC0_BnCR_BS_1MB
+
+#define BEECH_SRAM_PADDR		BEECH_BANK0_PADDR
+#define BEECH_SRAM_SIZE			((uint)(512 * 1024))
+
+#define BEECH_BOOTFLASH_PADDR		(BEECH_BANK0_PADDR + (512 * 1024))
+#define BEECH_BOOTFLASH_SIZE		((uint)(512 * 1024))
+
+/* EBC bank 1 controls the NVRAM, Ethernet and CPLD registers. The different
+   areas are mapped in as small an area as possible to help catch any kernel
+   addressing errors.
+
+   NVRAM is improperly connected on Beech Pass 1.  Only every other location is
+   accessible.  This is a 32 KB NVRAM.
+
+   The Ethernet chip maps 13 address lines. We only map the "I/O" space used by
+   the current driver.
+
+   The FPGA "registers" are decoded on 128 KB boundarys. Each is mapped in a
+   separate page. */
+
+#define BEECH_BANK1_PADDR       ((uint)0xffe00000)
+#define BEECH_BANK1_EBC_SIZE    EBC0_BnCR_BS_1MB
+
+#define BEECH_NVRAM_PADDR		BEECH_BANK1_PADDR
+#define BEECH_NVRAM_SIZE		((uint) (32 * 1024))
+
+#define BEECH_ETHERNET_PADDR		(BEECH_BANK1_PADDR + 0x00020000)
+#define BEECH_ETHERNET_SIZE		((uint) (8 * 1024))
+
+#define BEECH_FPGA_REG_0_PADDR		(BEECH_BANK1_PADDR + 0x00080000)
+#define BEECH_FPGA_REG_0_SIZE		PAGE_SIZE
+
+#define BEECH_FPGA_REG_1_PADDR		(BEECH_BANK1_PADDR + 0x000A0000)
+#define BEECH_FPGA_REG_1_SIZE		PAGE_SIZE
+
+#define BEECH_FPGA_REG_2_PADDR		(BEECH_BANK1_PADDR + 0x000C0000)
+#define BEECH_FPGA_REG_2_SIZE		PAGE_SIZE
+
+#define BEECH_FPGA_REG_3_PADDR		(BEECH_BANK1_PADDR + 0x000E0000)
+#define BEECH_FPGA_REG_3_SIZE		PAGE_SIZE
+
+#define BEECH_FPGA_REG_4_PADDR		(BEECH_BANK1_PADDR + 0x00060000)
+#define BEECH_FPGA_REG_4_SIZE		PAGE_SIZE
+
+/* FPGA Register Bits (From IBM BIOS) [ May not be valid for Beech Pass 1 ]*/
+
+#define FPGA_REG_0_FLASH_N		0x01
+#define FPGA_REG_0_FLASH_ONBD_N		0x02
+#define FPGA_REG_0_HITA_TOSH_N		0x04	/* New in Pass 2 */
+#define FPGA_REG_0_STAT_OC		0x20
+#define FPGA_REG_0_AC_SOURCE_SEL_N	0x40
+#define FPGA_REG_0_AC_ACTIVE_N		0x80
+
+#define FPGA_REG_1_USB_ACTIVE		0x01	/* New in Pass 2 */
+#define FPGA_REG_1_CLK_VARIABLE		0x02
+#define FPGA_REG_1_CLK_TEST		0x04
+#define FPGA_REG_1_CLK_SS		0x08
+#define FPGA_REG_1_EXT_IRQ_N		0x10
+#define FPGA_REG_1_SMI_MODE_N		0x20
+#define FPGA_REG_1_BATT_LOW_N		0x40
+#define FPGA_REG_1_PCMCIA_PWR_FAULT_N	0x80
+
+#define FPGA_REG_2_DEFAULT_UART1_N	0x01
+#define FPGA_REG_2_EN_1_8V_PLL_N	0x02
+#define FPGA_REG_2_PC_BUF_EN_N		0x08
+#define FPGA_REG_2_CODEC_RESET_N	0x10	/* New in Pass 2 */
+#define FPGA_REG_2_TP_JSTICK_N		0x20	/* New in Pass 2 */
+
+#define FPGA_REG_3_GAS_GAUGE_IO		0x01
+
+#define FPGA_REG_4_SDRAM_CLK3_ENAB	0x01
+#define FPGA_REG_4_SDRAM_CLK2_ENAB	0x02
+#define FPGA_REG_4_SDRAM_CLK1_ENAB	0x04
+#define FPGA_REG_4_SDRAM_CLK0_ENAB	0x08
+#define FPGA_REG_4_PCMCIA_5V		0x10	/* New in Pass 2 */
+#define FPGA_REG_4_IRQ3			0x20	/* New in Pass 2 */
+
+/* EBC Bank 2 contains the 16 MB "Linux" flash. The FPGA decodes a 32 MB
+   bank. The lower 16 MB are available for expansion devices.  The upper 16 MB
+   are used for the "Linux" flash.
+
+   Partitioning information is for the benefit of the MTD driver.  See 
+   drivers/mtd/maps/ibm4xx.c. We currently allocate the lower 1 MB for a
+   kernel, and the other 15 MB for a filesystem.
+
+*/
+
+/* Bank 2 mappings changed between Beech Pass 1 and Pass 2 */
+
+#ifdef CONFIG_BEECH_PASS1
+#define BEECH_BIGFLASH_OFFSET 0
+#else
+#define BEECH_BIGFLASH_OFFSET (16 * 1024 * 1024)
+#endif
+
+#define BEECH_BANK2_PADDR      ((uint)0xf8000000)
+#define BEECH_BANK2_EBC_SIZE   EBC0_BnCR_BS_32MB
+
+#define BEECH_BIGFLASH_PADDR		(BEECH_BANK2_PADDR + BEECH_BIGFLASH_OFFSET)
+#define BEECH_BIGFLASH_SIZE		(16 * 1024 * 1024)
+
+#define BEECH_KERNEL_OFFSET    0
+#define BEECH_KERNEL_SIZE      (1 * 1024 * 1024)
+
+#define BEECH_FREE_AREA_OFFSET BEECH_KERNEL_SIZE
+#define BEECH_FREE_AREA_SIZE   (BEECH_BIGFLASH_SIZE - BEECH_KERNEL_SIZE)
+
+/* The PCMCIA controller driver 4xx_pccf.c is responsible for the EBC setup of
+   PCMCIA.  Externally, EBC bank selects 3..7 take on PCMCIA functions when
+   PCMCIA is enabled. */
+
+#define BEECH_PCMCIA_PADDR		((uint)0xf0000000)
+#define BEECH_PCMCIA_SIZE		((uint)(32 * 1024 * 1024))
+
+/* We do not currently support the internal clock mode for the UART.  This
+   limits the minimum OPB frequency to just over 2X the UART oscillator
+   frequency. At OPB frequencies less than this the serial port will not
+   function due to the way that SerClk is sampled. */
+
+#define PPC4xx_SERCLK_FREQ		11059200
+#define BASE_BAUD			(PPC4xx_SERCLK_FREQ / 16)
+
+#define PPC4xx_MACHINE_NAME		"IBM 405LP Beech"
+
+/****************************************************************************
+ * Non-standard board support follows
+ ****************************************************************************/
+
+extern int beech_sram_free(void *p);
+extern int ibm405lp_set_pixclk(unsigned pixclk_low, unsigned pixclk_high);
+extern void *beech_sram_alloc(size_t size);
+
+#endif				/* !__ASSEMBLY__ */
+#endif				/* __ASM_BEECH_H__ */
+#endif				/* __KERNEL__ */