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Commit d42b1c47 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
     TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
     FPGA bindings to DT schema format

   - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
     controller

   - Add MediaTek MT8365 UART and SYSIRQ bindings

   - Add Arm Cortex-A78C and X1C core compatibles

   - Add vendor prefix for Novatek

   - Remove bindings for stih415, sti416, stid127 platforms

   - Drop uneeded quotes in schema files. This is preparation for
     yamllint checking quoting for us.

   - Add missing (unevaluated|additional)Properties constraints on child
     node schemas

   - Clean-up schema comments formatting

   - Fix I2C and SPI node bus names in schema examples

   - Clean-up some display compatibles schema syntax

   - Fix incorrect references to lvds.yaml

   - Gather all cache controller bindings in a common directory

  DT core:

   - Convert unittest to new void .remove platform device hook

   - kerneldoc fixes for DT address of_pci_range_to_resource/
     of_address_to_resource functions"

* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
  dt-bindings: rng: Drop unneeded quotes
  dt-bindings: arm/soc: mediatek: Drop unneeded quotes
  dt-bindings: soc: qcom: Drop unneeded quotes
  dt-bindings: i2c: samsung: Fix 'deprecated' value
  dt-bindings: display: Fix lvds.yaml references
  dt-bindings: display: simplify compatibles syntax
  dt-bindings: display: mediatek: simplify compatibles syntax
  dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
  dt-bindings: timer: Drop unneeded quotes
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
  dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
  dt-bindings: reset: remove stih415/stih416 reset
  dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
  dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
  dt-bindings: iommu: Convert QCOM IOMMU to YAML
  dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
  dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
  of: address: Reshuffle to remove forward declarations
  of: address: Fix documented return value of of_pci_range_to_resource()
  of: address: Document return value of of_address_to_resource()
  ...
parents 6df969b7 66ae0535
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Documentation/devicetree/bindings/.yamllint
View file @ d42b1c47
......@@ -19,7 +19,7 @@ rules:
colons: {max-spaces-before: 0, max-spaces-after: 1}
commas: {min-spaces-after: 1, max-spaces-after: 1}
comments:
require-starting-space: false
require-starting-space: true
min-spaces-from-content: 1
comments-indentation: disable
document-start:
......
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
View file @ d42b1c47
......@@ -144,6 +144,7 @@ patternProperties:
it is stricter and always has two compatibles.
type: object
$ref: '/schemas/simple-bus.yaml'
unevaluatedProperties: false
properties:
compatible:
......
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
View file @ d42b1c47
......@@ -30,6 +30,7 @@ properties:
clocks:
type: object
additionalProperties: false
properties:
compatible:
......@@ -47,6 +48,7 @@ properties:
reset:
type: object
additionalProperties: false
properties:
compatible:
......@@ -63,6 +65,7 @@ properties:
pwm:
type: object
additionalProperties: false
properties:
compatible:
......@@ -76,8 +79,6 @@ properties:
- compatible
- "#pwm-cells"
additionalProperties: false
required:
- compatible
- mboxes
......
Documentation/devicetree/bindings/arm/cpus.yaml
View file @ d42b1c47
......@@ -141,6 +141,7 @@ properties:
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
- arm,cortex-a78c
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-a715
......@@ -153,6 +154,7 @@ properties:
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,neoverse-e1
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Infrastructure System Configuration Controller
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek mmsys controller
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE Mirror Controller for MT7622
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE WED Controller for MT7986
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8186
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8186
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8192
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8192
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8195
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8195
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Peripheral Configuration Controller
......
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View file @ d42b1c47
......@@ -234,6 +234,7 @@ properties:
patternProperties:
"^[a-z0-9]+$":
type: object
additionalProperties: false
properties:
clocks:
......@@ -252,6 +253,9 @@ properties:
for controlling a power-gate.
See ../reset/reset.txt for more details.
power-domains:
maxItems: 1
'#power-domain-cells':
const: 0
description: Must be 0.
......
Documentation/devicetree/bindings/ata/ahci-common.yaml
View file @ d42b1c47
......@@ -59,7 +59,7 @@ properties:
const: sata-phy
hba-cap:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA generic platform capabilities like Staggered
Spin-up or Mechanical Presence Switch support. It can be used to
......@@ -67,7 +67,7 @@ properties:
in case if the system firmware hasn't done it.
ports-implemented:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mask that indicates which ports the HBA supports. Useful if PI is not
programmed by the BIOS, which is true for some embedded SoC's.
......@@ -110,7 +110,7 @@ $defs:
description: Power regulator for SATA port target device
hba-port-cap:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA port-specific platform capabilities like Hot
plugging, eSATA, FIS-based Switching, etc (see AHCI specification
......
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Serial-ATA Interface
......
Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml
View file @ d42b1c47
......@@ -72,7 +72,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
View file @ d42b1c47
......@@ -46,6 +46,7 @@ patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1
......
Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml
View file @ d42b1c47
......@@ -45,6 +45,7 @@ properties:
patternProperties:
"^.*@[0-9a-fA-F]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1
......
Documentation/devicetree/bindings/bus/palmbus.yaml
View file @ d42b1c47
......@@ -36,6 +36,7 @@ patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1
......
Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml → Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
View file @ d42b1c47
......@@ -2,7 +2,7 @@
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 L2-cache Control Block
......
Documentation/devicetree/bindings/arm/l2c2x0.yaml → Documentation/devicetree/bindings/cache/l2c2x0.yaml
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM L2 Cache Controller
......
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml → Documentation/devicetree/bindings/cache/qcom,llcc.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Last Level Cache Controller
......
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml → Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
View file @ d42b1c47
......@@ -2,7 +2,7 @@
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller
......
Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml → Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier outer cache controller
......
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
View file @ d42b1c47
......@@ -41,7 +41,7 @@ additionalProperties: false
examples:
- |+
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml
View file @ d42b1c47
......@@ -20,7 +20,7 @@ additionalProperties: false
examples:
- |
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml
View file @ d42b1c47
......@@ -81,11 +81,11 @@ properties:
maxItems: 1
lock-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset to the unlocking register for the oscillator
vco-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset to the VCO register for the oscillator
deprecated: true
......
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek AP Mixedsys Controller
......
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Top Clock Generator Controller
......
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View file @ d42b1c47
......@@ -45,14 +45,14 @@ required:
additionalProperties: false
examples:
#Example 1 - A53 PLL found on MSM8916 devices
# Example 1 - A53 PLL found on MSM8916 devices
- |
a53pll: clock@b016000 {
compatible = "qcom,msm8916-a53pll";
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
#Example 2 - A53 PLL found on IPQ6018 devices
# Example 2 - A53 PLL found on IPQ6018 devices
- |
a53pll_ipq: clock-controller@b116000 {
compatible = "qcom,ipq6018-a53pll";
......
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Clock Pulse Generator / Module Standby and Software Reset
......
Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car USB 2.0 clock selector
......
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
......
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
View file @ d42b1c47
......@@ -202,7 +202,7 @@ allOf:
- description: External RTC clock (32768 Hz)
- description: CMU_HSI bus clock (from CMU_TOP)
- description: SD card clock (from CMU_TOP)
- description: "USB 2.0 DRD clock (from CMU_TOP)"
- description: USB 2.0 DRD clock (from CMU_TOP)
clock-names:
items:
......
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SC9863A Clock Control Unit
......
Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UMS512 Soc clock controller
......
Documentation/devicetree/bindings/clock/ti,lmk04832.yaml
View file @ d42b1c47
......@@ -160,7 +160,7 @@ examples:
};
};
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard
......
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0-mon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Secure Non-Volatile Storage (SNVS)
maintainers:
- '"Horia Geantă" <horia.geanta@nxp.com>'
- Pankaj Gupta <pankaj.gupta@nxp.com>
- Gaurav Jain <gaurav.jain@nxp.com>
description:
Node defines address range and the associated interrupt for the SNVS function.
This function monitors security state information & reports security
violations. This also included rtc, system power off and ON/OFF key.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v4.0-mon
- const: syscon
- const: simple-mfd
- items:
- const: fsl,sec-v5.0-mon
- const: fsl,sec-v4.0-mon
- items:
- enum:
- fsl,sec-v5.3-mon
- fsl,sec-v5.4-mon
- const: fsl,sec-v5.0-mon
- const: fsl,sec-v4.0-mon
reg:
maxItems: 1
interrupts:
maxItems: 2
snvs-rtc-lp:
type: object
additionalProperties: false
description:
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
properties:
compatible:
const: fsl,sec-v4.0-mon-rtc-lp
clocks:
maxItems: 1
clock-names:
const: snvs-rtc
interrupts:
# VFxxx has only one. What is the 2nd one?
minItems: 1
maxItems: 2
regmap:
description: Parent node containing registers
$ref: /schemas/types.yaml#/definitions/phandle
offset:
description: LP register offset
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x34
required:
- compatible
- interrupts
- regmap
snvs-powerkey:
type: object
additionalProperties: false
description:
The snvs-pwrkey is designed to enable POWER key function which controlled
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
system if pressed after system suspend.
properties:
compatible:
const: fsl,sec-v4.0-pwrkey
clocks:
maxItems: 1
clock-names:
const: snvs-pwrkey
interrupts:
maxItems: 1
regmap:
description: Parent node containing registers
$ref: /schemas/types.yaml#/definitions/phandle
wakeup-source: true
linux,keycode:
default: 116
required:
- compatible
- interrupts
- regmap
snvs-lpgpr:
$ref: /schemas/nvmem/snvs-lpgpr.yaml#
snvs-poweroff:
description:
The SNVS could drive signal to PMIC to turn off system power by setting
SNVS_LP LPCR register.
$ref: /schemas/power/reset/syscon-poweroff.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx7d-clock.h>
sec_mon: sec-mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x314000 0x1000>;
snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&sec_mon>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&sec_mon>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-pwrkey";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <116>; /* KEY_POWER */
wakeup-source;
};
};
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SEC 4
maintainers:
- '"Horia Geantă" <horia.geanta@nxp.com>'
- Pankaj Gupta <pankaj.gupta@nxp.com>
- Gaurav Jain <gaurav.jain@nxp.com>
description: |
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).
SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).
High Speed Data Path Configuration:
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080. The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.
Job Ring Data Path Configuration:
Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4
- const: fsl,sec-v5.0
- const: fsl,sec-v4.0
- items:
- enum:
- fsl,imx6ul-caam
- fsl,sec-v5.0
- const: fsl,sec-v4.0
- const: fsl,sec-v4.0
reg:
maxItems: 1
ranges:
maxItems: 1
'#address-cells':
enum: [1, 2]
'#size-cells':
enum: [1, 2]
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
items:
enum: [mem, aclk, ipg, emi_slow]
dma-coherent: true
interrupts:
maxItems: 1
fsl,sec-era:
description: Defines the 'ERA' of the SEC device.
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
'^jr@[0-9a-f]+$':
type: object
additionalProperties: false
description:
Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
peripheral bus for purposes of processing cryptographic descriptors. The
specified address range can be made visible to one (or more) cores. The
interrupt defined for this node is controlled within the address range of
this node.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4-job-ring
- const: fsl,sec-v5.0-job-ring
- const: fsl,sec-v4.0-job-ring
- items:
- const: fsl,sec-v5.0-job-ring
- const: fsl,sec-v4.0-job-ring
- const: fsl,sec-v4.0-job-ring
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,liodn:
description:
Specifies the LIODN to be used in conjunction with the ppid-to-liodn
table that specifies the PPID to LIODN mapping. Needed if the PAMU is
used. Value is a 12 bit value where value is a LIODN ID for this JR.
This property is normally set by boot firmware.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0xfff
'^rtic@[0-9a-f]+$':
type: object
additionalProperties: false
description:
Run Time Integrity Check (RTIC) Node. Defines a register space that
contains up to 5 sets of addresses and their lengths (sizes) that will be
checked at run time. After an initial hash result is calculated, these
addresses are checked by HW to monitor any change. If any memory is
modified, a Security Violation is triggered (see SNVS definition).
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4-rtic
- const: fsl,sec-v5.0-rtic
- const: fsl,sec-v4.0-rtic
- const: fsl,sec-v4.0-rtic
reg:
maxItems: 1
ranges:
maxItems: 1
interrupts:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
patternProperties:
'^rtic-[a-z]@[0-9a-f]+$':
type: object
additionalProperties: false
description:
Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
memory regions that are used to perform run-time integrity check of
memory areas that should not modified. The node defines a register
that contains the memory address & length (combined) and a second
register that contains the hash result in big endian format.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4-rtic-memory
- const: fsl,sec-v5.0-rtic-memory
- const: fsl,sec-v4.0-rtic-memory
- const: fsl,sec-v4.0-rtic-memory
reg:
items:
- description: RTIC memory address
- description: RTIC hash result
fsl,liodn:
description:
Specifies the LIODN to be used in conjunction with the
ppid-to-liodn table that specifies the PPID to LIODN mapping.
Needed if the PAMU is used. Value is a 12 bit value where value
is a LIODN ID for this JR. This property is normally set by boot
firmware.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0xfff
fsl,rtic-region:
description:
Specifies the HW address (36 bit address) for this region
followed by the length of the HW partition to be checked;
the address is represented as a 64 bit quantity followed
by a 32 bit length.
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- ranges
additionalProperties: false
examples:
- |
crypto@300000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2>;
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2>;
};
jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2>;
};
jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2>;
};
jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2>;
};
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20>, <0x100 0x80>;
};
rtic-b@20 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20>, <0x200 0x80>;
};
rtic-c@40 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20>, <0x300 0x80>;
};
rtic-d@60 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20>, <0x500 0x80>;
};
};
};
...
Documentation/devicetree/bindings/crypto/fsl-sec4.txt deleted 100644 → 0
View file @ 6df969b7
=====================================================================
SEC 4 Device Tree Binding
Copyright (C) 2008-2011 Freescale Semiconductor Inc.
CONTENTS
-Overview
-SEC 4 Node
-Job Ring Node
-Run Time Integrity Check (RTIC) Node
-Run Time Integrity Check (RTIC) Memory Node
-Secure Non-Volatile Storage (SNVS) Node
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
-Full Example
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).
=====================================================================
Overview
DESCRIPTION
SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).
High Speed Data Path Configuration:
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080. The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.
Job Ring Data Path Configuration:
Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
=====================================================================
SEC 4 Node
Description
Node defines the base address of the SEC 4 block.
This block specifies the address range of all global
configuration registers for the SEC 4 block. It
also receives interrupts from the Run Time Integrity Check
(RTIC) function within the SEC 4 block.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0"
- fsl,sec-era
Usage: optional
Value type: <u32>
Definition: A standard property. Define the 'ERA' of the SEC
device.
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical
address and length of the SEC4 configuration registers.
registers
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SEC 4.0 register space (-SNVS not included). A
triplet that includes the child address, parent address, &
length.
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
- clocks
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <prop_encoded-array>
Definition: A list of phandle and clock specifier pairs describing
the clocks required for enabling and disabling SEC 4.0.
- clock-names
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <string>
Definition: A list of clock name strings in the same order as the
clocks property.
Note: All other standard properties (see the Devicetree Specification)
are allowed but are optional.
EXAMPLE
iMX6QDL/SX requires four clocks
crypto@300000 {
compatible = "fsl,sec-v4.0";
fsl,sec-era = <2>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
<&clks IMX6QDL_CLK_CAAM_ACLK>,
<&clks IMX6QDL_CLK_CAAM_IPG>,
<&clks IMX6QDL_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
};
iMX6UL does only require three clocks
crypto: crypto@2140000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2140000 0x3c000>;
ranges = <0 0x2140000 0x3c000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
<&clks IMX6UL_CLK_CAAM_ACLK>,
<&clks IMX6UL_CLK_CAAM_IPG>;
clock-names = "mem", "aclk", "ipg";
};
=====================================================================
Job Ring (JR) Node
Child of the crypto node defines data processing interface to SEC 4
across the peripheral bus for purposes of processing
cryptographic descriptors. The specified address
range can be made visible to one (or more) cores.
The interrupt defined for this node is controlled within
the address range of this node.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-job-ring"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies a two JR parameters: an offset from
the parent physical address and the length the JR registers.
- fsl,liodn
Usage: optional-but-recommended
Value type: <prop-encoded-array>
Definition:
Specifies the LIODN to be used in conjunction with
the ppid-to-liodn table that specifies the PPID to LIODN mapping.
Needed if the PAMU is used. Value is a 12 bit value
where value is a LIODN ID for this JR. This property is
normally set by boot firmware.
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
EXAMPLE
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
fsl,liodn = <0x081>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
=====================================================================
Run Time Integrity Check (RTIC) Node
Child node of the crypto node. Defines a register space that
contains up to 5 sets of addresses and their lengths (sizes) that
will be checked at run time. After an initial hash result is
calculated, these addresses are checked by HW to monitor any
change. If any memory is modified, a Security Violation is
triggered (see SNVS definition).
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-rtic".
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes. Must
have a value of 1.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes. Must have a value of 1.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies a two parameters:
an offset from the parent physical address and the length
the SEC4 registers.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SEC 4 register space (-SNVS not included). A
triplet that includes the child address, parent address, &
length.
EXAMPLE
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
};
=====================================================================
Run Time Integrity Check (RTIC) Memory Node
A child node that defines individual RTIC memory regions that are used to
perform run-time integrity check of memory areas that should not modified.
The node defines a register that contains the memory address &
length (combined) and a second register that contains the hash result
in big endian format.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-rtic-memory".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies two parameters:
an offset from the parent physical address and the length:
1. The location of the RTIC memory address & length registers.
2. The location RTIC hash result.
- fsl,rtic-region
Usage: optional-but-recommended
Value type: <prop-encoded-array>
Definition:
Specifies the HW address (36 bit address) for this region
followed by the length of the HW partition to be checked;
the address is represented as a 64 bit quantity followed
by a 32 bit length.
- fsl,liodn
Usage: optional-but-recommended
Value type: <prop-encoded-array>
Definition:
Specifies the LIODN to be used in conjunction with
the ppid-to-liodn table that specifies the PPID to LIODN
mapping. Needed if the PAMU is used. Value is a 12 bit value
where value is a LIODN ID for this RTIC memory region. This
property is normally set by boot firmware.
EXAMPLE
rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
fsl,liodn = <0x03c>;
fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
};
=====================================================================
Secure Non-Volatile Storage (SNVS) Node
Node defines address range and the associated
interrupt for the SNVS function. This function
monitors security state information & reports
security violations. This also included rtc,
system power off and ON/OFF key.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical
address and length of the SEC4 configuration
registers.
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes. Must
have a value of 1.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes. Must have a value of 1.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SNVS register space. A triplet that includes
the child address, parent address, & length.
- interrupts
Usage: optional
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
EXAMPLE
sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon";
reg = <0x314000 0x1000>;
ranges = <0 0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2>;
};
=====================================================================
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
A SNVS child node that defines SNVS LP RTC.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
- regmap
Usage: required
Value type: <phandle>
Definition: this is phandle to the register map node.
- offset
Usage: option
value type: <u32>
Definition: LP register offset. default it is 0x34.
- clocks
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <prop_encoded-array>
Definition: a clock specifier describing the clock required for
enabling and disabling SNVS LP RTC.
- clock-names
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <string>
Definition: clock name string should be "snvs-rtc".
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
=====================================================================
System ON/OFF key driver
The snvs-pwrkey is designed to enable POWER key function which controlled
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
system if pressed after system suspend.
- compatible:
Usage: required
Value type: <string>
Definition: Mush include "fsl,sec-v4.0-pwrkey".
- interrupts:
Usage: required
Value type: <prop_encoded-array>
Definition: The SNVS ON/OFF interrupt number to the CPU(s).
- linux,keycode:
Usage: option
Value type: <int>
Definition: Keycode to emit, KEY_POWER by default.
- wakeup-source:
Usage: option
Value type: <boo>
Definition: Button can wake-up the system.
- regmap:
Usage: required:
Value type: <phandle>
Definition: this is phandle to the register map node.
EXAMPLE:
snvs-pwrkey@020cc000 {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <0 4 0x4>
linux,keycode = <116>; /* KEY_POWER */
wakeup-source;
};
=====================================================================
FULL EXAMPLE
crypto: crypto@300000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <89 2>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <90 2>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <91 2>;
};
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
ranges = <0 0x314000 0x1000>;
sec_mon_rtc_lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&sec_mon>;
interrupts = <0 4 0x4>;
linux,keycode = <116>; /* KEY_POWER */
wakeup-source;
};
};
=====================================================================
Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml
View file @ d42b1c47
......@@ -26,8 +26,8 @@ properties:
dmas:
items:
- description: TX DMA Channel
- description: RX DMA Channel #1
- description: RX DMA Channel #2
- description: 'RX DMA Channel #1'
- description: 'RX DMA Channel #2'
dma-names:
items:
......
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
View file @ d42b1c47
......@@ -16,8 +16,7 @@ description: |
properties:
compatible:
items:
- const: analogix,anx7625
const: analogix,anx7625
reg:
maxItems: 1
......@@ -134,7 +133,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/anx6345.yaml
View file @ d42b1c47
......@@ -61,7 +61,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
View file @ d42b1c47
......@@ -67,7 +67,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c4 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/nxp,ptn3460.yaml
View file @ d42b1c47
......@@ -71,7 +71,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/parade,ps8622.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/parade,ps8622.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Parade PS8622/PS8625 DisplayPort to LVDS Converter
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
properties:
compatible:
enum:
- parade,ps8622
- parade,ps8625
reg:
maxItems: 1
lane-count:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
description: Number of DP lanes to use.
use-external-pwm:
type: boolean
description: Backlight will be controlled by an external PWM.
reset-gpios:
maxItems: 1
description: GPIO connected to RST_ pin.
sleep-gpios:
maxItems: 1
description: GPIO connected to PD_ pin.
vdd12-supply: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for LVDS output.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for DisplayPort input.
required:
- port@0
- port@1
required:
- compatible
- reg
- reset-gpios
- sleep-gpios
- ports
allOf:
- if:
properties:
compatible:
const: parade,ps8622
then:
properties:
lane-count:
const: 1
else:
properties:
lane-count:
const: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
lane-count = <2>;
use-external-pwm;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
port@1 {
reg = <1>;
bridge_in: endpoint {
remote-endpoint = <&dp_out>;
};
};
};
};
};
Documentation/devicetree/bindings/display/bridge/ps8622.txt deleted 100644 → 0
View file @ 6df969b7
ps8622-bridge bindings
Required properties:
- compatible: "parade,ps8622" or "parade,ps8625"
- reg: first i2c address of the bridge
- sleep-gpios: OF device-tree gpio specification for PD_ pin.
- reset-gpios: OF device-tree gpio specification for RST_ pin.
Optional properties:
- lane-count: number of DP lanes to use
- use-external-pwm: backlight will be controlled by an external PWM
- video interfaces: Device node can contain video interface port
nodes for panel according to [1].
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
lvds-bridge@48 {
compatible = "parade,ps8622";
reg = <0x48>;
sleep-gpios = <&gpc3 6 1 0 0>;
reset-gpios = <&gpc3 1 1 0 0>;
lane-count = <1>;
ports {
port@0 {
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
Documentation/devicetree/bindings/display/bridge/ps8640.yaml
View file @ d42b1c47
......@@ -73,7 +73,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/sil,sii9234.yaml
View file @ d42b1c47
......@@ -71,7 +71,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
View file @ d42b1c47
......@@ -83,7 +83,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
View file @ d42b1c47
......@@ -90,7 +90,7 @@ properties:
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
......@@ -106,7 +106,6 @@ properties:
description:
If you have 1 logical lane the bridge supports routing
to either port 0 or port 1. Port 0 is suggested.
See ../../media/video-interface.txt for details.
- minItems: 2
maxItems: 2
......@@ -118,7 +117,6 @@ properties:
description:
If you have 2 logical lanes the bridge supports
reordering but only on physical ports 0 and 1.
See ../../media/video-interface.txt for details.
- minItems: 4
maxItems: 4
......@@ -132,7 +130,6 @@ properties:
description:
If you have 4 logical lanes the bridge supports
reordering in any way.
See ../../media/video-interface.txt for details.
lane-polarities:
minItems: 1
......@@ -141,7 +138,6 @@ properties:
enum:
- 0
- 1
description: See ../../media/video-interface.txt
dependencies:
lane-polarities: [data-lanes]
......
Documentation/devicetree/bindings/display/bridge/toshiba,tc358762.yaml
View file @ d42b1c47
......@@ -51,7 +51,7 @@ additionalProperties: false
examples:
- |
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/bridge/toshiba,tc358764.txt deleted 100644 → 0
View file @ 6df969b7
TC358764 MIPI-DSI to LVDS panel bridge
Required properties:
- compatible: "toshiba,tc358764"
- reg: the virtual channel number of a DSI peripheral
- vddc-supply: core voltage supply, 1.2V
- vddio-supply: I/O voltage supply, 1.8V or 3.3V
- vddlvds-supply: LVDS1/2 voltage supply, 3.3V
- reset-gpios: a GPIO spec for the reset pin
The device node can contain following 'port' child nodes,
according to the OF graph bindings defined in [1]:
0: DSI Input, not required, if the bridge is DSI controlled
1: LVDS Output, mandatory
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
bridge@0 {
reg = <0>;
compatible = "toshiba,tc358764";
vddc-supply = <&vcc_1v2_reg>;
vddio-supply = <&vcc_1v8_reg>;
vddlvds-supply = <&vcc_3v3_reg>;
reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_ep: endpoint {
remote-endpoint = <&panel_ep>;
};
};
};
Documentation/devicetree/bindings/display/bridge/toshiba,tc358764.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358764.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba TC358764 MIPI-DSI to LVDS bridge
maintainers:
- Andrzej Hajda <andrzej.hajda@intel.com>
properties:
compatible:
const: toshiba,tc358764
reg:
description: Virtual channel number of a DSI peripheral
maxItems: 1
reset-gpios:
maxItems: 1
vddc-supply:
description: Core voltage supply, 1.2V
vddio-supply:
description: I/O voltage supply, 1.8V or 3.3V
vddlvds-supply:
description: LVDS1/2 voltage supply, 3.3V
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for MIPI DSI input, if the bridge DSI controlled
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for LVDS output (panel or connector).
required:
- port@1
required:
- compatible
- reg
- reset-gpios
- vddc-supply
- vddio-supply
- vddlvds-supply
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
bridge@0 {
compatible = "toshiba,tc358764";
reg = <0>;
reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
vddc-supply = <&vcc_1v2_reg>;
vddio-supply = <&vcc_1v8_reg>;
vddlvds-supply = <&vcc_3v3_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_ep: endpoint {
remote-endpoint = <&panel_ep>;
};
};
};
};
};
Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml
View file @ d42b1c47
......@@ -87,7 +87,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
View file @ d42b1c47
......@@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8183-disp-ccorr
- items:
- const: mediatek,mt8192-disp-ccorr
- enum:
- mediatek,mt8183-disp-ccorr
- mediatek,mt8192-disp-ccorr
- items:
- enum:
- mediatek,mt8186-disp-ccorr
......
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
View file @ d42b1c47
......@@ -22,12 +22,10 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-disp-color
- items:
- const: mediatek,mt8167-disp-color
- items:
- const: mediatek,mt8173-disp-color
- enum:
- mediatek,mt2701-disp-color
- mediatek,mt8167-disp-color
- mediatek,mt8173-disp-color
- items:
- enum:
- mediatek,mt7623-disp-color
......
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
View file @ d42b1c47
......@@ -22,8 +22,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8183-disp-dither
- enum:
- mediatek,mt8183-disp-dither
- items:
- enum:
- mediatek,mt8186-disp-dither
......
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
View file @ d42b1c47
......@@ -20,8 +20,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8195-disp-dsc
- enum:
- mediatek,mt8195-disp-dsc
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
View file @ d42b1c47
......@@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-gamma
- items:
- const: mediatek,mt8183-disp-gamma
- enum:
- mediatek,mt8173-disp-gamma
- mediatek,mt8183-disp-gamma
- items:
- enum:
- mediatek,mt8186-disp-gamma
......
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
View file @ d42b1c47
......@@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8195-disp-merge
- enum:
- mediatek,mt8173-disp-merge
- mediatek,mt8195-disp-merge
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
View file @ d42b1c47
......@@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2712-disp-od
- items:
- const: mediatek,mt8173-disp-od
- enum:
- mediatek,mt2712-disp-od
- mediatek,mt8173-disp-od
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
View file @ d42b1c47
......@@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8183-disp-ovl-2l
- items:
- const: mediatek,mt8192-disp-ovl-2l
- enum:
- mediatek,mt8183-disp-ovl-2l
- mediatek,mt8192-disp-ovl-2l
- items:
- enum:
- mediatek,mt8186-disp-ovl-2l
......
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
View file @ d42b1c47
......@@ -21,14 +21,11 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-disp-ovl
- items:
- const: mediatek,mt8173-disp-ovl
- items:
- const: mediatek,mt8183-disp-ovl
- items:
- const: mediatek,mt8192-disp-ovl
- enum:
- mediatek,mt2701-disp-ovl
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
- items:
- enum:
- mediatek,mt7623-disp-ovl
......
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
View file @ d42b1c47
......@@ -21,8 +21,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8192-disp-postmask
- enum:
- mediatek,mt8192-disp-postmask
- items:
- enum:
- mediatek,mt8186-disp-postmask
......
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
View file @ d42b1c47
......@@ -23,14 +23,11 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-disp-rdma
- items:
- const: mediatek,mt8173-disp-rdma
- items:
- const: mediatek,mt8183-disp-rdma
- items:
- const: mediatek,mt8195-disp-rdma
- enum:
- mediatek,mt2701-disp-rdma
- mediatek,mt8173-disp-rdma
- mediatek,mt8183-disp-rdma
- mediatek,mt8195-disp-rdma
- items:
- enum:
- mediatek,mt8188-disp-rdma
......
Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
View file @ d42b1c47
......@@ -21,8 +21,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-split
- enum:
- mediatek,mt8173-disp-split
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
View file @ d42b1c47
......@@ -22,8 +22,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-ufoe
- enum:
- mediatek,mt8173-disp-ufoe
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
View file @ d42b1c47
......@@ -21,8 +21,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-wdma
- enum:
- mediatek,mt8173-disp-wdma
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
View file @ d42b1c47
......@@ -61,7 +61,7 @@ properties:
- const: lut
- const: tbu
- const: tbu_rt
#MSM8996 has additional iommu clock
# MSM8996 has additional iommu clock
- items:
- const: iface
- const: bus
......
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
View file @ d42b1c47
......@@ -101,6 +101,7 @@ required:
patternProperties:
"^display-controller@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
contains:
......@@ -108,6 +109,7 @@ patternProperties:
"^dsi@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
contains:
......@@ -115,6 +117,7 @@ patternProperties:
"^phy@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
enum:
......@@ -132,6 +135,7 @@ patternProperties:
"^hdmi-tx@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
enum:
......
Documentation/devicetree/bindings/display/panel/advantech,idk-1110wr.yaml
View file @ d42b1c47
......@@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:
......
Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml
View file @ d42b1c47
......@@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:
......
Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml
View file @ d42b1c47
......@@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:
......
Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml
View file @ d42b1c47
......@@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:
......
Documentation/devicetree/bindings/display/panel/nec,nl8048hl11.yaml
View file @ d42b1c47
......@@ -41,7 +41,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
View file @ d42b1c47
......@@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:
......
Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml
View file @ d42b1c47
......@@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:
......
Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml
View file @ d42b1c47
......@@ -34,8 +34,8 @@ properties:
- items:
- const: sharp,lq101r1sx03
- const: sharp,lq101r1sx01
- items:
- const: sharp,lq101r1sx01
- enum:
- sharp,lq101r1sx01
reg: true
power-supply: true
......
Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
View file @ d42b1c47
......@@ -14,20 +14,18 @@ properties:
compatible:
oneOf:
# Deprecated compatible strings
- items:
- enum:
- solomon,ssd1305fb-i2c
- solomon,ssd1306fb-i2c
- solomon,ssd1307fb-i2c
- solomon,ssd1309fb-i2c
- enum:
- solomon,ssd1305fb-i2c
- solomon,ssd1306fb-i2c
- solomon,ssd1307fb-i2c
- solomon,ssd1309fb-i2c
deprecated: true
- items:
- enum:
- sinowealth,sh1106
- solomon,ssd1305
- solomon,ssd1306
- solomon,ssd1307
- solomon,ssd1309
- enum:
- sinowealth,sh1106
- solomon,ssd1305
- solomon,ssd1306
- solomon,ssd1307
- solomon,ssd1309
reg:
maxItems: 1
......@@ -226,7 +224,7 @@ unevaluatedProperties: false
examples:
- |
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -239,7 +237,7 @@ examples:
ssd1306_i2c: oled@3d {
compatible = "solomon,ssd1306";
reg = <0x3c>;
reg = <0x3d>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
solomon,com-lrremap;
......
Documentation/devicetree/bindings/eeprom/at25.yaml
View file @ d42b1c47
......@@ -122,7 +122,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/example-schema.yaml
View file @ d42b1c47
......@@ -176,6 +176,8 @@ properties:
description: Child nodes are just another property from a json-schema
perspective.
type: object # DT nodes are json objects
# Child nodes also need additionalProperties or unevaluatedProperties
additionalProperties: false
properties:
vendor,a-child-node-property:
description: Child node properties have all the same schema
......
Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.yaml
View file @ d42b1c47
......@@ -34,7 +34,7 @@ additionalProperties: false
examples:
- |
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
cros-ec@0 {
......
Documentation/devicetree/bindings/extcon/extcon-usbc-tusb320.yaml
View file @ d42b1c47
......@@ -30,7 +30,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
tusb320@61 {
......
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt deleted 100644 → 0
View file @ 6df969b7
Xilinx LogiCORE Partial Reconfig Decoupler Softcore
The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
decouplers / fpga bridges.
The controller can decouple/disable the bridges which prevents signal
changes from passing through the bridge. The controller can also
couple / enable the bridges which allows traffic to pass through the
bridge normally.
Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
from passing through the bridge. The controller safely handles AXI4MM
and AXI4-Lite interfaces on a Reconfigurable Partition when it is
undergoing dynamic reconfiguration, preventing the system deadlock
that can occur if AXI transactions are interrupted by DFX
The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.
Required properties:
- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
"xlnx,pr-decoupler" or
"xlnx,dfx-axi-shutdown-manager-1.00" followed by
"xlnx,dfx-axi-shutdown-manager"
- regs : base address and size for decoupler module
- clocks : input clock to IP
- clock-names : should contain "aclk"
See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
Partial Reconfig Decoupler:
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00",
"xlnx-pr-decoupler";
regs = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
bridge-enable = <0>;
};
Dynamic Function eXchange AXI shutdown manager:
fpga-bridge@100000450 {
compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
"xlnx,dfx-axi-shutdown-manager";
regs = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
bridge-enable = <0>;
};
Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt deleted 100644 → 0
View file @ 6df969b7
Xilinx Slave Serial SPI FPGA Manager
Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
bitstream over what is referred to as "slave serial" interface.
The slave serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
See:
- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
Required properties:
- compatible: should contain "xlnx,fpga-slave-serial"
- reg: spi chip select of the FPGA
- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
- done-gpios: config status pin (referred to as DONE in the manual)
Optional properties:
- init-b-gpios: initialization status and configuration error pin
(referred to as INIT_B in the manual)
Example for full FPGA configuration:
fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr_spi>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
spi1: spi@10680 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
spi-max-frequency = <60000000>;
spi-cpha;
reg = <0>;
prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-serial.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Slave Serial SPI FPGA
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
over what is referred to as slave serial interface.The slave serial link is
not technically SPI, and might require extra circuits in order to play nicely
with other SPI slaves on the same bus.
Datasheets:
https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
enum:
- xlnx,fpga-slave-serial
spi-cpha: true
spi-max-frequency:
maximum: 60000000
reg:
maxItems: 1
prog_b-gpios:
description:
config pin (referred to as PROGRAM_B in the manual)
maxItems: 1
done-gpios:
description:
config status pin (referred to as DONE in the manual)
maxItems: 1
init-b-gpios:
description:
initialization status and configuration error pin
(referred to as INIT_B in the manual)
maxItems: 1
required:
- compatible
- reg
- prog_b-gpios
- done-gpios
- init-b-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
spi-max-frequency = <60000000>;
spi-cpha;
reg = <0>;
prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
...
Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
decouplers/fpga bridges. The controller can decouple/disable the bridges
which prevents signal changes from passing through the bridge. The controller
can also couple / enable the bridges which allows traffic to pass through the
bridge normally.
Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
eXchange AXI shutdown manager prevents AXI traffic from passing through the
bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
Reconfigurable Partition when it is undergoing dynamic reconfiguration,
preventing the system deadlock that can occur if AXI transactions are
interrupted by DFX.
Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
common binding part and usage.
properties:
compatible:
oneOf:
- items:
- const: xlnx,pr-decoupler-1.00
- const: xlnx,pr-decoupler
- items:
- const: xlnx,dfx-axi-shutdown-manager-1.00
- const: xlnx,dfx-axi-shutdown-manager
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: aclk
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00", "xlnx,pr-decoupler";
reg = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
};
...
Documentation/devicetree/bindings/gpio/gpio-pca9570.yaml
View file @ d42b1c47
......@@ -34,7 +34,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
View file @ d42b1c47
......@@ -151,7 +151,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -177,7 +177,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -203,7 +203,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c2 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -221,7 +221,7 @@ examples:
};
- |
i2c3 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
View file @ d42b1c47
......@@ -35,6 +35,7 @@ properties:
patternProperties:
"^.*-pins?$":
$ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
pins:
......
Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml
View file @ d42b1c47
......@@ -32,6 +32,7 @@ properties:
patternProperties:
"^channel@([0-1])$":
type: object
additionalProperties: false
description: |
Represents the two supplies to be monitored.
......
Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
View file @ d42b1c47
......@@ -60,7 +60,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
i2c0: i2c-bus@40 {
i2c@40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-i2c-bus";
......
Documentation/devicetree/bindings/i2c/google,cros-ec-i2c-tunnel.yaml
View file @ d42b1c47
......@@ -39,7 +39,7 @@ unevaluatedProperties: false
examples:
- |
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
View file @ d42b1c47
......@@ -37,7 +37,7 @@ properties:
for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are
permanently wired to the respective client.
This property is deprecated. Use "pinctrl-0" and "pinctrl-names" instead.
deprecated: yes
deprecated: true
interrupts:
maxItems: 1
......
Documentation/devicetree/bindings/input/adc-joystick.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019-2020 Artur Rojek
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/adc-joystick.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/input/adc-joystick.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADC attached joystick
......
Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml
View file @ d42b1c47
......@@ -57,7 +57,7 @@ if:
contains:
const: google,cros-ec-keyb
then:
$ref: "/schemas/input/matrix-keymap.yaml#"
$ref: /schemas/input/matrix-keymap.yaml#
required:
- keypad,num-rows
- keypad,num-columns
......
Documentation/devicetree/bindings/input/imx-keypad.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- Liu Ying <gnuiyl@gmail.com>
allOf:
- $ref: "/schemas/input/matrix-keymap.yaml#"
- $ref: /schemas/input/matrix-keymap.yaml#
description: |
The KPP is designed to interface with a keypad matrix with 2-point contact
......
Documentation/devicetree/bindings/input/matrix-keymap.yaml
View file @ d42b1c47
......@@ -21,7 +21,7 @@ description: |
properties:
linux,keymap:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
An array of packed 1-cell entries containing the equivalent of row,
column and linux key-code. The 32-bit big endian cell is packed as:
......
Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- Mattijs Korpershoek <mkorpershoek@baylibre.com>
allOf:
- $ref: "/schemas/input/matrix-keymap.yaml#"
- $ref: /schemas/input/matrix-keymap.yaml#
description: |
Mediatek's Keypad controller is used to interface a SoC with a matrix-type
......
Documentation/devicetree/bindings/input/microchip,cap11xx.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/microchip,cap11xx.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/input/microchip,cap11xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip CAP11xx based capacitive touch sensors
......
Documentation/devicetree/bindings/input/pwm-vibrator.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/pwm-vibrator.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PWM vibrator
......
Documentation/devicetree/bindings/input/regulator-haptic.yaml
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/regulator-haptic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/input/regulator-haptic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Regulator Haptic
......
Documentation/devicetree/bindings/input/snvs-pwrkey.txt deleted 100644 → 0
View file @ 6df969b7
See Documentation/devicetree/bindings/crypto/fsl-sec4.txt
Documentation/devicetree/bindings/input/touchscreen/elan,elants_i2c.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/touchscreen/elan,elants_i2c.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/input/touchscreen/elan,elants_i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Elantech I2C Touchscreen
......
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
View file @ d42b1c47
......@@ -66,6 +66,7 @@ properties:
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
additionalProperties: false
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
......
Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
View file @ d42b1c47
......@@ -32,7 +32,7 @@ properties:
The first cell is the input IRQ number, between 0 and 2, while the second
cell is the trigger type as defined in interrupt.txt in this directory.
'interrupts':
interrupts:
description: |
Contains the GIC SPI IRQs mapped to the external interrupt lines.
They shall be specified sequentially from output 0 to 2.
......@@ -44,7 +44,7 @@ required:
- reg
- interrupt-controller
- '#interrupt-cells'
- 'interrupts'
- interrupts
additionalProperties: false
......
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
View file @ d42b1c47
......@@ -133,12 +133,14 @@ properties:
ppi-partitions:
type: object
additionalProperties: false
description:
PPI affinity can be expressed as a single "ppi-partitions" node,
containing a set of sub-nodes.
patternProperties:
"^interrupt-partition-[0-9]+$":
type: object
additionalProperties: false
properties:
affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
......
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
View file @ d42b1c47
......@@ -133,8 +133,8 @@ properties:
- items: # for "arm,cortex-a9-gic"
- const: PERIPHCLK
- const: PERIPHCLKEN
- const: clk # for "arm,gic-400" and "nvidia,tegra210"
- const: gclk #for "arm,pl390"
- const: clk # for "arm,gic-400" and "nvidia,tegra210"
- const: gclk # for "arm,pl390"
power-domains:
maxItems: 1
......
Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
View file @ d42b1c47
......@@ -48,13 +48,13 @@ properties:
const: 1
fsl,channel:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: |
u32 value representing the output channel that all input IRQs should be
steered into.
fsl,num-irqs:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: |
u32 value representing the number of input interrupts of this channel,
should be multiple of 32 input interrupts and up to 512 interrupts.
......
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
......
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
......
Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx XScale Networking Processors Interrupt Controller
......
Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-3 HyperTransport Interrupt Controller
......
Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-3 HyperTransport Interrupt Vector Controller
......
Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson Local I/O Interrupt Controller
......@@ -54,7 +54,7 @@ properties:
'#interrupt-cells':
const: 2
'loongson,parent_int_map':
loongson,parent_int_map:
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
......@@ -71,7 +71,7 @@ required:
- interrupts
- interrupt-controller
- '#interrupt-cells'
- 'loongson,parent_int_map'
- loongson,parent_int_map
unevaluatedProperties: false
......
Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson PCH MSI Controller
......@@ -25,7 +25,7 @@ properties:
description:
u32 value of the base of parent HyperTransport vector allocated
to PCH MSI.
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
......@@ -33,7 +33,7 @@ properties:
description:
u32 value of the number of parent HyperTransport vectors allocated
to PCH MSI.
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 256
......@@ -46,7 +46,7 @@ required:
- loongson,msi-base-vec
- loongson,msi-num-vecs
additionalProperties: true #fixme
additionalProperties: true # fixme
examples:
- |
......
Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson PCH PIC Controller
......@@ -25,7 +25,7 @@ properties:
description:
u32 value of the base of parent HyperTransport vector allocated
to PCH PIC.
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 192
......
Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
View file @ d42b1c47
......@@ -25,6 +25,7 @@ Required properties:
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
"mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
......
Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml
View file @ d42b1c47
......@@ -53,8 +53,8 @@ allOf:
maxItems: 1
reg-names:
items:
- const: 'mux status'
- const: 'mux mask'
- const: mux status
- const: mux mask
required:
- interrupts
else:
......
Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microsemi Ocelot SoC ICPU Interrupt Controller
......
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
View file @ d42b1c47
......@@ -26,6 +26,8 @@ properties:
compatible:
items:
- enum:
- qcom,qdu1000-pdc
- qcom,sa8775p-pdc
- qcom,sc7180-pdc
- qcom,sc7280-pdc
- qcom,sc8280xp-pdc
......@@ -53,7 +55,7 @@ properties:
qcom,pdc-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 1
maxItems: 32 # no hard limit
maxItems: 128 # no hard limit
items:
items:
- description: starting PDC port
......
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View file @ d42b1c47
......@@ -91,7 +91,7 @@ properties:
riscv,cpu-intc node, which has a riscv node as parent.
riscv,ndev:
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies how many external interrupts are supported by this controller.
......
Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
View file @ d42b1c47
......@@ -6,11 +6,7 @@ and PL310 L2 Cache IRQs are controlled using System Configuration registers.
This driver is used to unmask them prior to use.
Required properties:
- compatible : Should be set to one of:
"st,stih415-irq-syscfg"
"st,stih416-irq-syscfg"
"st,stih407-irq-syscfg"
"st,stid127-irq-syscfg"
- compatible : Should be "st,stih407-irq-syscfg"
- st,syscfg : Phandle to Cortex-A9 IRQ system config registers
- st,irq-device : Array of IRQs to enable - should be 2 in length
- st,fiq-device : Array of FIQs to enable - should be 2 in length
......@@ -25,11 +21,10 @@ Optional properties:
Example:
irq-syscfg {
compatible = "st,stih416-irq-syscfg";
compatible = "st,stih407-irq-syscfg";
st,syscfg = <&syscfg_cpu>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
<ST_IRQ_SYSCFG_DISABLED>;
st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>;
};
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
View file @ d42b1c47
......@@ -85,6 +85,9 @@ properties:
description:
Array of phandles to DMA controllers where the unmapped events originate.
power-domains:
maxItems: 1
required:
- compatible
- reg
......
Documentation/devicetree/bindings/iommu/qcom,iommu.txt deleted 100644 → 0
View file @ 6df969b7
* QCOM IOMMU v1 Implementation
Qualcomm "B" family devices which are not compatible with arm-smmu have
a similar looking IOMMU but without access to the global register space,
and optionally requiring additional configuration to route context irqs
to non-secure vs secure interrupt line.
** Required properties:
- compatible : Should be one of:
"qcom,msm8916-iommu"
"qcom,msm8953-iommu"
Followed by "qcom,msm-iommu-v1".
- clock-names : Should be a pair of "iface" (required for IOMMUs
register group access) and "bus" (required for
the IOMMUs underlying bus access).
- clocks : Phandles for respective clocks described by
clock-names.
- #address-cells : must be 1.
- #size-cells : must be 1.
- #iommu-cells : Must be 1. Index identifies the context-bank #.
- ranges : Base address and size of the iommu context banks.
- qcom,iommu-secure-id : secure-id.
- List of sub-nodes, one per translation context bank. Each sub-node
has the following required properties:
- compatible : Should be one of:
- "qcom,msm-iommu-v1-ns" : non-secure context bank
- "qcom,msm-iommu-v1-sec" : secure context bank
- reg : Base address and size of context bank within the iommu
- interrupts : The context fault irq.
** Optional properties:
- reg : Base address and size of the SMMU local base, should
be only specified if the iommu requires configuration
for routing of context bank irq's to secure vs non-
secure lines. (Ie. if the iommu contains secure
context banks)
** Examples:
apps_iommu: iommu@1e20000 {
#address-cells = <1>;
#size-cells = <1>;
#iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x1e20000 0x40000>;
reg = <0x1ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;
clock-names = "iface", "bus";
qcom,iommu-secure-id = <17>;
// mdp_0:
iommu-ctx@4000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x4000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
// venus_ns:
iommu-ctx@5000 {
compatible = "qcom,msm-iommu-v1-sec";
reg = <0x5000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpu_iommu: iommu@1f08000 {
#address-cells = <1>;
#size-cells = <1>;
#iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x1f08000 0x10000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_GFX_TCU_CLK>;
clock-names = "iface", "bus";
qcom,iommu-secure-id = <18>;
// gfx3d_user:
iommu-ctx@1000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
};
// gfx3d_priv:
iommu-ctx@2000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
};
};
...
venus: video-codec@1d00000 {
...
iommus = <&apps_iommu 5>;
};
mdp: mdp@1a01000 {
...
iommus = <&apps_iommu 4>;
};
gpu@1c00000 {
...
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
};
Documentation/devicetree/bindings/iommu/qcom,iommu.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies legacy IOMMU implementations
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm "B" family devices which are not compatible with arm-smmu have
a similar looking IOMMU, but without access to the global register space
and optionally requiring additional configuration to route context IRQs
to non-secure vs secure interrupt line.
properties:
compatible:
items:
- enum:
- qcom,msm8916-iommu
- qcom,msm8953-iommu
- const: qcom,msm-iommu-v1
clocks:
items:
- description: Clock required for IOMMU register group access
- description: Clock required for underlying bus access
clock-names:
items:
- const: iface
- const: bus
power-domains:
maxItems: 1
reg:
maxItems: 1
ranges: true
qcom,iommu-secure-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The SCM secure ID of the IOMMU instance.
'#address-cells':
const: 1
'#size-cells':
const: 1
'#iommu-cells':
const: 1
patternProperties:
"^iommu-ctx@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
enum:
- qcom,msm-iommu-v1-ns
- qcom,msm-iommu-v1-sec
interrupts:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- interrupts
- reg
required:
- compatible
- clocks
- clock-names
- ranges
- '#address-cells'
- '#size-cells'
- '#iommu-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
reg = <0x01ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;
clock-names = "iface", "bus";
qcom,iommu-secure-id = <17>;
#address-cells = <1>;
#size-cells = <1>;
#iommu-cells = <1>;
ranges = <0 0x01e20000 0x40000>;
/* mdp_0: */
iommu-ctx@4000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x4000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml
View file @ d42b1c47
......@@ -58,7 +58,7 @@ examples:
#include <dt-bindings/leds/common.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml
View file @ d42b1c47
......@@ -165,7 +165,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/leds/leds-aw2013.yaml
View file @ d42b1c47
......@@ -54,7 +54,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/leds/leds-rt4505.yaml
View file @ d42b1c47
......@@ -39,7 +39,7 @@ examples:
- |
#include <dt-bindings/leds/common.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/leds/ti,tca6507.yaml
View file @ d42b1c47
......@@ -87,7 +87,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson Message-Handling-Unit Controller
......
Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
......
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APCS global block
......
Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spreadtrum mailbox controller
......
Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 IPC controller
......
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
......@@ -72,6 +72,7 @@ patternProperties:
'^mailbox@[0-9a-f]+$':
description: Internal ipi mailbox node
type: object # DT nodes are json objects
additionalProperties: false
properties:
xlnx,ipi-id:
description:
......
Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml
View file @ d42b1c47
......@@ -82,7 +82,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml
View file @ d42b1c47
......@@ -55,7 +55,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/imx219.yaml
View file @ d42b1c47
......@@ -83,7 +83,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/imx258.yaml
View file @ d42b1c47
......@@ -84,7 +84,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -111,7 +111,7 @@ examples:
};
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
View file @ d42b1c47
......@@ -156,6 +156,7 @@ properties:
patternProperties:
"^i2c@[0-3]$":
type: object
additionalProperties: false
description: |
Child node of the i2c bus multiplexer which represents a GMSL link.
Each serializer device on the GMSL link remote end is represented with
......@@ -167,6 +168,12 @@ properties:
description: The index of the GMSL channel.
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^camera@[a-f0-9]+$":
type: object
......
Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
View file @ d42b1c47
......@@ -106,7 +106,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
i2c2 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml
View file @ d42b1c47
......@@ -81,7 +81,7 @@ examples:
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/ovti,ov772x.yaml
View file @ d42b1c47
......@@ -107,7 +107,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
ov772x: camera@21 {
......
Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml
View file @ d42b1c47
......@@ -82,7 +82,7 @@ examples:
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/gpio/gpio.h>
i2c2 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/ovti,ov9282.yaml
View file @ d42b1c47
......@@ -78,7 +78,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/rda,rda5807.yaml
View file @ d42b1c47
......@@ -50,7 +50,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/sony,imx214.yaml
View file @ d42b1c47
......@@ -97,7 +97,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml
View file @ d42b1c47
......@@ -52,7 +52,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml
View file @ d42b1c47
......@@ -65,7 +65,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/sony,imx335.yaml
View file @ d42b1c47
......@@ -66,7 +66,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/i2c/sony,imx412.yaml
View file @ d42b1c47
......@@ -77,7 +77,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/renesas,vin.yaml
View file @ d42b1c47
......@@ -70,7 +70,7 @@ properties:
resets:
maxItems: 1
#The per-board settings for Gen2 and RZ/G1 platforms:
# The per-board settings for Gen2 and RZ/G1 platforms:
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
......@@ -109,7 +109,7 @@ properties:
data-active: true
#The per-board settings for Gen3 and RZ/G2 platforms:
# The per-board settings for Gen3 and RZ/G2 platforms:
renesas,id:
description: VIN channel number
$ref: /schemas/types.yaml#/definitions/uint32
......
Documentation/devicetree/bindings/media/ti,cal.yaml
View file @ d42b1c47
......@@ -75,7 +75,7 @@ properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI2 Port #0
description: 'CSI2 Port #0'
properties:
endpoint:
......@@ -93,7 +93,7 @@ properties:
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI2 Port #1
description: 'CSI2 Port #1'
properties:
endpoint:
......
Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
View file @ d42b1c47
......@@ -73,6 +73,7 @@ properties:
patternProperties:
"@[0-7],[a-f0-9]+$":
type: object
additionalProperties: true
description: |
The child device node represents the controller connected to the SMC
bus. The controller can be a NAND controller or a pair of any memory
......
Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
View file @ d42b1c47
......@@ -38,6 +38,7 @@ properties:
patternProperties:
"^.*@[0-3],[a-f0-9]+$":
type: object
additionalProperties: true
description:
The actual device nodes should be added as subnodes to the SROMc node.
These subnodes, in addition to regular device specification, should
......
Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml
View file @ d42b1c47
......@@ -57,6 +57,7 @@ patternProperties:
subnodes.
type: object
$ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
additionalProperties: true
required:
- compatible
......
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
View file @ d42b1c47
......@@ -50,6 +50,7 @@ properties:
patternProperties:
"^emc-timings-[0-9]+$":
type: object
additionalProperties: false
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
......
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
View file @ d42b1c47
......@@ -47,6 +47,7 @@ properties:
patternProperties:
"^.*@[0-4],[a-f0-9]+$":
additionalProperties: true
type: object
$ref: mc-peripheral-props.yaml#
......
Documentation/devicetree/bindings/mfd/actions,atc260x.yaml
View file @ d42b1c47
......@@ -129,7 +129,7 @@ required:
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
View file @ d42b1c47
......@@ -246,7 +246,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -263,7 +263,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......@@ -296,7 +296,7 @@ examples:
# Example for FPMCU
- |
spi0 {
spi {
#address-cells = <0x1>;
#size-cells = <0x0>;
......
Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml
View file @ d42b1c47
......@@ -46,6 +46,7 @@ properties:
rtc:
type: object
$ref: /schemas/rtc/rtc.yaml#
unevaluatedProperties: false
description:
MT6357 Real Time Clock.
properties:
......
Documentation/devicetree/bindings/mfd/mediatek,mt6370.yaml
View file @ d42b1c47
......@@ -35,6 +35,7 @@ properties:
adc:
type: object
additionalProperties: false
description: |
Provides 9 channels for system monitoring, including VBUSDIV5 (lower
accuracy, higher measure range), VBUSDIV2 (higher accuracy, lower
......@@ -73,6 +74,7 @@ properties:
regulators:
type: object
additionalProperties: false
description: |
List all supported regulators, which support the control for DisplayBias
voltages and one general purpose LDO which commonly used to drive the
......
Documentation/devicetree/bindings/mfd/ti,tps65086.yaml
View file @ d42b1c47
......@@ -95,7 +95,7 @@ required:
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
View file @ d42b1c47
......@@ -299,7 +299,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -315,7 +315,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
View file @ d42b1c47
......@@ -42,6 +42,7 @@ patternProperties:
"^sdhci@[0-9a-f]+$":
type: object
$ref: mmc-controller.yaml
unevaluatedProperties: false
properties:
compatible:
......
Documentation/devicetree/bindings/mtd/mtd.yaml
View file @ d42b1c47
......@@ -44,6 +44,7 @@ patternProperties:
"^otp(-[0-9]+)?$":
$ref: ../nvmem/nvmem.yaml#
unevaluatedProperties: false
description: |
An OTP memory region. Some flashes provide a one-time-programmable
......
Documentation/devicetree/bindings/net/asix,ax88796c.yaml
View file @ d42b1c47
......@@ -58,7 +58,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/net/brcm,bcmgenet.yaml
View file @ d42b1c47
......@@ -73,8 +73,6 @@ allOf:
unevaluatedProperties: false
examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
- |
ethernet@f0b60000 {
phy-mode = "internal";
......
Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml
View file @ d42b1c47
......@@ -62,7 +62,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
View file @ d42b1c47
......@@ -31,9 +31,9 @@ properties:
ranges: true
#The subnodes represents the two ethernet ports in this device.
#They are not independent of each other since they share resources
#in the parent node, and are thus children.
# The subnodes represents the two ethernet ports in this device.
# They are not independent of each other since they share resources
# in the parent node, and are thus children.
patternProperties:
"^ethernet-port@[0-9]+$":
type: object
......
Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
View file @ d42b1c47
......@@ -67,7 +67,7 @@ examples:
};
};
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/net/mdio-gpio.yaml
View file @ d42b1c47
......@@ -33,8 +33,8 @@ properties:
- description: MDIO
- description: MDO
#Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
#node.
# Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
# node.
additionalProperties:
type: object
......
Documentation/devicetree/bindings/net/nfc/samsung,s3fwrn5.yaml
View file @ d42b1c47
......@@ -69,7 +69,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c4 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/net/sti-dwmac.txt
View file @ d42b1c47
......@@ -7,8 +7,7 @@ and what is needed on STi platforms to program the stmmac glue logic.
The device node has following properties.
Required properties:
- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
"st,stih407-dwmac", "st,stid127-dwmac".
- compatible : "st,stih407-dwmac"
- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
encompases the glue register, and the offset of the control register.
- st,gmac_en: this is to enable the gmac into a dedicated sysctl control
......
Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml
View file @ d42b1c47
......@@ -55,7 +55,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml
View file @ d42b1c47
......@@ -89,7 +89,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
// For wl12xx family:
spi1 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......@@ -104,8 +104,11 @@ examples:
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
// For wl18xx family:
spi2 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......@@ -118,6 +121,9 @@ examples:
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
// SDIO example:
mmc3 {
vmmc-supply = <&wlan_en_reg>;
......
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- Tom Joseph <tjoseph@cadence.com>
allOf:
- $ref: "cdns-pcie-ep.yaml#"
- $ref: cdns-pcie-ep.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
View file @ d42b1c47
......@@ -11,7 +11,7 @@ maintainers:
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: "cdns-pcie-host.yaml#"
- $ref: cdns-pcie-host.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence PCIe Device
......@@ -10,8 +10,8 @@ maintainers:
- Tom Joseph <tjoseph@cadence.com>
allOf:
- $ref: "cdns-pcie.yaml#"
- $ref: "pci-ep.yaml#"
- $ref: cdns-pcie.yaml#
- $ref: pci-ep.yaml#
properties:
cdns,max-outbound-regions:
......
Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence PCIe Host
......@@ -10,8 +10,8 @@ maintainers:
- Tom Joseph <tjoseph@cadence.com>
allOf:
- $ref: "/schemas/pci/pci-bus.yaml#"
- $ref: "cdns-pcie.yaml#"
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: cdns-pcie.yaml#
properties:
cdns,max-outbound-regions:
......
Documentation/devicetree/bindings/pci/cdns-pcie.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/cdns-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence PCIe Core
......
Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay PCIe controller Endpoint mode
......
Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay PCIe controller Root Complex mode
......
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
View file @ d42b1c47
......@@ -45,7 +45,7 @@ properties:
description: Reference to a syscon representing TCSR followed by the two
offsets within syscon for Perst enable and Perst separation
enable registers
$ref: "/schemas/types.yaml#/definitions/phandle-array"
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: Syscon to TCSR system registers
......
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI J721E PCI EP (PCIe Wrapper)
......@@ -11,7 +11,7 @@ maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
allOf:
- $ref: "cdns-pcie-ep.yaml#"
- $ref: cdns-pcie-ep.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI J721E PCI Host (PCIe Wrapper)
......@@ -11,7 +11,7 @@ maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
allOf:
- $ref: "cdns-pcie-host.yaml#"
- $ref: cdns-pcie-host.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
View file @ d42b1c47
......@@ -41,7 +41,7 @@ properties:
Phandle to the system controller node
$ref: /schemas/types.yaml#/definitions/phandle
#Required child nodes:
# Required child nodes:
patternProperties:
"^usb-phy@[0|1]$":
......
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
View file @ d42b1c47
......@@ -55,7 +55,7 @@ properties:
description: number of clock cells for ck_usbo_48m consumer
const: 0
#Required child nodes:
# Required child nodes:
patternProperties:
"^usb-phy@[0|1]$":
......
Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
View file @ d42b1c47
......@@ -83,7 +83,7 @@ properties:
description:
Phandle to a regulator supply to any specific refclk pll block.
#Required nodes:
# Required nodes:
patternProperties:
"^usb3-phy@[0-9a-f]+$":
type: object
......
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
View file @ d42b1c47
......@@ -51,7 +51,7 @@ properties:
description: The interrupt outputs to sysirq.
maxItems: 1
#PIN CONFIGURATION NODES
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
......
Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml
View file @ d42b1c47
......@@ -31,7 +31,7 @@ description: |
};
};
state_1_node_a {
spi0 {
spi {
function = "spi0";
groups = "spi0pins";
};
......
Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
View file @ d42b1c47
......@@ -293,7 +293,7 @@ examples:
pinctrl-names = "default";
};
i2c0 {
i2c {
pinctrl-0 = <&i2c0_pins_default>;
pinctrl-names = "default";
};
......
Documentation/devicetree/bindings/power/supply/bq2415x.yaml
View file @ d42b1c47
......@@ -77,7 +77,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq24190.yaml
View file @ d42b1c47
......@@ -75,7 +75,7 @@ examples:
charge-term-current-microamp = <128000>;
};
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq24257.yaml
View file @ d42b1c47
......@@ -84,7 +84,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -104,7 +104,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq24735.yaml
View file @ d42b1c47
......@@ -77,7 +77,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq2515x.yaml
View file @ d42b1c47
......@@ -73,7 +73,7 @@ examples:
constant-charge-voltage-max-microvolt = <4000000>;
};
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq25890.yaml
View file @ d42b1c47
......@@ -102,7 +102,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq25980.yaml
View file @ d42b1c47
......@@ -95,7 +95,7 @@ examples:
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
View file @ d42b1c47
......@@ -75,15 +75,16 @@ additionalProperties: false
examples:
- |
i2c0 {
bat: battery {
compatible = "simple-battery";
voltage-min-design-microvolt = <3200000>;
energy-full-design-microwatt-hours = <5290000>;
charge-full-design-microamp-hours = <1430000>;
};
i2c {
#address-cells = <1>;
#size-cells = <0>;
bat: battery {
compatible = "simple-battery";
voltage-min-design-microvolt = <3200000>;
energy-full-design-microwatt-hours = <5290000>;
charge-full-design-microamp-hours = <1430000>;
};
bq27510g3: fuel-gauge@55 {
compatible = "ti,bq27510g3";
......
Documentation/devicetree/bindings/power/supply/lltc,ltc294x.yaml
View file @ d42b1c47
......@@ -54,7 +54,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
battery@64 {
......
Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml
View file @ d42b1c47
......@@ -54,7 +54,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
charger: battery-charger@68 {
......
Documentation/devicetree/bindings/power/supply/maxim,max14656.yaml
View file @ d42b1c47
......@@ -32,7 +32,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/maxim,max17040.yaml
View file @ d42b1c47
......@@ -68,7 +68,7 @@ unevaluatedProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......@@ -82,7 +82,7 @@ examples:
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/maxim,max17042.yaml
View file @ d42b1c47
......@@ -69,7 +69,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/richtek,rt9455.yaml
View file @ d42b1c47
......@@ -68,7 +68,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/power/supply/ti,lp8727.yaml
View file @ d42b1c47
......@@ -28,6 +28,7 @@ properties:
patternProperties:
'^(ac|usb)$':
type: object
additionalProperties: false
description: USB/AC charging parameters
properties:
charger-type:
......@@ -61,7 +62,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/regulator/active-semi,act8865.yaml
View file @ d42b1c47
......@@ -90,7 +90,7 @@ examples:
- |
#include <dt-bindings/regulator/active-semi,8865-regulator.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/regulator/google,cros-ec-regulator.yaml
View file @ d42b1c47
......@@ -32,7 +32,7 @@ unevaluatedProperties: false
examples:
- |
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml
View file @ d42b1c47
......@@ -17,10 +17,10 @@ description: |
Datasheet is available at
https://www.nxp.com/docs/en/data-sheet/PCA9450DS.pdf
#The valid names for PCA9450 regulator nodes are:
#BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6,
#LDO1, LDO2, LDO3, LDO4, LDO5
#Note: Buck3 removed on PCA9450B and connect with Buck1 on PCA9450C.
# The valid names for PCA9450 regulator nodes are:
# BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6,
# LDO1, LDO2, LDO3, LDO4, LDO5
# Note: Buck3 removed on PCA9450B and connect with Buck1 on PCA9450C.
properties:
compatible:
......
Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml
View file @ d42b1c47
......@@ -92,7 +92,7 @@ additionalProperties: false
examples:
- |
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml
View file @ d42b1c47
......@@ -82,20 +82,20 @@ patternProperties:
# Supported default DVS states:
# buck | run | idle | suspend | lpsr
#--------------------------------------------------------------
# --------------------------------------------------------------
# 1, 2, 6, and 7 | supported | supported | supported (*)
#--------------------------------------------------------------
# --------------------------------------------------------------
# 3, 4, and 5 | supported (**)
#--------------------------------------------------------------
# --------------------------------------------------------------
#
#(*) LPSR and SUSPEND states use same voltage but both states have own
# enable /
# disable settings. Voltage 0 can be specified for a state to make
# regulator disabled on that state.
# (*) LPSR and SUSPEND states use same voltage but both states have own
# enable /
# disable settings. Voltage 0 can be specified for a state to make
# regulator disabled on that state.
#
#(**) All states use same voltage but have own enable / disable
# settings. Voltage 0 can be specified for a state to make
# regulator disabled on that state.
# (**) All states use same voltage but have own enable / disable
# settings. Voltage 0 can be specified for a state to make
# regulator disabled on that state.
required:
- regulator-name
......
Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml
View file @ d42b1c47
......@@ -23,9 +23,9 @@ description: |
if they are disabled at startup the voltage monitoring for LDO5/LDO6 will
cause PMIC to reset.
#The valid names for BD71837 regulator nodes are:
#BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7, BUCK8
#LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7
# The valid names for BD71837 regulator nodes are:
# BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7, BUCK8
# LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7
patternProperties:
"^LDO[1-7]$":
......
Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml
View file @ d42b1c47
......@@ -22,9 +22,9 @@ description: |
not be disabled by driver at startup. If BUCK5 is disabled at startup the
voltage monitoring for LDO5/LDO6 can cause PMIC to reset.
#The valid names for BD71847 regulator nodes are:
#BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6
#LDO1, LDO2, LDO3, LDO4, LDO5, LDO6
# The valid names for BD71847 regulator nodes are:
# BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6
# LDO1, LDO2, LDO3, LDO4, LDO5, LDO6
patternProperties:
"^LDO[1-6]$":
......
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
View file @ d42b1c47
......@@ -157,6 +157,7 @@ properties:
mba:
type: object
additionalProperties: false
description:
MBA reserved region (prefer using memory-region with two items)
properties:
......@@ -167,6 +168,7 @@ properties:
mpss:
type: object
additionalProperties: false
description:
MPSS reserved region (prefer using memory-region with two items)
properties:
......
Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
View file @ d42b1c47
......@@ -16,7 +16,7 @@ maintainers:
- David Brazdil <dbrazdil@google.com>
allOf:
- $ref: "reserved-memory.yaml"
- $ref: reserved-memory.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml
View file @ d42b1c47
......@@ -14,7 +14,7 @@ description: On Tegra210, firmware passes a binary representation of the
EMC frequency table via a reserved memory region.
allOf:
- $ref: "reserved-memory.yaml"
- $ref: reserved-memory.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reserved-memory/phram.yaml
View file @ d42b1c47
......@@ -17,8 +17,8 @@ maintainers:
- Vincent Whitchurch <vincent.whitchurch@axis.com>
allOf:
- $ref: "reserved-memory.yaml"
- $ref: "/schemas/mtd/mtd.yaml"
- $ref: reserved-memory.yaml
- $ref: /schemas/mtd/mtd.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reserved-memory/qcom,cmd-db.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reserved-memory/qcom,cmd-db.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Command DB
......@@ -20,7 +20,7 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
allOf:
- $ref: "reserved-memory.yaml"
- $ref: reserved-memory.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reserved-memory/qcom,rmtfs-mem.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reserved-memory/qcom,rmtfs-mem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Remote File System Memory
......@@ -15,7 +15,7 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
allOf:
- $ref: "reserved-memory.yaml"
- $ref: reserved-memory.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reserved-memory/ramoops.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reserved-memory/ramoops.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reserved-memory/ramoops.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ramoops oops/panic logger
......@@ -27,7 +27,7 @@ maintainers:
- Kees Cook <keescook@chromium.org>
allOf:
- $ref: "reserved-memory.yaml"
- $ref: reserved-memory.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reserved-memory/shared-dma-pool.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- devicetree-spec@vger.kernel.org
allOf:
- $ref: "reserved-memory.yaml"
- $ref: reserved-memory.yaml
properties:
compatible:
......
Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic audio memory arbiter controller
......
Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson SoC Reset Controller
......
Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019 Manivannan Sadhasivam <mani@kernel.org>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bitmain BM1880 SoC Reset Controller
......
Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM6345 reset controller
......
Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2020 Broadcom
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM7216 RESCAL reset controller
......
Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom STB SW_INIT-style reset controller
......
Documentation/devicetree/bindings/reset/marvell,berlin2-reset.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2015 Antoine Tenart <atenart@kernel.org>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin reset controller
......
Documentation/devicetree/bindings/reset/microchip,rst.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Sparx5 Switch Reset Controller
......@@ -36,7 +36,7 @@ properties:
const: 1
cpu-syscon:
$ref: "/schemas/types.yaml#/definitions/phandle"
$ref: /schemas/types.yaml#/definitions/phandle
description: syscon used to access CPU reset
required:
......
Documentation/devicetree/bindings/reset/qca,ar7100-reset.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2015 Alban Bedel <albeu@free.fr>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
......
Documentation/devicetree/bindings/reset/renesas,rst.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/renesas,rst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car and RZ/G Reset Controller
......
Documentation/devicetree/bindings/reset/sunplus,reset.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/reset/sunplus,reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sunplus SoC Reset Controller
......
Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/rng/amlogic,meson-rng.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/rng/amlogic,meson-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson Random number generator
......
Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/rng/brcm,iproc-rng200.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/rng/brcm,iproc-rng200.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HWRNG support for the iproc-rng200 driver
......
Documentation/devicetree/bindings/rng/mtk-rng.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/rng/mtk-rng.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/rng/mtk-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Random number generator
......
Documentation/devicetree/bindings/rng/ti,keystone-rng.yaml
View file @ d42b1c47
......@@ -25,7 +25,7 @@ properties:
maxItems: 1
ti,syscon-sa-cfg:
$ref: "/schemas/types.yaml#/definitions/phandle"
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to syscon node of the SA configuration registers. These
registers are shared between HWRNG and crypto drivers.
......
Documentation/devicetree/bindings/rtc/snvs-rtc.txt deleted 100644 → 0
View file @ 6df969b7
See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details.
Documentation/devicetree/bindings/serial/mediatek,uart.yaml
View file @ d42b1c47
......@@ -45,6 +45,7 @@ properties:
- mediatek,mt8188-uart
- mediatek,mt8192-uart
- mediatek,mt8195-uart
- mediatek,mt8365-uart
- mediatek,mt8516-uart
- const: mediatek,mt6577-uart
......
Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml
View file @ d42b1c47
......@@ -38,8 +38,9 @@ properties:
patternProperties:
"power-domain@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
items:
......
Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# # Copyright 2020 MediaTek Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/mediatek/devapc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/mediatek/devapc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Device Access Permission Control driver
......
Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
View file @ d42b1c47
......@@ -54,6 +54,7 @@ patternProperties:
"^timer@[0-2]$":
description: The timer block channels that are used as timers or counters.
type: object
additionalProperties: false
properties:
compatible:
items:
......
Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router)
......
Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,eud.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/qcom/qcom,eud.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Embedded USB Debugger
......
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GENI Serial Engine QUP Wrapper Controller
......
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Resource Power Manager (RPM) over SMD/GLINK
......
Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,smem.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/qcom/qcom,smem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Shared Memory Manager
......
Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Subsystem Power Manager
......
Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml
View file @ d42b1c47
......@@ -20,7 +20,7 @@ properties:
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
default: "wlan/prima/WCNSS_qcom_wlan_nv.bin"
default: wlan/prima/WCNSS_qcom_wlan_nv.bin
description:
Relative firmware image path for the WLAN NV blob.
......
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View file @ d42b1c47
......@@ -111,7 +111,7 @@ properties:
- description: RZ/G1C (R8A77470)
items:
- enum:
- iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
- iwave,g23s # iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
- const: renesas,r8a77470
- description: RZ/G2M (R8A774A1)
......
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
View file @ d42b1c47
......@@ -130,6 +130,7 @@ patternProperties:
PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
type: object
additionalProperties: false
properties:
compatible:
......@@ -313,7 +314,7 @@ additionalProperties: false
# Due to inability of correctly verifying sub-nodes with an @address through
# the "required" list, the required sub-nodes below are commented out for now.
#required:
# required:
# - memories
# - interrupt-controller
# - pru
......
Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.yaml
View file @ d42b1c47
......@@ -24,7 +24,7 @@ properties:
items:
- description: Bit clock
- description: Sample clock
- description: Master clock #optional
- description: Master clock # optional
clock-names:
minItems: 2
......
Documentation/devicetree/bindings/sound/everest,es8316.yaml
View file @ d42b1c47
......@@ -40,7 +40,7 @@ unevaluatedProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
es8316: codec@11 {
......
Documentation/devicetree/bindings/sound/marvell,mmp-sspa.yaml
View file @ d42b1c47
......@@ -60,6 +60,7 @@ properties:
properties:
endpoint:
type: object
additionalProperties: true
properties:
dai-format:
......
Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
View file @ d42b1c47
......@@ -34,13 +34,13 @@ properties:
clock-names:
oneOf:
- items: #for ADSP based platforms
- items: # for ADSP based platforms
- const: mclk
- const: npl
- const: macro
- const: dcodec
- const: fsgen
- items: #for ADSP bypass based platforms
- items: # for ADSP bypass based platforms
- const: mclk
- const: npl
- const: fsgen
......
Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
View file @ d42b1c47
......@@ -36,13 +36,13 @@ properties:
clock-names:
oneOf:
- items: #for ADSP based platforms
- items: # for ADSP based platforms
- const: mclk
- const: npl
- const: macro
- const: dcodec
- const: fsgen
- items: #for ADSP bypass based platforms
- items: # for ADSP bypass based platforms
- const: mclk
- const: npl
- const: fsgen
......
Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
View file @ d42b1c47
......@@ -34,11 +34,11 @@ properties:
clock-names:
oneOf:
- items: #for ADSP based platforms
- items: # for ADSP based platforms
- const: mclk
- const: macro
- const: dcodec
- items: #for ADSP bypass based platforms
- items: # for ADSP bypass based platforms
- const: mclk
clock-output-names:
......
Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml
View file @ d42b1c47
......@@ -26,7 +26,7 @@ properties:
'#size-cells':
const: 0
#Digital Audio Interfaces
# Digital Audio Interfaces
patternProperties:
'^dai@[0-9]+$':
type: object
......
Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml
View file @ d42b1c47
......@@ -134,6 +134,7 @@ properties:
patternProperties:
"^.*@[0-9a-f]+$":
type: object
additionalProperties: true
description: |
WCD934x subnode for each slave devices. Bindings of each subnodes
depends on the specific driver providing the functionality and
......
Documentation/devicetree/bindings/sound/samsung,odroid.yaml
View file @ d42b1c47
......@@ -35,12 +35,14 @@ properties:
cpu:
type: object
additionalProperties: false
properties:
sound-dai:
description: phandles to the I2S controllers
codec:
type: object
additionalProperties: false
properties:
sound-dai:
minItems: 1
......
Documentation/devicetree/bindings/sound/simple-card.yaml
View file @ d42b1c47
......@@ -262,9 +262,9 @@ required:
additionalProperties: false
examples:
#--------------------
# --------------------
# single DAI link
#--------------------
# --------------------
- |
sound {
compatible = "simple-audio-card";
......@@ -291,9 +291,9 @@ examples:
};
};
#--------------------
# --------------------
# Multi DAI links
#--------------------
# --------------------
- |
sound {
compatible = "simple-audio-card";
......@@ -334,10 +334,10 @@ examples:
};
};
#--------------------
# --------------------
# route audio from IMX6 SSI2 through TLV320DAC3100 codec
# through TPA6130A2 amplifier to headphones:
#--------------------
# --------------------
- |
sound {
compatible = "simple-audio-card";
......@@ -359,9 +359,9 @@ examples:
};
};
#--------------------
# --------------------
# Sampling Rate Conversion
#--------------------
# --------------------
- |
sound {
compatible = "simple-audio-card";
......@@ -387,9 +387,9 @@ examples:
};
};
#--------------------
# --------------------
# 2 CPU 1 Codec (Mixing)
#--------------------
# --------------------
- |
sound {
compatible = "simple-audio-card";
......@@ -424,7 +424,7 @@ examples:
};
};
#--------------------
# --------------------
# Multi DAI links with DPCM:
#
# CPU0 ------ ak4613
......@@ -433,7 +433,7 @@ examples:
# CPU3 --/ /* DPCM 5ch/6ch */
# CPU4 --/ /* DPCM 7ch/8ch */
# CPU5 ------ PCM3168A-c
#--------------------
# --------------------
- |
sound {
compatible = "simple-audio-card";
......
Documentation/devicetree/bindings/sound/tas2562.yaml
View file @ d42b1c47
......@@ -66,7 +66,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
codec: codec@4c {
......
Documentation/devicetree/bindings/sound/tas2770.yaml
View file @ d42b1c47
......@@ -68,7 +68,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
codec: codec@41 {
......
Documentation/devicetree/bindings/sound/tas27xx.yaml
View file @ d42b1c47
......@@ -61,7 +61,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
codec: codec@38 {
......
Documentation/devicetree/bindings/sound/tas5805m.yaml
View file @ d42b1c47
......@@ -39,7 +39,7 @@ properties:
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
tas5805m: tas5805m@2c {
......
Documentation/devicetree/bindings/sound/tlv320adcx140.yaml
View file @ d42b1c47
......@@ -192,7 +192,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
codec: codec@4c {
......
Documentation/devicetree/bindings/sound/zl38060.yaml
View file @ d42b1c47
......@@ -56,7 +56,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml
View file @ d42b1c47
......@@ -200,6 +200,7 @@ properties:
patternProperties:
"^.*@[0-9a-f],[0-9a-f]$":
type: object
additionalProperties: true
description:
Child nodes for a standalone audio codec or speaker amplifier IC.
It has RX and TX Soundwire secondary devices.
......
Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
View file @ d42b1c47
......@@ -51,6 +51,7 @@ properties:
patternProperties:
"^.*@[0-9a-f]+":
type: object
additionalProperties: true
properties:
reg:
items:
......
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
View file @ d42b1c47
......@@ -63,6 +63,7 @@ properties:
patternProperties:
"^.*@[0-9a-f]+":
type: object
additionalProperties: true
properties:
reg:
items:
......
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
View file @ d42b1c47
......@@ -22,7 +22,7 @@ properties:
- items:
- const: microchip,mpfs-qspi
- const: microchip,coreqspi-rtl-v2
- const: microchip,coreqspi-rtl-v2 #FPGA QSPI
- const: microchip,coreqspi-rtl-v2 # FPGA QSPI
- const: microchip,mpfs-spi
reg:
......
Documentation/devicetree/bindings/spi/spi-controller.yaml
View file @ d42b1c47
......@@ -94,6 +94,7 @@ patternProperties:
"^.*@[0-9a-f]+$":
type: object
$ref: spi-peripheral-props.yaml
additionalProperties: true
properties:
spi-3wire:
......
Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
View file @ d42b1c47
......@@ -57,17 +57,17 @@ properties:
patternProperties:
"^sram@[a-z0-9]+":
type: object
properties:
compatible:
const: mmio-sram
$ref: /schemas/sram/sram.yaml#
unevaluatedProperties: false
patternProperties:
"^sram-section?@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
reg: true
compatible:
oneOf:
- const: allwinner,sun4i-a10-sram-a3-a4
......
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
View file @ d42b1c47
......@@ -61,6 +61,7 @@ additionalProperties: false
patternProperties:
"-sram@[0-9a-f]+$":
type: object
additionalProperties: false
description: A region of reserved memory.
properties:
......
Documentation/devicetree/bindings/thermal/thermal-zones.yaml
View file @ d42b1c47
......@@ -171,6 +171,7 @@ patternProperties:
cooling-maps:
type: object
additionalProperties: false
description:
This node describes the action to be taken when a thermal zone
crosses one of the temperature thresholds described in the trips
......
Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt deleted 100644 → 0
View file @ 6df969b7
Amlogic Meson6 SoCs Timer Controller
Required properties:
- compatible : should be "amlogic,meson6-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The four interrupts, one for each timer event
- clocks : phandles to the pclk (system clock) and XTAL clocks
- clock-names : must contain "pclk" and "xtal"
Example:
timer@c1109940 {
compatible = "amlogic,meson6-timer";
reg = <0xc1109940 0x14>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clk81>;
clock-names = "xtal", "pclk";
};
Documentation/devicetree/bindings/timer/amlogic,meson6-timer.yaml 0 → 100644
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/amlogic,meson6-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson6 SoCs Timer Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
properties:
compatible:
const: amlogic,meson6-timer
reg:
maxItems: 1
interrupts:
maxItems: 4
description: per-timer event interrupts
clocks:
maxItems: 2
clock-names:
items:
- const: xtal
- const: pclk
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@c1109940 {
compatible = "amlogic,meson6-timer";
reg = <0xc1109940 0x14>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clk81>;
clock-names = "xtal", "pclk";
};
Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
View file @ d42b1c47
......@@ -66,7 +66,7 @@ patternProperties:
description: A timer node has up to 8 frame sub-nodes, each with the following properties.
properties:
frame-number:
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
......
Documentation/devicetree/bindings/timer/cdns,ttc.yaml
View file @ d42b1c47
......@@ -28,7 +28,7 @@ properties:
maxItems: 1
timer-width:
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Bit width of the timer, necessary if not 16.
......
Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx XScale Networking Processors Timers
......
Documentation/devicetree/bindings/timer/nvidia,tegra-timer.yaml
View file @ d42b1c47
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra timer
......
Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
View file @ d42b1c47
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 timer
......
Documentation/devicetree/bindings/timer/st,nomadik-mtu.yaml
View file @ d42b1c47
......@@ -2,8 +2,8 @@
# Copyright 2022 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/st,nomadik-mtu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/timer/st,nomadik-mtu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ST Microelectronics Nomadik Multi-Timer Unit MTU Timer
......
Documentation/devicetree/bindings/usb/maxim,max33359.yaml
View file @ d42b1c47
......@@ -40,7 +40,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/usb/pd.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml
View file @ d42b1c47
......@@ -52,7 +52,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/mediatek,mt6360-tcpc.yaml
View file @ d42b1c47
......@@ -43,7 +43,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/usb/pd.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
View file @ d42b1c47
......@@ -121,6 +121,7 @@ properties:
patternProperties:
"^usb@[0-9a-f]+$":
$ref: snps,dwc3.yaml#
unevaluatedProperties: false
properties:
wakeup-source: false
......
Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml
View file @ d42b1c47
......@@ -51,7 +51,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/usb/pd.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/richtek,rt1719.yaml
View file @ d42b1c47
......@@ -48,7 +48,7 @@ required:
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/st,stusb160x.yaml
View file @ d42b1c47
......@@ -56,7 +56,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c4 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml
View file @ d42b1c47
......@@ -51,7 +51,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/usb/ti,tps6598x.yaml
View file @ d42b1c47
......@@ -43,7 +43,7 @@ additionalProperties: true
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file @ d42b1c47
......@@ -941,6 +941,8 @@ patternProperties:
description: Nokia
"^nordic,.*":
description: Nordic Semiconductor
"^novatek,.*":
description: Novatek
"^novtech,.*":
description: NovTech, Inc.
"^nutsboard,.*":
......
Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
View file @ d42b1c47
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Watchdog
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
maintainers:
- Chen-Yu Tsai <wens@csie.org>
......
Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
View file @ d42b1c47
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SoC Watchdog
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
maintainers:
- Sven Peter <sven@svenpeter.dev>
......
Documentation/devicetree/bindings/watchdog/arm-smc-wdt.yaml
View file @ d42b1c47
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Secure Monitor Call based watchdog
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
maintainers:
- Julius Werner <jwerner@chromium.org>
......
Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- Eugen Hristev <eugen.hristev@microchip.com>
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
View file @ d42b1c47
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM63xx and BCM7038 watchdog timer
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
......
Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml
View file @ d42b1c47
......@@ -15,7 +15,7 @@ description: |
SoCs and others.
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- Anson Huang <Anson.Huang@nxp.com>
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml
View file @ d42b1c47
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim 63xx Watchdog Timers
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
maintainers:
......
Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
View file @ d42b1c47
......@@ -115,7 +115,7 @@ required:
- clocks
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
- if:
not:
......
Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
View file @ d42b1c47
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys Designware Watchdog Timer
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
maintainers:
- Jamie Iles <jamie@jamieiles.com>
......
Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml
View file @ d42b1c47
......@@ -10,7 +10,7 @@ maintainers:
- Keiji Hayashibara <hayashibara.keiji@socionext.com>
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
View file @ d42b1c47
......@@ -11,7 +11,7 @@ maintainers:
- Christophe Roullier <christophe.roullier@foss.st.com>
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml
View file @ d42b1c47
......@@ -18,7 +18,7 @@ description:
to directly reset the SoC.
allOf:
- $ref: "watchdog.yaml#"
- $ref: watchdog.yaml#
properties:
compatible:
......
MAINTAINERS
View file @ d42b1c47
......@@ -8134,7 +8134,7 @@ M: Pankaj Gupta <pankaj.gupta@nxp.com>
M: Gaurav Jain <gaurav.jain@nxp.com>
L: linux-crypto@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/fsl-sec4.txt
F: Documentation/devicetree/bindings/crypto/fsl,sec-v4.0*
F: drivers/crypto/caam/
FREESCALE COLDFIRE M5441X MMC DRIVER
......@@ -11932,6 +11932,7 @@ M: Scott Wood <oss@buserror.net>
L: linuxppc-dev@lists.ozlabs.org
S: Odd fixes
T: git git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
F: Documentation/devicetree/bindings/cache/freescale-l2cache.txt
F: Documentation/devicetree/bindings/powerpc/fsl/
F: arch/powerpc/platforms/83xx/
F: arch/powerpc/platforms/85xx/
......@@ -19163,6 +19164,7 @@ M: Conor Dooley <conor@kernel.org>
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
F: drivers/soc/sifive/
SILEAD TOUCHSCREEN DRIVER
......
drivers/of/address.c
View file @ d42b1c47
......@@ -22,11 +22,6 @@
#define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
#define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && (ns) > 0)
static struct of_bus *of_match_bus(struct device_node *np);
static int __of_address_to_resource(struct device_node *dev, int index,
int bar_no, struct resource *r);
static bool of_mmio_is_nonposted(struct device_node *np);
/* Debug utility */
#ifdef DEBUG
static void of_dump_addr(const char *s, const __be32 *addr, int na)
......@@ -195,17 +190,6 @@ static int of_bus_pci_translate(__be32 *addr, u64 offset, int na)
}
#endif /* CONFIG_PCI */
int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r)
{
if (!IS_ENABLED(CONFIG_PCI))
return -ENOSYS;
return __of_address_to_resource(dev, -1, bar, r);
}
EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
/*
* of_pci_range_to_resource - Create a resource from an of_pci_range
* @range: the PCI range that describes the resource
......@@ -213,7 +197,7 @@ EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
* @res: pointer to a valid resource that will be updated to
* reflect the values contained in the range.
*
* Returns EINVAL if the range cannot be converted to resource.
* Returns -EINVAL if the range cannot be converted to resource.
*
* Note that if the range is an IO range, the resource will be converted
* using pci_address_to_pio() which can fail if it is called too early or
......@@ -834,126 +818,6 @@ static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr,
return port;
}
static int __of_address_to_resource(struct device_node *dev, int index, int bar_no,
struct resource *r)
{
u64 taddr;
const __be32 *addrp;
u64 size;
unsigned int flags;
const char *name = NULL;
addrp = __of_get_address(dev, index, bar_no, &size, &flags);
if (addrp == NULL)
return -EINVAL;
/* Get optional "reg-names" property to add a name to a resource */
if (index >= 0)
of_property_read_string_index(dev, "reg-names", index, &name);
if (flags & IORESOURCE_MEM)
taddr = of_translate_address(dev, addrp);
else if (flags & IORESOURCE_IO)
taddr = of_translate_ioport(dev, addrp, size);
else
return -EINVAL;
if (taddr == OF_BAD_ADDR)
return -EINVAL;
memset(r, 0, sizeof(struct resource));
if (of_mmio_is_nonposted(dev))
flags |= IORESOURCE_MEM_NONPOSTED;
r->start = taddr;
r->end = taddr + size - 1;
r->flags = flags;
r->name = name ? name : dev->full_name;
return 0;
}
/**
* of_address_to_resource - Translate device tree address and return as resource
* @dev: Caller's Device Node
* @index: Index into the array
* @r: Pointer to resource array
*
* Note that if your address is a PIO address, the conversion will fail if
* the physical address can't be internally converted to an IO token with
* pci_address_to_pio(), that is because it's either called too early or it
* can't be matched to any host bridge IO space
*/
int of_address_to_resource(struct device_node *dev, int index,
struct resource *r)
{
return __of_address_to_resource(dev, index, -1, r);
}
EXPORT_SYMBOL_GPL(of_address_to_resource);
/**
* of_iomap - Maps the memory mapped IO for a given device_node
* @np: the device whose io range will be mapped
* @index: index of the io range
*
* Returns a pointer to the mapped memory
*/
void __iomem *of_iomap(struct device_node *np, int index)
{
struct resource res;
if (of_address_to_resource(np, index, &res))
return NULL;
if (res.flags & IORESOURCE_MEM_NONPOSTED)
return ioremap_np(res.start, resource_size(&res));
else
return ioremap(res.start, resource_size(&res));
}
EXPORT_SYMBOL(of_iomap);
/*
* of_io_request_and_map - Requests a resource and maps the memory mapped IO
* for a given device_node
* @device: the device whose io range will be mapped
* @index: index of the io range
* @name: name "override" for the memory region request or NULL
*
* Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded
* error code on failure. Usage example:
*
* base = of_io_request_and_map(node, 0, "foo");
* if (IS_ERR(base))
* return PTR_ERR(base);
*/
void __iomem *of_io_request_and_map(struct device_node *np, int index,
const char *name)
{
struct resource res;
void __iomem *mem;
if (of_address_to_resource(np, index, &res))
return IOMEM_ERR_PTR(-EINVAL);
if (!name)
name = res.name;
if (!request_mem_region(res.start, resource_size(&res), name))
return IOMEM_ERR_PTR(-EBUSY);
if (res.flags & IORESOURCE_MEM_NONPOSTED)
mem = ioremap_np(res.start, resource_size(&res));
else
mem = ioremap(res.start, resource_size(&res));
if (!mem) {
release_mem_region(res.start, resource_size(&res));
return IOMEM_ERR_PTR(-ENOMEM);
}
return mem;
}
EXPORT_SYMBOL(of_io_request_and_map);
#ifdef CONFIG_HAS_DMA
/**
* of_dma_get_range - Get DMA range info and put it into a map array
......@@ -1150,3 +1014,136 @@ static bool of_mmio_is_nonposted(struct device_node *np)
of_node_put(parent);
return nonposted;
}
static int __of_address_to_resource(struct device_node *dev, int index, int bar_no,
struct resource *r)
{
u64 taddr;
const __be32 *addrp;
u64 size;
unsigned int flags;
const char *name = NULL;
addrp = __of_get_address(dev, index, bar_no, &size, &flags);
if (addrp == NULL)
return -EINVAL;
/* Get optional "reg-names" property to add a name to a resource */
if (index >= 0)
of_property_read_string_index(dev, "reg-names", index, &name);
if (flags & IORESOURCE_MEM)
taddr = of_translate_address(dev, addrp);
else if (flags & IORESOURCE_IO)
taddr = of_translate_ioport(dev, addrp, size);
else
return -EINVAL;
if (taddr == OF_BAD_ADDR)
return -EINVAL;
memset(r, 0, sizeof(struct resource));
if (of_mmio_is_nonposted(dev))
flags |= IORESOURCE_MEM_NONPOSTED;
r->start = taddr;
r->end = taddr + size - 1;
r->flags = flags;
r->name = name ? name : dev->full_name;
return 0;
}
/**
* of_address_to_resource - Translate device tree address and return as resource
* @dev: Caller's Device Node
* @index: Index into the array
* @r: Pointer to resource array
*
* Returns -EINVAL if the range cannot be converted to resource.
*
* Note that if your address is a PIO address, the conversion will fail if
* the physical address can't be internally converted to an IO token with
* pci_address_to_pio(), that is because it's either called too early or it
* can't be matched to any host bridge IO space
*/
int of_address_to_resource(struct device_node *dev, int index,
struct resource *r)
{
return __of_address_to_resource(dev, index, -1, r);
}
EXPORT_SYMBOL_GPL(of_address_to_resource);
int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r)
{
if (!IS_ENABLED(CONFIG_PCI))
return -ENOSYS;
return __of_address_to_resource(dev, -1, bar, r);
}
EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
/**
* of_iomap - Maps the memory mapped IO for a given device_node
* @np: the device whose io range will be mapped
* @index: index of the io range
*
* Returns a pointer to the mapped memory
*/
void __iomem *of_iomap(struct device_node *np, int index)
{
struct resource res;
if (of_address_to_resource(np, index, &res))
return NULL;
if (res.flags & IORESOURCE_MEM_NONPOSTED)
return ioremap_np(res.start, resource_size(&res));
else
return ioremap(res.start, resource_size(&res));
}
EXPORT_SYMBOL(of_iomap);
/*
* of_io_request_and_map - Requests a resource and maps the memory mapped IO
* for a given device_node
* @device: the device whose io range will be mapped
* @index: index of the io range
* @name: name "override" for the memory region request or NULL
*
* Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded
* error code on failure. Usage example:
*
* base = of_io_request_and_map(node, 0, "foo");
* if (IS_ERR(base))
* return PTR_ERR(base);
*/
void __iomem *of_io_request_and_map(struct device_node *np, int index,
const char *name)
{
struct resource res;
void __iomem *mem;
if (of_address_to_resource(np, index, &res))
return IOMEM_ERR_PTR(-EINVAL);
if (!name)
name = res.name;
if (!request_mem_region(res.start, resource_size(&res), name))
return IOMEM_ERR_PTR(-EBUSY);
if (res.flags & IORESOURCE_MEM_NONPOSTED)
mem = ioremap_np(res.start, resource_size(&res));
else
mem = ioremap(res.start, resource_size(&res));
if (!mem) {
release_mem_region(res.start, resource_size(&res));
return IOMEM_ERR_PTR(-ENOMEM);
}
return mem;
}
EXPORT_SYMBOL(of_io_request_and_map);
drivers/of/unittest.c
View file @ d42b1c47
......@@ -1529,13 +1529,12 @@ static int unittest_probe(struct platform_device *pdev)
return 0;
}
static int unittest_remove(struct platform_device *pdev)
static void unittest_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
dev_dbg(dev, "%s for node @%pOF\n", __func__, np);
return 0;
}
static const struct of_device_id unittest_match[] = {
......@@ -1545,7 +1544,7 @@ static const struct of_device_id unittest_match[] = {
static struct platform_driver unittest_driver = {
.probe = unittest_probe,
.remove = unittest_remove,
.remove_new = unittest_remove,
.driver = {
.name = "unittest",
.of_match_table = of_match_ptr(unittest_match),
......@@ -1626,23 +1625,17 @@ static int unittest_gpio_probe(struct platform_device *pdev)
return ret;
}
static int unittest_gpio_remove(struct platform_device *pdev)
static void unittest_gpio_remove(struct platform_device *pdev)
{
struct unittest_gpio_dev *devptr = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
dev_dbg(dev, "%s for node @%pfw\n", __func__, devptr->chip.fwnode);
if (!devptr)
return -EINVAL;
if (devptr->chip.base != -1)
gpiochip_remove(&devptr->chip);
platform_set_drvdata(pdev, NULL);
kfree(devptr);
return 0;
}
static const struct of_device_id unittest_gpio_id[] = {
......@@ -1652,7 +1645,7 @@ static const struct of_device_id unittest_gpio_id[] = {
static struct platform_driver unittest_gpio_driver = {
.probe = unittest_gpio_probe,
.remove = unittest_gpio_remove,
.remove_new = unittest_gpio_remove,
.driver = {
.name = "unittest-gpio",
.of_match_table = of_match_ptr(unittest_gpio_id),
......@@ -2490,7 +2483,7 @@ static int unittest_i2c_bus_probe(struct platform_device *pdev)
return 0;
}
static int unittest_i2c_bus_remove(struct platform_device *pdev)
static void unittest_i2c_bus_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
......@@ -2498,8 +2491,6 @@ static int unittest_i2c_bus_remove(struct platform_device *pdev)
dev_dbg(dev, "%s for node @%pOF\n", __func__, np);
i2c_del_adapter(&std->adap);
return 0;
}
static const struct of_device_id unittest_i2c_bus_match[] = {
......@@ -2509,7 +2500,7 @@ static const struct of_device_id unittest_i2c_bus_match[] = {
static struct platform_driver unittest_i2c_bus_driver = {
.probe = unittest_i2c_bus_probe,
.remove = unittest_i2c_bus_remove,
.remove_new = unittest_i2c_bus_remove,
.driver = {
.name = "unittest-i2c-bus",
.of_match_table = of_match_ptr(unittest_i2c_bus_match),
......
include/dt-bindings/reset/stih415-resets.h deleted 100644 → 0
View file @ 6df969b7
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for the reset controller
* based peripheral powerdown requests on the STMicroelectronics
* STiH415 SoC.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
#define STIH415_EMISS_POWERDOWN 0
#define STIH415_NAND_POWERDOWN 1
#define STIH415_KEYSCAN_POWERDOWN 2
#define STIH415_USB0_POWERDOWN 3
#define STIH415_USB1_POWERDOWN 4
#define STIH415_USB2_POWERDOWN 5
#define STIH415_SATA0_POWERDOWN 6
#define STIH415_SATA1_POWERDOWN 7
#define STIH415_PCIE_POWERDOWN 8
#define STIH415_ETH0_SOFTRESET 0
#define STIH415_ETH1_SOFTRESET 1
#define STIH415_IRB_SOFTRESET 2
#define STIH415_USB0_SOFTRESET 3
#define STIH415_USB1_SOFTRESET 4
#define STIH415_USB2_SOFTRESET 5
#define STIH415_KEYSCAN_SOFTRESET 6
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
include/dt-bindings/reset/stih416-resets.h deleted 100644 → 0
View file @ 6df969b7
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for the reset controller
* based peripheral powerdown requests on the STMicroelectronics
* STiH416 SoC.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
#define STIH416_EMISS_POWERDOWN 0
#define STIH416_NAND_POWERDOWN 1
#define STIH416_KEYSCAN_POWERDOWN 2
#define STIH416_USB0_POWERDOWN 3
#define STIH416_USB1_POWERDOWN 4
#define STIH416_USB2_POWERDOWN 5
#define STIH416_USB3_POWERDOWN 6
#define STIH416_SATA0_POWERDOWN 7
#define STIH416_SATA1_POWERDOWN 8
#define STIH416_PCIE0_POWERDOWN 9
#define STIH416_PCIE1_POWERDOWN 10
#define STIH416_ETH0_SOFTRESET 0
#define STIH416_ETH1_SOFTRESET 1
#define STIH416_IRB_SOFTRESET 2
#define STIH416_USB0_SOFTRESET 3
#define STIH416_USB1_SOFTRESET 4
#define STIH416_USB2_SOFTRESET 5
#define STIH416_USB3_SOFTRESET 6
#define STIH416_SATA0_SOFTRESET 7
#define STIH416_SATA1_SOFTRESET 8
#define STIH416_PCIE0_SOFTRESET 9
#define STIH416_PCIE1_SOFTRESET 10
#define STIH416_AUD_DAC_SOFTRESET 11
#define STIH416_HDTVOUT_SOFTRESET 12
#define STIH416_VTAC_M_RX_SOFTRESET 13
#define STIH416_VTAC_A_RX_SOFTRESET 14
#define STIH416_SYNC_HD_SOFTRESET 15
#define STIH416_SYNC_SD_SOFTRESET 16
#define STIH416_BLITTER_SOFTRESET 17
#define STIH416_GPU_SOFTRESET 18
#define STIH416_VTAC_M_TX_SOFTRESET 19
#define STIH416_VTAC_A_TX_SOFTRESET 20
#define STIH416_VTG_AUX_SOFTRESET 21
#define STIH416_JPEG_DEC_SOFTRESET 22
#define STIH416_HVA_SOFTRESET 23
#define STIH416_COMPO_M_SOFTRESET 24
#define STIH416_COMPO_A_SOFTRESET 25
#define STIH416_VP8_DEC_SOFTRESET 26
#define STIH416_VTG_MAIN_SOFTRESET 27
#define STIH416_KEYSCAN_SOFTRESET 28
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
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