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Commit d48f1de2 authored by Ralf Baechle's avatar Ralf Baechle
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[MIPS] Remove EV96100 as previously announced. 

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 432bef2a
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Showing with 3 additions and 2414 deletions
Documentation/feature-removal-schedule.txt
View file @ d48f1de2
......@@ -217,14 +217,6 @@ Who: Nick Piggin <npiggin@suse.de>
---------------------------
What: Support for the MIPS EV96100 evaluation board
When: September 2006
Why: Does no longer build since at least November 15, 2003, apparently
no userbase left.
Who: Ralf Baechle <ralf@linux-mips.org>
---------------------------
What: Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board
When: September 2006
Why: Does no longer build since quite some time, and was never popular,
......
Documentation/kernel-parameters.txt
View file @ d48f1de2
......@@ -573,8 +573,6 @@ running once the system is up.
gscd= [HW,CD]
Format: <io>
gt96100eth= [NET] MIPS GT96100 Advanced Communication Controller
gus= [HW,OSS]
Format: <io>,<irq>,<dma>,<dma16>
......
arch/mips/Kconfig
View file @ d48f1de2
......@@ -203,26 +203,6 @@ config MIPS_EV64120
<http://www.marvell.com/>. Say Y here if you wish to build a
kernel for this platform.
config MIPS_EV96100
bool "Galileo EV96100 Evaluation board (EXPERIMENTAL)"
depends on EXPERIMENTAL
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select MIPS_GT96100
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_R5000
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_BIG_ENDIAN
help
This is an evaluation board based on the Galileo GT-96100 LAN/WAN
communications controllers containing a MIPS R5000 compatible core
running at 83MHz. Their website is <http://www.marvell.com/>. Say Y
here if you wish to build a kernel for this platform.
config MIPS_IVR
bool "Globespan IVR board"
select DMA_NONCOHERENT
......@@ -1069,10 +1049,6 @@ config AU1X00_USB_DEVICE
depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
default n
config MIPS_GT96100
bool
select MIPS_GT64120
config IT8172_CIR
bool
depends on MIPS_ITE8172 || MIPS_IVR
......
arch/mips/Makefile
View file @ d48f1de2
......@@ -279,13 +279,6 @@ core-$(CONFIG_MIPS_EV64120) += arch/mips/gt64120/common/
cflags-$(CONFIG_MIPS_EV64120) += -Iinclude/asm-mips/mach-ev64120
load-$(CONFIG_MIPS_EV64120) += 0xffffffff80100000
#
# Galileo EV96100 Board
#
core-$(CONFIG_MIPS_EV96100) += arch/mips/galileo-boards/ev96100/
cflags-$(CONFIG_MIPS_EV96100) += -Iinclude/asm-mips/mach-ev96100
load-$(CONFIG_MIPS_EV96100) += 0xffffffff80100000
#
# Wind River PPMC Board (4KC + GT64120)
#
......
arch/mips/configs/atlas_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/bigsur_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/capcella_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/cobalt_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
CONFIG_MIPS_COBALT=y
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/db1000_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/db1100_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/db1200_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/db1500_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/db1550_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ddb5477_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/decstation_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MACH_DECSTATION=y
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/e55_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/emma2rh_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ev64120_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
CONFIG_MIPS_EV64120=y
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ev96100_defconfig deleted 100644 → 0
View file @ 432bef2a
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.18-rc1
# Thu Jul 6 10:04:05 2006
#
CONFIG_MIPS=y
#
# Machine selection
#
# CONFIG_MIPS_MTX1 is not set
# CONFIG_MIPS_BOSPORUS is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_MIPS_PB1100 is not set
# CONFIG_MIPS_PB1500 is not set
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_PB1200 is not set
# CONFIG_MIPS_DB1000 is not set
# CONFIG_MIPS_DB1100 is not set
# CONFIG_MIPS_DB1500 is not set
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
CONFIG_MIPS_EV96100=y
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_LASAT is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_MIPS_GT64120=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_MIPS_GT96100=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
CONFIG_CPU_RM7000=y
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_R5000=y
CONFIG_SYS_HAS_CPU_RM7000=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
#
# Kernel type
#
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_BOARD_SCACHE=y
CONFIG_RM7000_CPU_SCACHE=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_HZ_48 is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_128 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_256 is not set
CONFIG_HZ_1000=y
# CONFIG_HZ_1024 is not set
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_HZ=1000
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_RELAY=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_RT_MUTEXES=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_KMOD is not set
#
# Block layer
#
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_HW_HAS_PCI=y
# CONFIG_PCI is not set
CONFIG_MMU=y
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# PCI Hotplug Support
#
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_TRAD_SIGNALS=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
# CONFIG_PACKET is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
CONFIG_NETWORK_SECMARK=y
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_IEEE80211=m
# CONFIG_IEEE80211_DEBUG is not set
CONFIG_IEEE80211_CRYPT_WEP=m
CONFIG_IEEE80211_CRYPT_CCMP=m
CONFIG_IEEE80211_SOFTMAC=m
# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
CONFIG_WIRELESS_EXT=y
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
CONFIG_CONNECTOR=m
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
CONFIG_ATA_OVER_ETH=m
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_RAID_ATTRS=m
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# PHY device support
#
CONFIG_PHYLIB=m
#
# MII PHY device drivers
#
CONFIG_MARVELL_PHY=m
CONFIG_DAVICOM_PHY=m
CONFIG_QSEMI_PHY=m
CONFIG_LXT_PHY=m
CONFIG_CICADA_PHY=m
CONFIG_VITESSE_PHY=m
CONFIG_SMSC_PHY=m
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
CONFIG_MIPS_GT96100ETH=y
# CONFIG_DM9000 is not set
#
# Ethernet (1000 Mbit)
#
#
# Ethernet (10000 Mbit)
#
#
# Token Ring devices
#
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_LIBPS2 is not set
CONFIG_SERIO_RAW=m
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Misc devices
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
CONFIG_VIDEO_V4L2=y
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB_ARCH_HAS_HCD is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=m
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_FS is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_DEBUG_PROC_KEYS=y
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
CONFIG_CRYPTO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=m
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_CRC32C=m
# CONFIG_CRYPTO_TEST is not set
#
# Hardware crypto devices
#
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=m
CONFIG_CRC32=m
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=m
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
arch/mips/configs/excite_defconfig
View file @ d48f1de2
......@@ -26,7 +26,6 @@ CONFIG_BASLER_EXCITE=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ip22_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ip27_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ip32_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/it8172_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
CONFIG_MIPS_ITE8172=y
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ivr_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
CONFIG_MIPS_IVR=y
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/jaguar-atx_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/jmr3927_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/lasat200_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/malta_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/mipssim_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/mpc30x_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ocelot_3_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ocelot_c_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ocelot_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/ocelot_g_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/pb1100_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/pb1500_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/pb1550_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/pnx8550-jbs_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/pnx8550-v2pci_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/qemu_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/rbhma4500_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/rm200_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/sb1250-swarm_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/sead_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/tb0226_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/tb0229_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/tb0287_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/workpad_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/wrppmc_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/configs/yosemite_defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/defconfig
View file @ d48f1de2
......@@ -25,7 +25,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
......
arch/mips/galileo-boards/ev96100/Makefile deleted 100644 → 0
View file @ 432bef2a
#
# Copyright 2000 MontaVista Software Inc.
# Author: MontaVista Software, Inc.
# ppopov@mvista.com or source@mvista.com
#
# Makefile for the Galileo EV96100 board.
#
obj-y += init.o irq.o puts.o reset.o time.o setup.o
arch/mips/galileo-boards/ev96100/init.c deleted 100644 → 0
View file @ 432bef2a
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/generic/generic.c
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/gt64120.h>
/* Environment variable */
typedef struct {
char *name;
char *val;
} t_env_var;
int prom_argc;
char **prom_argv, **prom_envp;
int init_debug = 0;
char * __init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
unsigned long __init prom_free_prom_memory(void)
{
return 0;
}
void __init prom_init_cmdline(void)
{
char *cp;
int actr;
actr = 1; /* Always ignore argv[0] */
cp = &(arcs_cmdline[0]);
while(actr < prom_argc) {
strcpy(cp, prom_argv[actr]);
cp += strlen(prom_argv[actr]);
*cp++ = ' ';
actr++;
}
if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
--cp;
*cp = '\0';
}
char *prom_getenv(char *envname)
{
/*
* Return a pointer to the given environment variable.
*/
t_env_var *env = (t_env_var *) prom_envp;
int i;
i = strlen(envname);
while (env->name) {
if (strncmp(envname, env->name, i) == 0) {
return (env->val);
}
env++;
}
return (NULL);
}
static inline unsigned char str2hexnum(unsigned char c)
{
if (c >= '0' && c <= '9')
return c - '0';
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return 0; /* foo */
}
static inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
int i;
for (i = 0; i < 6; i++) {
unsigned char num;
if ((*str == '.') || (*str == ':'))
str++;
num = str2hexnum(*str++) << 4;
num |= (str2hexnum(*str++));
ea[i] = num;
}
}
int get_ethernet_addr(char *ethernet_addr)
{
char *ethaddr_str;
ethaddr_str = prom_getenv("ethaddr");
if (!ethaddr_str) {
printk("ethaddr not set in boot prom\n");
return -1;
}
str2eaddr(ethernet_addr, ethaddr_str);
if (init_debug > 1) {
int i;
printk("get_ethernet_addr: ");
for (i = 0; i < 5; i++)
printk("%02x:",
(unsigned char) *(ethernet_addr + i));
printk("%02x\n", *(ethernet_addr + i));
}
return 0;
}
const char *get_system_type(void)
{
return "Galileo EV96100";
}
void __init prom_init(void)
{
volatile unsigned char *uart;
char ppbuf[8];
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_GALILEO;
mips_machtype = MACH_EV96100;
prom_init_cmdline();
/* 32 MB upgradable */
add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
}
arch/mips/galileo-boards/ev96100/irq.c deleted 100644 → 0
View file @ 432bef2a
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/atlas/atlas_int.c.
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <asm/irq_cpu.h>
static inline unsigned int ffz8(unsigned int word)
{
unsigned long k;
k = 7;
if (word & 0x0fUL) { k -= 4; word <<= 4; }
if (word & 0x30UL) { k -= 2; word <<= 2; }
if (word & 0x40UL) { k -= 1; }
return k;
}
extern void mips_timer_interrupt(struct pt_regs *regs);
asmlinkage void ev96100_cpu_irq(unsigned int pending, struct pt_regs *regs)
{
do_IRQ(ffz8(pending >> 8), regs);
}
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & CAUSEF_IP7)
mips_timer_interrupt(regs);
else if (pending)
ev96100_cpu_irq(pending, regs);
else
spurious_interrupt(regs);
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init(0);
}
arch/mips/galileo-boards/ev96100/puts.c deleted 100644 → 0
View file @ 432bef2a
/*
* Debug routines which directly access the uart.
*/
#include <linux/types.h>
#include <asm/gt64120.h>
//#define SERIAL_BASE EV96100_UART0_REGS_BASE
#define SERIAL_BASE 0xBD000020
#define NS16550_BASE SERIAL_BASE
#define SERA_CMD 0x0D
#define SERA_DATA 0x08
//#define SERB_CMD 0x05
#define SERB_CMD 20
#define SERB_DATA 0x00
#define TX_BUSY 0x20
#define TIMEOUT 0xffff
#undef SLOW_DOWN
static const char digits[16] = "0123456789abcdef";
static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
#ifdef SLOW_DOWN
static inline void slow_down()
{
int k;
for (k = 0; k < 10000; k++);
}
#else
#define slow_down()
#endif
void putch(const unsigned char c)
{
unsigned char ch;
int i = 0;
do {
ch = com1[SERB_CMD];
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SERB_DATA] = c;
}
void putchar(const unsigned char c)
{
unsigned char ch;
int i = 0;
do {
ch = com1[SERB_CMD];
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SERB_DATA] = c;
}
void puts(unsigned char *cp)
{
unsigned char ch;
int i = 0;
while (*cp) {
do {
ch = com1[SERB_CMD];
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SERB_DATA] = *cp++;
}
putch('\r');
putch('\n');
}
void fputs(unsigned char *cp)
{
unsigned char ch;
int i = 0;
while (*cp) {
do {
ch = com1[SERB_CMD];
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SERB_DATA] = *cp++;
}
}
void put64(uint64_t ul)
{
int cnt;
unsigned ch;
cnt = 16; /* 16 nibbles in a 64 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
void put32(unsigned u)
{
int cnt;
unsigned ch;
cnt = 8; /* 8 nibbles in a 32 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char) (u >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
arch/mips/galileo-boards/ev96100/reset.c deleted 100644 → 0
View file @ 432bef2a
/*
* BRIEF MODULE DESCRIPTION
* Galileo EV96100 reset routines.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/generic/reset.c
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/gt64120.h>
static void mips_machine_restart(char *command);
static void mips_machine_halt(void);
static void mips_machine_restart(char *command)
{
set_c0_status(ST0_BEV | ST0_ERL);
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_c0_wired(0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
while (1);
}
static void mips_machine_halt(void)
{
printk(KERN_NOTICE "You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void mips_reboot_setup(void)
{
_machine_restart = mips_machine_restart;
_machine_halt = mips_machine_halt;
}
arch/mips/galileo-boards/ev96100/setup.c deleted 100644 → 0
View file @ 432bef2a
/*
* BRIEF MODULE DESCRIPTION
* Galileo EV96100 setup.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/atlas/atlas_setup.c.
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/pci.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/irq.h>
#include <asm/delay.h>
#include <asm/gt64120.h>
#include <asm/galileo-boards/ev96100int.h>
extern char *__init prom_getcmdline(void);
extern void mips_reboot_setup(void);
unsigned char mac_0_1[12];
void __init plat_mem_setup(void)
{
unsigned int config = read_c0_config();
unsigned int status = read_c0_status();
unsigned int info = read_c0_info();
u32 tmp;
char *argptr;
clear_c0_status(ST0_FR);
if (config & 0x8)
printk("Secondary cache is enabled\n");
else
printk("Secondary cache is disabled\n");
if (status & (1 << 27))
printk("User-mode cache ops enabled\n");
else
printk("User-mode cache ops disabled\n");
printk("CP0 info reg: %x\n", (unsigned) info);
if (info & (1 << 28))
printk("burst mode Scache RAMS\n");
else
printk("pipelined Scache RAMS\n");
if (info & 0x1)
printk("Atomic Enable is set\n");
argptr = prom_getcmdline();
#ifdef CONFIG_SERIAL_CONSOLE
if (strstr(argptr, "console=") == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
}
#endif
mips_reboot_setup();
set_io_port_base(KSEG1);
ioport_resource.start = GT_PCI_IO_BASE;
ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff;
#ifdef CONFIG_BLK_DEV_INITRD
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
#endif
/*
* Setup GT controller master bit so we can do config cycles
*/
/* Clear cause register bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
udelay(2);
tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
udelay(2);
GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
udelay(2);
tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
}
unsigned short get_gt_devid(void)
{
u32 gt_devid;
/* Figure out if this is a gt96100 or gt96100A */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
udelay(4);
gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS);
return gt_devid >> 16;
}
arch/mips/galileo-boards/ev96100/time.c deleted 100644 → 0
View file @ 432bef2a
/*
* BRIEF MODULE DESCRIPTION
* Galileo EV96100 rtc routines.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/atlas/atlas_rtc.c.
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/timex.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/time.h>
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
extern volatile unsigned long wall_jiffies;
unsigned long missed_heart_beats = 0;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
static inline void ack_r4ktimer(unsigned long newval)
{
write_c0_compare(newval);
}
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
* handler floating around. This one is rather different, but the algorithm
* is probably more robust.
*/
void mips_timer_interrupt(struct pt_regs *regs)
{
int irq = 7; /* FIX ME */
if (r4k_offset == 0) {
goto null;
}
do {
kstat_this_cpu.irqs[irq]++;
do_timer(regs);
#ifndef CONFIG_SMP
update_process_times(user_mode(regs));
#endif
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
} while (((unsigned long)read_c0_count()
- r4k_cur) < 0x7fffffff);
return;
null:
ack_r4ktimer(0);
}
arch/mips/pci/Makefile
View file @ d48f1de2
......@@ -11,7 +11,6 @@ obj-$(CONFIG_ITE_BOARD_GEN) += ops-it8172.o
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o
obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
obj-$(CONFIG_MIPS_GT96100) += ops-gt96100.o
obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
......@@ -29,7 +28,6 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o
obj-$(CONFIG_MIPS_EV96100) += fixup-ev96100.o pci-ev96100.o
obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o
obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o
obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
......
arch/mips/pci/fixup-ev96100.c deleted 100644 → 0
View file @ 432bef2a
/*
*
* BRIEF MODULE DESCRIPTION
* EV96100 Board specific pci fixups.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
static char irq_tab_ev96100[][5] __initdata = {
[8] = { 0, 5, 5, 5, 5 },
[9] = { 0, 2, 2, 2, 2 }
};
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
return irq_tab_ev96100[slot][pin];
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
arch/mips/pci/ops-gt96100.c deleted 100644 → 0
View file @ 432bef2a
/*
*
* BRIEF MODULE DESCRIPTION
* Galileo EV96100 board specific pci support.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/generic/pci.c
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/delay.h>
#include <asm/gt64120.h>
#include <asm/galileo-boards/ev96100.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static int static gt96100_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
{
unsigned char bus = bus->number;
u32 intr;
/*
* Because of a bug in the galileo (for slot 31).
*/
if (bus == 0 && devfn >= PCI_DEVFN(31, 0))
return PCIBIOS_DEVICE_NOT_FOUND;
/* Clear cause register bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
udelay(2);
if (access_type == PCI_ACCESS_WRITE) {
if (devfn != 0)
*data = le32_to_cpu(*data);
GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else {
*data = GT_READ(GT_PCI0_CFGDATA_OFS);
if (devfn != 0)
*data = le32_to_cpu(*data);
}
udelay(2);
/* Check for master or target abort */
intr = GT_READ(GT_INTRCAUSE_OFS);
if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
/* Error occured */
/* Clear bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
return -1;
}
return 0;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int gt96100_pcibios_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
u32 data = 0;
if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
switch (size) {
case 1:
*val = (data >> ((where & 3) << 3)) & 0xff;
break;
case 2:
*val = (data >> ((where & 3) << 3)) & 0xffff;
break;
case 4:
*val = data;
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int gt96100_pcibios_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
u32 data = 0;
switch (size) {
case 1:
if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (gt96100_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
case 2:
if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
case 4:
if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val))
return -1;
return PCIBIOS_SUCCESSFUL;
}
}
struct pci_ops gt96100_pci_ops = {
.read = gt96100_pcibios_read,
.write = gt96100_pcibios_write
};
arch/mips/pci/pci-ev96100.c deleted 100644 → 0
View file @ 432bef2a
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
static struct resource pci_io_resource = {
.name = "io pci IO space",
.start = 0x10000000,
.end = 0x11ffffff,
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.name = "ext pci memory space",
.start = 0x12000000,
.end = 0x13ffffff,
.flags = IORESOURCE_MEM
};
extern struct pci_ops gt96100_pci_ops;
struct pci_controller ev96100_controller = {
.pci_ops = &gt96100_pci_ops,
.io_resource = &pci_io_resource,
.mem_resource = &pci_mem_resource,
};
static void ev96100_pci_init(void)
{
register_pci_controller(&ev96100_controller);
}
arch_initcall(ev96100_pci_init);
include/asm-mips/bootinfo.h
View file @ d48f1de2
......@@ -112,8 +112,7 @@
* Valid machtype for group GALILEO
*/
#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */
#define MACH_EV96100 0 /* EV96100 */
#define MACH_EV64120A 1 /* EV64120A */
#define MACH_EV64120A 0 /* EV64120A */
/*
* Valid machtype for group MOMENCO
......
include/asm-mips/galileo-boards/gt96100.h deleted 100644 → 0
View file @ 432bef2a
/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Register offsets of the MIPS GT96100 Advanced Communication Controller.
*/
#ifndef _GT96100_H
#define _GT96100_H
/*
* Galileo GT96100 internal register base.
*/
#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
#define GT96100_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
#define GT96100_READ(ofs) \
le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
#define GT96100_ETH_IO_SIZE 0x4000
/************************************************************************
* Register offset addresses follow
************************************************************************/
/* CPU Interface Control Registers */
#define GT96100_CPU_INTERF_CONFIG 0x000000
/* Ethernet Ports */
#define GT96100_ETH_PHY_ADDR_REG 0x080800
#define GT96100_ETH_SMI_REG 0x080810
/*
These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to
get offsets to port 1 registers.
*/
#define GT96100_ETH_PORT_CONFIG 0x084800
#define GT96100_ETH_PORT_CONFIG_EXT 0x084808
#define GT96100_ETH_PORT_COMM 0x084810
#define GT96100_ETH_PORT_STATUS 0x084818
#define GT96100_ETH_SER_PARAM 0x084820
#define GT96100_ETH_HASH_TBL_PTR 0x084828
#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830
#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838
#define GT96100_ETH_SDMA_CONFIG 0x084840
#define GT96100_ETH_SDMA_COMM 0x084848
#define GT96100_ETH_INT_CAUSE 0x084850
#define GT96100_ETH_INT_MASK 0x084858
#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880
#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884
#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888
#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C
#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0
#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4
#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8
#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC
#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0
#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4
#define GT96100_ETH_MIB_COUNT_BASE 0x085800
/* SDMAs */
#define GT96100_SDMA_GROUP_CONFIG 0x101AF0
/* SDMA Group 0 */
#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900
#define GT96100_SDMA_G0_CHAN0_COMM 0x000908
#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900
#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910
#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900
#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910
#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914
#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900
#define GT96100_SDMA_G0_CHAN1_COMM 0x010908
#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900
#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910
#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900
#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910
#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914
#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900
#define GT96100_SDMA_G0_CHAN2_COMM 0x020908
#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900
#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910
#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900
#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910
#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914
#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900
#define GT96100_SDMA_G0_CHAN3_COMM 0x030908
#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900
#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910
#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900
#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910
#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914
#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900
#define GT96100_SDMA_G0_CHAN4_COMM 0x040908
#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900
#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910
#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900
#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910
#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914
#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900
#define GT96100_SDMA_G0_CHAN5_COMM 0x050908
#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900
#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910
#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900
#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910
#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914
#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900
#define GT96100_SDMA_G0_CHAN6_COMM 0x060908
#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900
#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910
#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900
#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910
#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914
#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900
#define GT96100_SDMA_G0_CHAN7_COMM 0x070908
#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900
#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910
#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900
#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910
#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914
/* SDMA Group 1 */
#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900
#define GT96100_SDMA_G1_CHAN0_COMM 0x100908
#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900
#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910
#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900
#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910
#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914
#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900
#define GT96100_SDMA_G1_CHAN1_COMM 0x110908
#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900
#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910
#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900
#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910
#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914
#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900
#define GT96100_SDMA_G1_CHAN2_COMM 0x120908
#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900
#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910
#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900
#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910
#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914
#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900
#define GT96100_SDMA_G1_CHAN3_COMM 0x130908
#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900
#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910
#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900
#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910
#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914
#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900
#define GT96100_SDMA_G1_CHAN4_COMM 0x140908
#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900
#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910
#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900
#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910
#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914
#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900
#define GT96100_SDMA_G1_CHAN5_COMM 0x150908
#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900
#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910
#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900
#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910
#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914
#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900
#define GT96100_SDMA_G1_CHAN6_COMM 0x160908
#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900
#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910
#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900
#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910
#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914
#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900
#define GT96100_SDMA_G1_CHAN7_COMM 0x170908
#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900
#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910
#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900
#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910
#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914
/* MPSCs */
#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00
#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04
#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08
#define GT96100_MPSC_CHAN0_REG1 0x000A0C
#define GT96100_MPSC_CHAN0_REG2 0x000A10
#define GT96100_MPSC_CHAN0_REG3 0x000A14
#define GT96100_MPSC_CHAN0_REG4 0x000A18
#define GT96100_MPSC_CHAN0_REG5 0x000A1C
#define GT96100_MPSC_CHAN0_REG6 0x000A20
#define GT96100_MPSC_CHAN0_REG7 0x000A24
#define GT96100_MPSC_CHAN0_REG8 0x000A28
#define GT96100_MPSC_CHAN0_REG9 0x000A2C
#define GT96100_MPSC_CHAN0_REG10 0x000A30
#define GT96100_MPSC_CHAN0_REG11 0x000A34
#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00
#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04
#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08
#define GT96100_MPSC_CHAN1_REG1 0x008A0C
#define GT96100_MPSC_CHAN1_REG2 0x008A10
#define GT96100_MPSC_CHAN1_REG3 0x008A14
#define GT96100_MPSC_CHAN1_REG4 0x008A18
#define GT96100_MPSC_CHAN1_REG5 0x008A1C
#define GT96100_MPSC_CHAN1_REG6 0x008A20
#define GT96100_MPSC_CHAN1_REG7 0x008A24
#define GT96100_MPSC_CHAN1_REG8 0x008A28
#define GT96100_MPSC_CHAN1_REG9 0x008A2C
#define GT96100_MPSC_CHAN1_REG10 0x008A30
#define GT96100_MPSC_CHAN1_REG11 0x008A34
#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00
#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04
#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08
#define GT96100_MPSC_CHAN2_REG1 0x010A0C
#define GT96100_MPSC_CHAN2_REG2 0x010A10
#define GT96100_MPSC_CHAN2_REG3 0x010A14
#define GT96100_MPSC_CHAN2_REG4 0x010A18
#define GT96100_MPSC_CHAN2_REG5 0x010A1C
#define GT96100_MPSC_CHAN2_REG6 0x010A20
#define GT96100_MPSC_CHAN2_REG7 0x010A24
#define GT96100_MPSC_CHAN2_REG8 0x010A28
#define GT96100_MPSC_CHAN2_REG9 0x010A2C
#define GT96100_MPSC_CHAN2_REG10 0x010A30
#define GT96100_MPSC_CHAN2_REG11 0x010A34
#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00
#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04
#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08
#define GT96100_MPSC_CHAN3_REG1 0x018A0C
#define GT96100_MPSC_CHAN3_REG2 0x018A10
#define GT96100_MPSC_CHAN3_REG3 0x018A14
#define GT96100_MPSC_CHAN3_REG4 0x018A18
#define GT96100_MPSC_CHAN3_REG5 0x018A1C
#define GT96100_MPSC_CHAN3_REG6 0x018A20
#define GT96100_MPSC_CHAN3_REG7 0x018A24
#define GT96100_MPSC_CHAN3_REG8 0x018A28
#define GT96100_MPSC_CHAN3_REG9 0x018A2C
#define GT96100_MPSC_CHAN3_REG10 0x018A30
#define GT96100_MPSC_CHAN3_REG11 0x018A34
#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00
#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04
#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08
#define GT96100_MPSC_CHAN4_REG1 0x020A0C
#define GT96100_MPSC_CHAN4_REG2 0x020A10
#define GT96100_MPSC_CHAN4_REG3 0x020A14
#define GT96100_MPSC_CHAN4_REG4 0x020A18
#define GT96100_MPSC_CHAN4_REG5 0x020A1C
#define GT96100_MPSC_CHAN4_REG6 0x020A20
#define GT96100_MPSC_CHAN4_REG7 0x020A24
#define GT96100_MPSC_CHAN4_REG8 0x020A28
#define GT96100_MPSC_CHAN4_REG9 0x020A2C
#define GT96100_MPSC_CHAN4_REG10 0x020A30
#define GT96100_MPSC_CHAN4_REG11 0x020A34
#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00
#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04
#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08
#define GT96100_MPSC_CHAN5_REG1 0x028A0C
#define GT96100_MPSC_CHAN5_REG2 0x028A10
#define GT96100_MPSC_CHAN5_REG3 0x028A14
#define GT96100_MPSC_CHAN5_REG4 0x028A18
#define GT96100_MPSC_CHAN5_REG5 0x028A1C
#define GT96100_MPSC_CHAN5_REG6 0x028A20
#define GT96100_MPSC_CHAN5_REG7 0x028A24
#define GT96100_MPSC_CHAN5_REG8 0x028A28
#define GT96100_MPSC_CHAN5_REG9 0x028A2C
#define GT96100_MPSC_CHAN5_REG10 0x028A30
#define GT96100_MPSC_CHAN5_REG11 0x028A34
#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00
#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04
#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08
#define GT96100_MPSC_CHAN6_REG1 0x030A0C
#define GT96100_MPSC_CHAN6_REG2 0x030A10
#define GT96100_MPSC_CHAN6_REG3 0x030A14
#define GT96100_MPSC_CHAN6_REG4 0x030A18
#define GT96100_MPSC_CHAN6_REG5 0x030A1C
#define GT96100_MPSC_CHAN6_REG6 0x030A20
#define GT96100_MPSC_CHAN6_REG7 0x030A24
#define GT96100_MPSC_CHAN6_REG8 0x030A28
#define GT96100_MPSC_CHAN6_REG9 0x030A2C
#define GT96100_MPSC_CHAN6_REG10 0x030A30
#define GT96100_MPSC_CHAN6_REG11 0x030A34
#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00
#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04
#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08
#define GT96100_MPSC_CHAN7_REG1 0x038A0C
#define GT96100_MPSC_CHAN7_REG2 0x038A10
#define GT96100_MPSC_CHAN7_REG3 0x038A14
#define GT96100_MPSC_CHAN7_REG4 0x038A18
#define GT96100_MPSC_CHAN7_REG5 0x038A1C
#define GT96100_MPSC_CHAN7_REG6 0x038A20
#define GT96100_MPSC_CHAN7_REG7 0x038A24
#define GT96100_MPSC_CHAN7_REG8 0x038A28
#define GT96100_MPSC_CHAN7_REG9 0x038A2C
#define GT96100_MPSC_CHAN7_REG10 0x038A30
#define GT96100_MPSC_CHAN7_REG11 0x038A34
/* FlexTDMs */
/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00
#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00
#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00
#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00
/* RDPR0 - Receive Dual Port RAM. block size 0xff */
#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00
#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00
#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00
#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00
#define GT96100_FXTDM0_TX_READ_PTR 0x008B00
#define GT96100_FXTDM0_RX_READ_PTR 0x008B04
#define GT96100_FXTDM0_CONFIG 0x008B08
#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00
#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00
#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00
#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00
#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00
#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00
#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00
#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00
#define GT96100_FXTDM1_TX_READ_PTR 0x018B00
#define GT96100_FXTDM1_RX_READ_PTR 0x018B04
#define GT96100_FXTDM1_CONFIG 0x018B08
#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00
#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00
#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00
#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00
#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00
#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00
#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00
#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00
#define GT96100_FLTDM2_TX_READ_PTR 0x028B00
#define GT96100_FLTDM2_RX_READ_PTR 0x028B04
#define GT96100_FLTDM2_CONFIG 0x028B08
#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00
#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00
#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00
#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00
#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00
#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00
#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00
#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00
#define GT96100_FXTDM3_TX_READ_PTR 0x038B00
#define GT96100_FXTDM3_RX_READ_PTR 0x038B04
#define GT96100_FXTDM3_CONFIG 0x038B08
#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
/* Baud Rate Generators */
#define GT96100_BRG0_CONFIG 0x102A00
#define GT96100_BRG0_BAUD_TUNE 0x102A04
#define GT96100_BRG1_CONFIG 0x102A08
#define GT96100_BRG1_BAUD_TUNE 0x102A0C
#define GT96100_BRG2_CONFIG 0x102A10
#define GT96100_BRG2_BAUD_TUNE 0x102A14
#define GT96100_BRG3_CONFIG 0x102A18
#define GT96100_BRG3_BAUD_TUNE 0x102A1C
#define GT96100_BRG4_CONFIG 0x102A20
#define GT96100_BRG4_BAUD_TUNE 0x102A24
#define GT96100_BRG5_CONFIG 0x102A28
#define GT96100_BRG5_BAUD_TUNE 0x102A2C
#define GT96100_BRG6_CONFIG 0x102A30
#define GT96100_BRG6_BAUD_TUNE 0x102A34
#define GT96100_BRG7_CONFIG 0x102A38
#define GT96100_BRG7_BAUD_TUNE 0x102A3C
/* Routing Registers */
#define GT96100_ROUTE_MAIN 0x101A00
#define GT96100_ROUTE_RX_CLOCK 0x101A10
#define GT96100_ROUTE_TX_CLOCK 0x101A20
/* General Purpose Ports */
#define GT96100_GPP_CONFIG0 0x100A00
#define GT96100_GPP_CONFIG1 0x100A04
#define GT96100_GPP_CONFIG2 0x100A08
#define GT96100_GPP_CONFIG3 0x100A0C
#define GT96100_GPP_IO0 0x100A20
#define GT96100_GPP_IO1 0x100A24
#define GT96100_GPP_IO2 0x100A28
#define GT96100_GPP_IO3 0x100A2C
#define GT96100_GPP_DATA0 0x100A40
#define GT96100_GPP_DATA1 0x100A44
#define GT96100_GPP_DATA2 0x100A48
#define GT96100_GPP_DATA3 0x100A4C
#define GT96100_GPP_LEVEL0 0x100A60
#define GT96100_GPP_LEVEL1 0x100A64
#define GT96100_GPP_LEVEL2 0x100A68
#define GT96100_GPP_LEVEL3 0x100A6C
/* Watchdog */
#define GT96100_WD_CONFIG 0x101A80
#define GT96100_WD_VALUE 0x101A84
/* Communication Unit Arbiter */
#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
/* PCI Arbiters */
#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
/* CIU Arbiter */
#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
/* Interrupt Controller */
#define GT96100_MAIN_CAUSE 0x000C18
#define GT96100_INT0_MAIN_MASK 0x000C1C
#define GT96100_INT1_MAIN_MASK 0x000C24
#define GT96100_HIGH_CAUSE 0x000C98
#define GT96100_INT0_HIGH_MASK 0x000C9C
#define GT96100_INT1_HIGH_MASK 0x000CA4
#define GT96100_INT0_SELECT 0x000C70
#define GT96100_INT1_SELECT 0x000C74
#define GT96100_SERIAL_CAUSE 0x103A00
#define GT96100_SERINT0_MASK 0x103A80
#define GT96100_SERINT1_MASK 0x103A88
#endif /* _GT96100_H */
include/asm-mips/mach-ev96100/mach-gt64120.h deleted 100644 → 0
View file @ 432bef2a
/*
* This is a direct copy of the ev96100.h file, with a global
* search and replace. The numbers are the same.
*
* The reason I'm duplicating this is so that the 64120/96100
* defines won't be confusing in the source code.
*/
#ifndef _ASM_GT64120_EV96100_GT64120_DEP_H
#define _ASM_GT64120_EV96100_GT64120_DEP_H
/*
* GT96100 config space base address
*/
#define GT64120_BASE (KSEG1ADDR(0x14000000))
/*
* PCI Bus allocation
*
* (Guessing ...)
*/
#define GT_PCI_MEM_BASE 0x12000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x10000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
#define GT_ISA_IO_BASE PCI_IO_BASE
/*
* Duart I/O ports.
*/
#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20)
#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00)
/*
* EV96100 interrupt controller register base.
*/
#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* EV96100 UART register base.
*/
#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
#define EV96100_BASE_BAUD ( 3686400 / 16 )
#endif /* _ASM_GT64120_EV96100_GT64120_DEP_H */
include/asm-mips/serial.h
View file @ d48f1de2
......@@ -52,9 +52,9 @@
#endif
/*
* Both Galileo boards have the same UART mappings.
* Galileo EV64120 evaluation board
*/
#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
#ifdef CONFIG_MIPS_EV64120
#include <asm/galileo-boards/ev96100.h>
#include <asm/galileo-boards/ev96100int.h>
#define EV96100_SERIAL_PORT_DEFNS \
......
include/linux/pci_ids.h
View file @ d48f1de2
......@@ -1482,9 +1482,6 @@
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480
#define PCI_DEVICE_ID_MARVELL_GT96100 0x9652
#define PCI_DEVICE_ID_MARVELL_GT96100A 0x9653
#define PCI_VENDOR_ID_V3 0x11b0
#define PCI_DEVICE_ID_V3_V960 0x0001
......
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