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Commit d4ad24a0 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
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drm/amdgpu/jpeg: add JPEG multiple AIDs support 

Add JPEG multiple AIDs support.
Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e10ced4
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Showing with 227 additions and 153 deletions
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
View file @ d4ad24a0
...@@ -63,6 +63,8 @@ static int jpeg_v4_0_3_early_init(void *handle) ...@@ -63,6 +63,8 @@ static int jpeg_v4_0_3_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;
jpeg_v4_0_3_set_dec_ring_funcs(adev); jpeg_v4_0_3_set_dec_ring_funcs(adev);
jpeg_v4_0_3_set_irq_funcs(adev); jpeg_v4_0_3_set_irq_funcs(adev);
...@@ -80,12 +82,12 @@ static int jpeg_v4_0_3_sw_init(void *handle) ...@@ -80,12 +82,12 @@ static int jpeg_v4_0_3_sw_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
int i, r; int i, j, r;
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
/* JPEG TRAP */ /* JPEG TRAP */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
amdgpu_ih_srcid_jpeg[i], &adev->jpeg.inst->irq); amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
if (r) if (r)
return r; return r;
} }
...@@ -98,22 +100,27 @@ static int jpeg_v4_0_3_sw_init(void *handle) ...@@ -98,22 +100,27 @@ static int jpeg_v4_0_3_sw_init(void *handle)
if (r) if (r)
return r; return r;
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
ring = &adev->jpeg.inst->ring_dec[i]; if (adev->jpeg.harvest_config & (1 << i))
ring->use_doorbell = true; continue;
ring->vm_hub = AMDGPU_MMHUB0(0); for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; ring = &adev->jpeg.inst[i].ring_dec[j];
sprintf(ring->name, "jpeg_dec_%d", i); ring->use_doorbell = true;
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
AMDGPU_RING_PRIO_DEFAULT, NULL); ring->doorbell_index =
if (r) (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + j + 9 * i;
return r; sprintf(ring->name, "jpeg_dec_%d.%d", i, j);
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
adev->jpeg.internal.jpeg_pitch[i] = AMDGPU_RING_PRIO_DEFAULT, NULL);
regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; if (r)
adev->jpeg.inst->external.jpeg_pitch[i] = return r;
SOC15_REG_OFFSET1(JPEG, 0, regUVD_JRBC0_UVD_JRBC_SCRATCH0,
(i?(0x40 * i - 0xc80):0)); adev->jpeg.internal.jpeg_pitch[j] =
regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
adev->jpeg.inst[i].external.jpeg_pitch[j] =
SOC15_REG_OFFSET1(JPEG, i, regUVD_JRBC0_UVD_JRBC_SCRATCH0,
(j?(0x40 * j - 0xc80):0));
}
} }
return 0; return 0;
...@@ -149,22 +156,30 @@ static int jpeg_v4_0_3_sw_fini(void *handle) ...@@ -149,22 +156,30 @@ static int jpeg_v4_0_3_sw_fini(void *handle)
static int jpeg_v4_0_3_hw_init(void *handle) static int jpeg_v4_0_3_hw_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; struct amdgpu_ring *ring;
int i, r; int i, j, r;
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); if (adev->jpeg.harvest_config & (1 << i))
continue;
ring = adev->jpeg.inst[i].ring_dec;
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
ring = &adev->jpeg.inst->ring_dec[i];
if (ring->use_doorbell) if (ring->use_doorbell)
WREG32_SOC15_OFFSET(VCN, 0, regVCN_JPEG_DB_CTRL, adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
(ring->pipe?(ring->pipe - 0x15):0), (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * i,
ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | adev->jpeg.inst[i].aid_id);
VCN_JPEG_DB_CTRL__EN_MASK);
r = amdgpu_ring_test_helper(ring); for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
if (r) ring = &adev->jpeg.inst[i].ring_dec[j];
return r; if (ring->use_doorbell)
WREG32_SOC15_OFFSET(VCN, i, regVCN_JPEG_DB_CTRL,
(ring->pipe?(ring->pipe - 0x15):0),
ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
VCN_JPEG_DB_CTRL__EN_MASK);
r = amdgpu_ring_test_helper(ring);
if (r)
return r;
}
} }
DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
...@@ -233,48 +248,52 @@ static int jpeg_v4_0_3_resume(void *handle) ...@@ -233,48 +248,52 @@ static int jpeg_v4_0_3_resume(void *handle)
return r; return r;
} }
static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev) static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
{ {
uint32_t data; uint32_t data;
int i; int i;
data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL);
if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
else data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1));
} else {
data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
}
data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL, data);
data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE);
data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE, data);
} }
static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev) static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
{ {
uint32_t data; uint32_t data;
int i; int i;
data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL);
if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
else data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1);
} else {
data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
}
data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL, data);
data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE);
data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE, data);
} }
/** /**
...@@ -286,58 +305,63 @@ static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev) ...@@ -286,58 +305,63 @@ static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev)
*/ */
static int jpeg_v4_0_3_start(struct amdgpu_device *adev) static int jpeg_v4_0_3_start(struct amdgpu_device *adev)
{ {
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; struct amdgpu_ring *ring;
int i; int i, j;
WREG32_SOC15(JPEG, 0, regUVD_PGFSM_CONFIG, for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); if (adev->jpeg.harvest_config & (1 << i))
SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, continue;
UVD_PGFSM_STATUS__UVDJ_PWR_ON << WREG32_SOC15(JPEG, i, regUVD_PGFSM_CONFIG,
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); SOC15_WAIT_ON_RREG(JPEG, i, regUVD_PGFSM_STATUS,
UVD_PGFSM_STATUS__UVDJ_PWR_ON <<
/* disable anti hang mechanism */ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
/* disable anti hang mechanism */
/* JPEG disable CGC */ WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_POWER_STATUS), 0,
jpeg_v4_0_3_disable_clock_gating(adev); ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
/* MJPEG global tiling registers */ /* JPEG disable CGC */
WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX8_ADDR_CONFIG, jpeg_v4_0_3_disable_clock_gating(adev, i);
adev->gfx.config.gb_addr_config);
WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, /* MJPEG global tiling registers */
adev->gfx.config.gb_addr_config); WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX8_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
/* enable JMI channel */ WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX10_ADDR_CONFIG,
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, adev->gfx.config.gb_addr_config);
~UVD_JMI_CNTL__SOFT_RESET_MASK);
/* enable JMI channel */
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0,
unsigned int reg_offset = (i?(0x40 * i - 0xc80):0); ~UVD_JMI_CNTL__SOFT_RESET_MASK);
ring = &adev->jpeg.inst->ring_dec[i]; for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
/* enable System Interrupt for JRBC */
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), ring = &adev->jpeg.inst[i].ring_dec[j];
JPEG_SYS_INT_EN__DJRBC0_MASK << i,
~(JPEG_SYS_INT_EN__DJRBC0_MASK << i)); /* enable System Interrupt for JRBC */
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN),
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, reg_offset, 0); JPEG_SYS_INT_EN__DJRBC0_MASK << j,
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset, ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j));
(0x00000001L | 0x00000002L));
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, WREG32_SOC15_OFFSET(JPEG, i,
reg_offset, lower_32_bits(ring->gpu_addr)); regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, reg_offset, 0);
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset,
reg_offset, upper_32_bits(ring->gpu_addr)); (0x00000001L | 0x00000002L));
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR, reg_offset, 0); WREG32_SOC15_OFFSET(JPEG, i, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR, reg_offset, 0); reg_offset, lower_32_bits(ring->gpu_addr));
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset, WREG32_SOC15_OFFSET(JPEG, i, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
0x00000002L); reg_offset, upper_32_bits(ring->gpu_addr));
WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE, reg_offset, WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_RPTR, reg_offset, 0);
ring->ring_size / 4); WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_WPTR, reg_offset, 0);
ring->wptr = RREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR, WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset,
reg_offset); 0x00000002L);
WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_SIZE, reg_offset,
ring->ring_size / 4);
ring->wptr = RREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_WPTR,
reg_offset);
}
} }
return 0; return 0;
...@@ -352,24 +376,31 @@ static int jpeg_v4_0_3_start(struct amdgpu_device *adev) ...@@ -352,24 +376,31 @@ static int jpeg_v4_0_3_start(struct amdgpu_device *adev)
*/ */
static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) static int jpeg_v4_0_3_stop(struct amdgpu_device *adev)
{ {
/* reset JMI */ int i;
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
UVD_JMI_CNTL__SOFT_RESET_MASK, for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
~UVD_JMI_CNTL__SOFT_RESET_MASK); if (adev->jpeg.harvest_config & (1 << i))
continue;
jpeg_v4_0_3_enable_clock_gating(adev); /* reset JMI */
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL),
UVD_JMI_CNTL__SOFT_RESET_MASK,
~UVD_JMI_CNTL__SOFT_RESET_MASK);
/* enable anti hang mechanism */ jpeg_v4_0_3_enable_clock_gating(adev, i);
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
WREG32_SOC15(JPEG, 0, regUVD_PGFSM_CONFIG, /* enable anti hang mechanism */
2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_POWER_STATUS),
SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
UVD_PGFSM_STATUS__UVDJ_PWR_OFF << ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); WREG32_SOC15(JPEG, i, regUVD_PGFSM_CONFIG,
2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
SOC15_WAIT_ON_RREG(JPEG, i, regUVD_PGFSM_STATUS,
UVD_PGFSM_STATUS__UVDJ_PWR_OFF <<
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
}
return 0; return 0;
} }
...@@ -502,10 +533,28 @@ static void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, ...@@ -502,10 +533,28 @@ static void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0);
if (ring->adev->jpeg.inst[ring->me].aid_id) {
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
amdgpu_ring_write(ring, 0x4);
} else {
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
amdgpu_ring_write(ring, 0);
}
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
0, 0, PACKETJ_TYPE0)); 0, 0, PACKETJ_TYPE0));
amdgpu_ring_write(ring, 0x3fbc); amdgpu_ring_write(ring, 0x3fbc);
if (ring->adev->jpeg.inst[ring->me].aid_id) {
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
amdgpu_ring_write(ring, 0x0);
} else {
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
amdgpu_ring_write(ring, 0);
}
amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0, 0, PACKETJ_TYPE0)); 0, 0, PACKETJ_TYPE0));
amdgpu_ring_write(ring, 0x1); amdgpu_ring_write(ring, 0x1);
...@@ -651,15 +700,19 @@ static bool jpeg_v4_0_3_is_idle(void *handle) ...@@ -651,15 +700,19 @@ static bool jpeg_v4_0_3_is_idle(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool ret; bool ret;
int i; int i, j;
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
unsigned int reg_offset = (i?(0x40 * i - 0xc80):0); if (adev->jpeg.harvest_config & (1 << i))
continue;
ret &= ((RREG32_SOC15_OFFSET(JPEG, 0, for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset) & unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); ret &= ((RREG32_SOC15_OFFSET(JPEG, i,
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset) &
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
}
} }
return ret; return ret;
...@@ -669,17 +722,20 @@ static int jpeg_v4_0_3_wait_for_idle(void *handle) ...@@ -669,17 +722,20 @@ static int jpeg_v4_0_3_wait_for_idle(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret; int ret;
int i; int i, j;
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
unsigned int reg_offset = (i?(0x40 * i - 0xc80):0); if (adev->jpeg.harvest_config & (1 << i))
continue;
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, 0, ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, i,
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset,
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
}
} }
return ret; return ret;
} }
...@@ -688,15 +744,19 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle, ...@@ -688,15 +744,19 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false; bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
if (enable) { for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (!jpeg_v4_0_3_is_idle(handle)) if (adev->jpeg.harvest_config & (1 << i))
return -EBUSY; continue;
jpeg_v4_0_3_enable_clock_gating(adev); if (enable) {
} else { if (!jpeg_v4_0_3_is_idle(handle))
jpeg_v4_0_3_disable_clock_gating(adev); return -EBUSY;
jpeg_v4_0_3_enable_clock_gating(adev, i);
} else {
jpeg_v4_0_3_disable_clock_gating(adev, i);
}
} }
return 0; return 0;
} }
...@@ -732,32 +792,35 @@ static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, ...@@ -732,32 +792,35 @@ static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source, struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry) struct amdgpu_iv_entry *entry)
{ {
uint32_t i;
i = node_id_to_phys_map[entry->node_id];
DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n");
switch (entry->src_id) { switch (entry->src_id) {
case VCN_4_0__SRCID__JPEG_DECODE: case VCN_4_0__SRCID__JPEG_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[0]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[0]);
break; break;
case VCN_4_0__SRCID__JPEG1_DECODE: case VCN_4_0__SRCID__JPEG1_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[1]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[1]);
break; break;
case VCN_4_0__SRCID__JPEG2_DECODE: case VCN_4_0__SRCID__JPEG2_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[2]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[2]);
break; break;
case VCN_4_0__SRCID__JPEG3_DECODE: case VCN_4_0__SRCID__JPEG3_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[3]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[3]);
break; break;
case VCN_4_0__SRCID__JPEG4_DECODE: case VCN_4_0__SRCID__JPEG4_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[4]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[4]);
break; break;
case VCN_4_0__SRCID__JPEG5_DECODE: case VCN_4_0__SRCID__JPEG5_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[5]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[5]);
break; break;
case VCN_4_0__SRCID__JPEG6_DECODE: case VCN_4_0__SRCID__JPEG6_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[6]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[6]);
break; break;
case VCN_4_0__SRCID__JPEG7_DECODE: case VCN_4_0__SRCID__JPEG7_DECODE:
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[7]); amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[7]);
break; break;
default: default:
DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
...@@ -798,7 +861,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { ...@@ -798,7 +861,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */
18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
8 + 16, 8 + 16,
.emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */
.emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
...@@ -819,12 +882,17 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { ...@@ -819,12 +882,17 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)
{ {
int i; int i, j;
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
adev->jpeg.inst->ring_dec[i].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; if (adev->jpeg.harvest_config & (1 << i))
adev->jpeg.inst->ring_dec[i].me = 0; continue;
adev->jpeg.inst->ring_dec[i].pipe = i; for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;
adev->jpeg.inst[i].ring_dec[j].me = i;
adev->jpeg.inst[i].ring_dec[j].pipe = j;
}
adev->jpeg.inst[i].aid_id = i / adev->jpeg.num_inst_per_aid;
} }
DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
} }
...@@ -836,7 +904,13 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { ...@@ -836,7 +904,13 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = {
static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
{ {
adev->jpeg.inst->irq.num_types = adev->jpeg.num_jpeg_rings; int i;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (adev->jpeg.harvest_config & (1 << i))
continue;
adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
}
adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;
} }
......
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