Commit d57cef91 authored by Mihai Caraman's avatar Mihai Caraman Committed by Alexander Graf

KVM: PPC: e500: Fix default tlb for victim hint

Tlb search operation used for victim hint relies on the default tlb set by the
host. When hardware tablewalk support is enabled in the host, the default tlb is
TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb
when searching for victim hint.
Signed-off-by: default avatarMihai Caraman <mihai.caraman@freescale.com>
Reviewed-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 9642382e
...@@ -40,7 +40,9 @@ ...@@ -40,7 +40,9 @@
/* MAS registers bit definitions */ /* MAS registers bit definitions */
#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) #define MAS0_TLBSEL_MASK 0x30000000
#define MAS0_TLBSEL_SHIFT 28
#define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK)
#define MAS0_ESEL_MASK 0x0FFF0000 #define MAS0_ESEL_MASK 0x0FFF0000
#define MAS0_ESEL_SHIFT 16 #define MAS0_ESEL_SHIFT 16
#define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK)
...@@ -86,6 +88,7 @@ ...@@ -86,6 +88,7 @@
#define MAS3_SPSIZE 0x0000003e #define MAS3_SPSIZE 0x0000003e
#define MAS3_SPSIZE_SHIFT 1 #define MAS3_SPSIZE_SHIFT 1
#define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK
#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
#define MAS4_INDD 0x00008000 /* Default IND */ #define MAS4_INDD 0x00008000 /* Default IND */
#define MAS4_TSIZED(x) MAS1_TSIZE(x) #define MAS4_TSIZED(x) MAS1_TSIZE(x)
......
...@@ -107,11 +107,15 @@ static u32 get_host_mas0(unsigned long eaddr) ...@@ -107,11 +107,15 @@ static u32 get_host_mas0(unsigned long eaddr)
{ {
unsigned long flags; unsigned long flags;
u32 mas0; u32 mas0;
u32 mas4;
local_irq_save(flags); local_irq_save(flags);
mtspr(SPRN_MAS6, 0); mtspr(SPRN_MAS6, 0);
mas4 = mfspr(SPRN_MAS4);
mtspr(SPRN_MAS4, mas4 & ~MAS4_TLBSEL_MASK);
asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET)); asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET));
mas0 = mfspr(SPRN_MAS0); mas0 = mfspr(SPRN_MAS0);
mtspr(SPRN_MAS4, mas4);
local_irq_restore(flags); local_irq_restore(flags);
return mas0; return mas0;
......
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