Commit d6014e77 authored by Shirish S's avatar Shirish S Committed by Alex Deucher

drm/amd/display: remove dummy is_blanked() to optimise boot time

is_blanked() hook is a dummy one for underlay pipe, hence
when called, it loops for ~300ms at boot.

This patch removes this dummy call and adds missing checks.
Signed-off-by: default avatarShirish S <shirish.s@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent db4b3797
......@@ -230,6 +230,9 @@ bool hwss_wait_for_blank_complete(
{
int counter;
/* Not applicable if the pipe is not primary, save 300ms of boot time */
if (!tg->funcs->is_blanked)
return true;
for (counter = 0; counter < 100; counter++) {
if (tg->funcs->is_blanked(tg))
break;
......
......@@ -53,7 +53,8 @@ void dce_pipe_control_lock(struct dc *dc,
struct dce_hwseq *hws = dc->hwseq;
/* Not lock pipe when blank */
if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
if (lock && pipe->stream_res.tg->funcs->is_blanked &&
pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
return;
val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
......
......@@ -648,12 +648,6 @@ static void dce110_timing_generator_v_disable_vga(
return;
}
static bool dce110_tg_v_is_blanked(struct timing_generator *tg)
{
/* Signal comes from the primary pipe, underlay is never blanked. */
return false;
}
/** ********************************************************************************************
*
* DCE11 Timing Generator Constructor / Destructor
......@@ -670,7 +664,6 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {
.set_early_control = dce110_timing_generator_v_set_early_control,
.wait_for_state = dce110_timing_generator_v_wait_for_state,
.set_blank = dce110_timing_generator_v_set_blank,
.is_blanked = dce110_tg_v_is_blanked,
.set_colors = dce110_timing_generator_v_set_colors,
.set_overscan_blank_color =
dce110_timing_generator_v_set_overscan_color_black,
......
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