Commit d6463345 authored by Minghuan Lian's avatar Minghuan Lian Committed by Bjorn Helgaas

PCI: layerscape: Factor out SCFG related function

For the LS1021a PCIe controller, some status registers are located in SCFG,
unlike other Layerscape devices.

Move SCFG-related code to ls1021_pcie_host_init() and rename
ls_pcie_link_up() to ls1021_pcie_link_up() because LTSSM status is also in
SCFG.
Signed-off-by: default avatarMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 7af4ce35
...@@ -34,6 +34,10 @@ ...@@ -34,6 +34,10 @@
/* Symbol Timer Register and Filter Mask Register 1 */ /* Symbol Timer Register and Filter Mask Register 1 */
#define PCIE_STRFMR1 0x71c #define PCIE_STRFMR1 0x71c
struct ls_pcie_drvdata {
struct pcie_host_ops *ops;
};
struct ls_pcie { struct ls_pcie {
struct list_head node; struct list_head node;
struct device *dev; struct device *dev;
...@@ -41,6 +45,7 @@ struct ls_pcie { ...@@ -41,6 +45,7 @@ struct ls_pcie {
void __iomem *dbi; void __iomem *dbi;
struct regmap *scfg; struct regmap *scfg;
struct pcie_port pp; struct pcie_port pp;
const struct ls_pcie_drvdata *drvdata;
int index; int index;
int msi_irq; int msi_irq;
}; };
...@@ -57,11 +62,14 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) ...@@ -57,11 +62,14 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
return header_type == PCI_HEADER_TYPE_BRIDGE; return header_type == PCI_HEADER_TYPE_BRIDGE;
} }
static int ls_pcie_link_up(struct pcie_port *pp) static int ls1021_pcie_link_up(struct pcie_port *pp)
{ {
u32 state; u32 state;
struct ls_pcie *pcie = to_ls_pcie(pp); struct ls_pcie *pcie = to_ls_pcie(pp);
if (!pcie->scfg)
return 0;
regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
...@@ -71,10 +79,25 @@ static int ls_pcie_link_up(struct pcie_port *pp) ...@@ -71,10 +79,25 @@ static int ls_pcie_link_up(struct pcie_port *pp)
return 1; return 1;
} }
static void ls_pcie_host_init(struct pcie_port *pp) static void ls1021_pcie_host_init(struct pcie_port *pp)
{ {
struct ls_pcie *pcie = to_ls_pcie(pp); struct ls_pcie *pcie = to_ls_pcie(pp);
u32 val; u32 val, index[2];
pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
"fsl,pcie-scfg");
if (IS_ERR(pcie->scfg)) {
dev_err(pp->dev, "No syscfg phandle specified\n");
pcie->scfg = NULL;
return;
}
if (of_property_read_u32_array(pp->dev->of_node,
"fsl,pcie-scfg", index, 2)) {
pcie->scfg = NULL;
return;
}
pcie->index = index[1];
dw_pcie_setup_rc(pp); dw_pcie_setup_rc(pp);
...@@ -87,11 +110,21 @@ static void ls_pcie_host_init(struct pcie_port *pp) ...@@ -87,11 +110,21 @@ static void ls_pcie_host_init(struct pcie_port *pp)
iowrite32(val, pcie->dbi + PCIE_STRFMR1); iowrite32(val, pcie->dbi + PCIE_STRFMR1);
} }
static struct pcie_host_ops ls_pcie_host_ops = { static struct pcie_host_ops ls1021_pcie_host_ops = {
.link_up = ls_pcie_link_up, .link_up = ls1021_pcie_link_up,
.host_init = ls_pcie_host_init, .host_init = ls1021_pcie_host_init,
};
static struct ls_pcie_drvdata ls1021_drvdata = {
.ops = &ls1021_pcie_host_ops,
}; };
static const struct of_device_id ls_pcie_of_match[] = {
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
{ },
};
MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
static int ls_add_pcie_port(struct ls_pcie *pcie) static int ls_add_pcie_port(struct ls_pcie *pcie)
{ {
struct pcie_port *pp; struct pcie_port *pp;
...@@ -101,7 +134,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) ...@@ -101,7 +134,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie)
pp->dev = pcie->dev; pp->dev = pcie->dev;
pp->dbi_base = pcie->dbi; pp->dbi_base = pcie->dbi;
pp->root_bus_nr = -1; pp->root_bus_nr = -1;
pp->ops = &ls_pcie_host_ops; pp->ops = pcie->drvdata->ops;
ret = dw_pcie_host_init(pp); ret = dw_pcie_host_init(pp);
if (ret) { if (ret) {
...@@ -114,11 +147,15 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) ...@@ -114,11 +147,15 @@ static int ls_add_pcie_port(struct ls_pcie *pcie)
static int __init ls_pcie_probe(struct platform_device *pdev) static int __init ls_pcie_probe(struct platform_device *pdev)
{ {
const struct of_device_id *match;
struct ls_pcie *pcie; struct ls_pcie *pcie;
struct resource *dbi_base; struct resource *dbi_base;
u32 index[2];
int ret; int ret;
match = of_match_device(ls_pcie_of_match, &pdev->dev);
if (!match)
return -ENODEV;
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie) if (!pcie)
return -ENOMEM; return -ENOMEM;
...@@ -132,18 +169,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) ...@@ -132,18 +169,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pcie->dbi); return PTR_ERR(pcie->dbi);
} }
pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, pcie->drvdata = match->data;
"fsl,pcie-scfg");
if (IS_ERR(pcie->scfg)) {
dev_err(&pdev->dev, "No syscfg phandle specified\n");
return PTR_ERR(pcie->scfg);
}
ret = of_property_read_u32_array(pdev->dev.of_node,
"fsl,pcie-scfg", index, 2);
if (ret)
return ret;
pcie->index = index[1];
if (!ls_pcie_is_bridge(pcie)) if (!ls_pcie_is_bridge(pcie))
return -ENODEV; return -ENODEV;
...@@ -157,12 +183,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) ...@@ -157,12 +183,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
return 0; return 0;
} }
static const struct of_device_id ls_pcie_of_match[] = {
{ .compatible = "fsl,ls1021a-pcie" },
{ },
};
MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
static struct platform_driver ls_pcie_driver = { static struct platform_driver ls_pcie_driver = {
.driver = { .driver = {
.name = "layerscape-pcie", .name = "layerscape-pcie",
......
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