Commit d75e2c9a authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull late MIPS fixes from Ralf Baechle:
 "This fixes a number of lose ends in the MIPS code and various bug
  fixes.

  Aside of dropping some patch that should not be in this pull request
  everything has sat in -next for quite a while and there are no known
  issues.

  The biggest patch in this patch set moves the allocation of an array
  that is aliased to a function (for runtime generated code) to
  assembler code.  This avoids an issue with certain toolchains when
  building for microMIPS."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (35 commits)
  MIPS: PCI: Move fixups from __init to __devinit.
  MIPS: Fix bug.h MIPS build regression
  MIPS: sync-r4k: remove redundant irq operation
  MIPS: smp: Warn on too early irq enable
  MIPS: call set_cpu_online() on cpu being brought up with irq disabled
  MIPS: call ->smp_finish() a little late
  MIPS: Yosemite: delay irq enable to ->smp_finish()
  MIPS: SMTC: delay irq enable to ->smp_finish()
  MIPS: BMIPS: delay irq enable to ->smp_finish()
  MIPS: Octeon: delay enable irq to ->smp_finish()
  MIPS: Oprofile: Fix build as a module.
  MIPS: BCM63XX: Fix BCM6368 IPSec clock bit
  MIPS: perf: Fix build error caused by unused counters_per_cpu_to_total()
  MIPS: Fix Magic SysRq L kernel crash.
  MIPS: BMIPS: Fix duplicate header inclusion.
  mips: mark const init data with __initconst instead of __initdata
  MIPS: cmpxchg.h: Add missing include
  MIPS: Malta may also be equipped with MIPS64 R2 processors.
  MIPS: Fix typo multipy -> multiply
  MIPS: Cavium: Fix duplicate ARCH_SPARSEMEM_ENABLE in kconfig.
  ...
parents 93517374 85a053fa
...@@ -288,6 +288,7 @@ config MIPS_MALTA ...@@ -288,6 +288,7 @@ config MIPS_MALTA
select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_MIPS64_R2
select SYS_HAS_CPU_NEVADA select SYS_HAS_CPU_NEVADA
select SYS_HAS_CPU_RM7000 select SYS_HAS_CPU_RM7000
select SYS_HAS_EARLY_PRINTK select SYS_HAS_EARLY_PRINTK
...@@ -1423,6 +1424,7 @@ config CPU_SB1 ...@@ -1423,6 +1424,7 @@ config CPU_SB1
config CPU_CAVIUM_OCTEON config CPU_CAVIUM_OCTEON
bool "Cavium Octeon processor" bool "Cavium Octeon processor"
depends on SYS_HAS_CPU_CAVIUM_OCTEON depends on SYS_HAS_CPU_CAVIUM_OCTEON
select ARCH_SPARSEMEM_ENABLE
select CPU_HAS_PREFETCH select CPU_HAS_PREFETCH
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SMP
......
...@@ -21,6 +21,7 @@ config BCM47XX_BCMA ...@@ -21,6 +21,7 @@ config BCM47XX_BCMA
select BCMA select BCMA
select BCMA_HOST_SOC select BCMA_HOST_SOC
select BCMA_DRIVER_MIPS select BCMA_DRIVER_MIPS
select BCMA_HOST_PCI if PCI
select BCMA_DRIVER_PCI_HOSTMODE if PCI select BCMA_DRIVER_PCI_HOSTMODE if PCI
default y default y
help help
......
...@@ -79,11 +79,11 @@ static int __init config_pcmcia_cs(unsigned int cs, ...@@ -79,11 +79,11 @@ static int __init config_pcmcia_cs(unsigned int cs,
return ret; return ret;
} }
static const __initdata struct { static const struct {
unsigned int cs; unsigned int cs;
unsigned int base; unsigned int base;
unsigned int size; unsigned int size;
} pcmcia_cs[3] = { } pcmcia_cs[3] __initconst = {
{ {
.cs = MPI_CS_PCMCIA_COMMON, .cs = MPI_CS_PCMCIA_COMMON,
.base = BCM_PCMCIA_COMMON_BASE_PA, .base = BCM_PCMCIA_COMMON_BASE_PA,
......
...@@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY ...@@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY
help help
Lock the kernel's implementation of memcpy() into L2. Lock the kernel's implementation of memcpy() into L2.
config ARCH_SPARSEMEM_ENABLE
def_bool y
select SPARSEMEM_STATIC
config IOMMU_HELPER config IOMMU_HELPER
bool bool
......
...@@ -185,7 +185,6 @@ static void __cpuinit octeon_init_secondary(void) ...@@ -185,7 +185,6 @@ static void __cpuinit octeon_init_secondary(void)
octeon_init_cvmcount(); octeon_init_cvmcount();
octeon_irq_setup_secondary(); octeon_irq_setup_secondary();
raw_local_irq_enable();
} }
/** /**
...@@ -233,6 +232,7 @@ static void octeon_smp_finish(void) ...@@ -233,6 +232,7 @@ static void octeon_smp_finish(void)
/* to generate the first CPU timer interrupt */ /* to generate the first CPU timer interrupt */
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
local_irq_enable();
} }
/** /**
......
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#ifndef __ASM_CMPXCHG_H #ifndef __ASM_CMPXCHG_H
#define __ASM_CMPXCHG_H #define __ASM_CMPXCHG_H
#include <linux/bug.h>
#include <linux/irqflags.h> #include <linux/irqflags.h>
#include <asm/war.h> #include <asm/war.h>
......
...@@ -94,6 +94,7 @@ ...@@ -94,6 +94,7 @@
#define PRID_IMP_24KE 0x9600 #define PRID_IMP_24KE 0x9600
#define PRID_IMP_74K 0x9700 #define PRID_IMP_74K 0x9700
#define PRID_IMP_1004K 0x9900 #define PRID_IMP_1004K 0x9900
#define PRID_IMP_M14KC 0x9c00
/* /*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
...@@ -260,12 +261,12 @@ enum cpu_type_enum { ...@@ -260,12 +261,12 @@ enum cpu_type_enum {
*/ */
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC,
/* /*
* MIPS64 class processors * MIPS64 class processors
*/ */
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
CPU_XLR, CPU_XLP, CPU_XLR, CPU_XLP,
...@@ -288,7 +289,7 @@ enum cpu_type_enum { ...@@ -288,7 +289,7 @@ enum cpu_type_enum {
#define MIPS_CPU_ISA_M64R2 0x00000100 #define MIPS_CPU_ISA_M64R2 0x00000100
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
......
...@@ -206,7 +206,7 @@ ...@@ -206,7 +206,7 @@
#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
#define GIC_VPE_EIC_SS(intr) \ #define GIC_VPE_EIC_SS(intr) \
(GIC_EIC_SHADOW_SET_BASE + (4 * intr)) (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
#define GIC_VPE_EIC_VEC_BASE 0x0800 #define GIC_VPE_EIC_VEC_BASE 0x0800
#define GIC_VPE_EIC_VEC(intr) \ #define GIC_VPE_EIC_VEC(intr) \
...@@ -330,6 +330,17 @@ struct gic_intr_map { ...@@ -330,6 +330,17 @@ struct gic_intr_map {
#define GIC_FLAG_TRANSPARENT 0x02 #define GIC_FLAG_TRANSPARENT 0x02
}; };
/*
* This is only used in EIC mode. This helps to figure out which
* shared interrupts we need to process when we get a vector interrupt.
*/
#define GIC_MAX_SHARED_INTR 0x5
struct gic_shared_intr_map {
unsigned int num_shared_intr;
unsigned int intr_list[GIC_MAX_SHARED_INTR];
unsigned int local_intr_mask;
};
extern void gic_init(unsigned long gic_base_addr, extern void gic_init(unsigned long gic_base_addr,
unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
unsigned int intrmap_size, unsigned int irqbase); unsigned int intrmap_size, unsigned int irqbase);
...@@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void); ...@@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void);
extern void gic_send_ipi(unsigned int intr); extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
extern void gic_bind_eic_interrupt(int irq, int set);
extern unsigned int gic_get_timer_pending(void);
#endif /* _ASM_GICREGS_H */ #endif /* _ASM_GICREGS_H */
...@@ -251,7 +251,7 @@ struct f_format { /* FPU register format */ ...@@ -251,7 +251,7 @@ struct f_format { /* FPU register format */
unsigned int func : 6; unsigned int func : 6;
}; };
struct ma_format { /* FPU multipy and add format (MIPS IV) */ struct ma_format { /* FPU multiply and add format (MIPS IV) */
unsigned int opcode : 6; unsigned int opcode : 6;
unsigned int fr : 5; unsigned int fr : 5;
unsigned int ft : 5; unsigned int ft : 5;
...@@ -324,7 +324,7 @@ struct f_format { /* FPU register format */ ...@@ -324,7 +324,7 @@ struct f_format { /* FPU register format */
unsigned int opcode : 6; unsigned int opcode : 6;
}; };
struct ma_format { /* FPU multipy and add format (MIPS IV) */ struct ma_format { /* FPU multiply and add format (MIPS IV) */
unsigned int fmt : 2; unsigned int fmt : 2;
unsigned int func : 4; unsigned int func : 4;
unsigned int fd : 5; unsigned int fd : 5;
......
...@@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq); ...@@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq);
* IE7. Since R2 their number has to be read from the c0_intctl register. * IE7. Since R2 their number has to be read from the c0_intctl register.
*/ */
#define CP0_LEGACY_COMPARE_IRQ 7 #define CP0_LEGACY_COMPARE_IRQ 7
#define CP0_LEGACY_PERFCNT_IRQ 7
extern int cp0_compare_irq; extern int cp0_compare_irq;
extern int cp0_compare_irq_shift; extern int cp0_compare_irq_shift;
......
...@@ -99,7 +99,7 @@ ...@@ -99,7 +99,7 @@
#define CKCTL_6368_USBH_CLK_EN (1 << 15) #define CKCTL_6368_USBH_CLK_EN (1 << 15)
#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
#define CKCTL_6368_NAND_CLK_EN (1 << 17) #define CKCTL_6368_NAND_CLK_EN (1 << 17)
#define CKCTL_6368_IPSEC_CLK_EN (1 << 17) #define CKCTL_6368_IPSEC_CLK_EN (1 << 18)
#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
CKCTL_6368_SWPKT_SAR_EN | \ CKCTL_6368_SWPKT_SAR_EN | \
......
...@@ -86,6 +86,16 @@ ...@@ -86,6 +86,16 @@
#define GIC_CPU_INT4 4 /* . */ #define GIC_CPU_INT4 4 /* . */
#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ #define GIC_CPU_INT5 5 /* Core Interrupt 5 */
/* MALTA GIC local interrupts */
#define GIC_INT_TMR (GIC_CPU_INT5)
#define GIC_INT_PERFCTR (GIC_CPU_INT5)
/* GIC constants */
/* Add 2 to convert non-eic hw int # to eic vector # */
#define GIC_CPU_TO_VEC_OFFSET (2)
/* If we map an intr to pin X, GIC will actually generate vector X+1 */
#define GIC_PIN_TO_VEC_OFFSET (1)
#define GIC_EXT_INTR(x) x #define GIC_EXT_INTR(x) x
/* External Interrupts used for IPI */ /* External Interrupts used for IPI */
......
...@@ -22,7 +22,7 @@ struct task_struct; ...@@ -22,7 +22,7 @@ struct task_struct;
* switch_to(n) should switch tasks to task nr n, first * switch_to(n) should switch tasks to task nr n, first
* checking that n isn't the current task, in which case it does nothing. * checking that n isn't the current task, in which case it does nothing.
*/ */
extern asmlinkage void *resume(void *last, void *next, void *next_ti); extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu);
extern unsigned int ll_bit; extern unsigned int ll_bit;
extern struct task_struct *ll_task; extern struct task_struct *ll_task;
...@@ -66,11 +66,13 @@ do { \ ...@@ -66,11 +66,13 @@ do { \
#define switch_to(prev, next, last) \ #define switch_to(prev, next, last) \
do { \ do { \
u32 __usedfpu; \
__mips_mt_fpaff_switch_to(prev); \ __mips_mt_fpaff_switch_to(prev); \
if (cpu_has_dsp) \ if (cpu_has_dsp) \
__save_dsp(prev); \ __save_dsp(prev); \
__clear_software_ll_bit(); \ __clear_software_ll_bit(); \
(last) = resume(prev, next, task_thread_info(next)); \ __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \
(last) = resume(prev, next, task_thread_info(next), __usedfpu); \
} while (0) } while (0)
#define finish_arch_switch(prev) \ #define finish_arch_switch(prev) \
......
...@@ -60,6 +60,8 @@ struct thread_info { ...@@ -60,6 +60,8 @@ struct thread_info {
register struct thread_info *__current_thread_info __asm__("$28"); register struct thread_info *__current_thread_info __asm__("$28");
#define current_thread_info() __current_thread_info #define current_thread_info() __current_thread_info
#endif /* !__ASSEMBLY__ */
/* thread information allocation */ /* thread information allocation */
#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
#define THREAD_SIZE_ORDER (1) #define THREAD_SIZE_ORDER (1)
...@@ -85,8 +87,6 @@ register struct thread_info *__current_thread_info __asm__("$28"); ...@@ -85,8 +87,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
#define STACK_WARN (THREAD_SIZE / 8) #define STACK_WARN (THREAD_SIZE / 8)
#endif /* !__ASSEMBLY__ */
#define PREEMPT_ACTIVE 0x10000000 #define PREEMPT_ACTIVE 0x10000000
/* /*
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Copyright (C) xxxx the Anonymous * Copyright (C) xxxx the Anonymous
* Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 1994 - 2006 Ralf Baechle
* Copyright (C) 2003, 2004 Maciej W. Rozycki * Copyright (C) 2003, 2004 Maciej W. Rozycki
* Copyright (C) 2001, 2004 MIPS Inc. * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
...@@ -199,6 +199,7 @@ void __init check_wait(void) ...@@ -199,6 +199,7 @@ void __init check_wait(void)
cpu_wait = rm7k_wait_irqoff; cpu_wait = rm7k_wait_irqoff;
break; break;
case CPU_M14KC:
case CPU_24K: case CPU_24K:
case CPU_34K: case CPU_34K:
case CPU_1004K: case CPU_1004K:
...@@ -810,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -810,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_5KC; c->cputype = CPU_5KC;
__cpu_name[cpu] = "MIPS 5Kc"; __cpu_name[cpu] = "MIPS 5Kc";
break; break;
case PRID_IMP_5KE:
c->cputype = CPU_5KE;
__cpu_name[cpu] = "MIPS 5KE";
break;
case PRID_IMP_20KC: case PRID_IMP_20KC:
c->cputype = CPU_20KC; c->cputype = CPU_20KC;
__cpu_name[cpu] = "MIPS 20Kc"; __cpu_name[cpu] = "MIPS 20Kc";
...@@ -831,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -831,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_74K; c->cputype = CPU_74K;
__cpu_name[cpu] = "MIPS 74Kc"; __cpu_name[cpu] = "MIPS 74Kc";
break; break;
case PRID_IMP_M14KC:
c->cputype = CPU_M14KC;
__cpu_name[cpu] = "MIPS M14Kc";
break;
case PRID_IMP_1004K: case PRID_IMP_1004K:
c->cputype = CPU_1004K; c->cputype = CPU_1004K;
__cpu_name[cpu] = "MIPS 1004Kc"; __cpu_name[cpu] = "MIPS 1004Kc";
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05 by Ralf Baechle * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle
* Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc. * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc.
*/ */
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -34,6 +34,12 @@ EXPORT_SYMBOL(memmove); ...@@ -34,6 +34,12 @@ EXPORT_SYMBOL(memmove);
EXPORT_SYMBOL(kernel_thread); EXPORT_SYMBOL(kernel_thread);
/*
* Functions that operate on entire pages. Mostly used by memory management.
*/
EXPORT_SYMBOL(clear_page);
EXPORT_SYMBOL(copy_page);
/* /*
* Userspace access stuff. * Userspace access stuff.
*/ */
......
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
/* /*
* task_struct *resume(task_struct *prev, task_struct *next, * task_struct *resume(task_struct *prev, task_struct *next,
* struct thread_info *next_ti) * struct thread_info *next_ti, int usedfpu)
*/ */
.align 7 .align 7
LEAF(resume) LEAF(resume)
......
...@@ -162,11 +162,6 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters) ...@@ -162,11 +162,6 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters)
return counters >> vpe_shift(); return counters >> vpe_shift();
} }
static unsigned int counters_per_cpu_to_total(unsigned int counters)
{
return counters << vpe_shift();
}
#else /* !CONFIG_MIPS_MT_SMP */ #else /* !CONFIG_MIPS_MT_SMP */
#define vpe_id() 0 #define vpe_id() 0
......
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
/* /*
* task_struct *resume(task_struct *prev, task_struct *next, * task_struct *resume(task_struct *prev, task_struct *next,
* struct thread_info *next_ti) ) * struct thread_info *next_ti, int usedfpu)
*/ */
LEAF(resume) LEAF(resume)
mfc0 t1, CP0_STATUS mfc0 t1, CP0_STATUS
...@@ -51,18 +51,9 @@ LEAF(resume) ...@@ -51,18 +51,9 @@ LEAF(resume)
cpu_save_nonscratch a0 cpu_save_nonscratch a0
sw ra, THREAD_REG31(a0) sw ra, THREAD_REG31(a0)
/* beqz a3, 1f
* check if we need to save FPU registers
*/
lw t3, TASK_THREAD_INFO(a0)
lw t0, TI_FLAGS(t3)
li t1, _TIF_USEDFPU
and t2, t0, t1
beqz t2, 1f
nor t1, zero, t1
and t0, t0, t1 PTR_L t3, TASK_THREAD_INFO(a0)
sw t0, TI_FLAGS(t3)
/* /*
* clear saved user stack CU1 bit * clear saved user stack CU1 bit
......
...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
/* /*
* task_struct *resume(task_struct *prev, task_struct *next, * task_struct *resume(task_struct *prev, task_struct *next,
* struct thread_info *next_ti) * struct thread_info *next_ti, int usedfpu)
*/ */
.align 5 .align 5
LEAF(resume) LEAF(resume)
...@@ -53,16 +53,10 @@ ...@@ -53,16 +53,10 @@
/* /*
* check if we need to save FPU registers * check if we need to save FPU registers
*/ */
PTR_L t3, TASK_THREAD_INFO(a0)
LONG_L t0, TI_FLAGS(t3)
li t1, _TIF_USEDFPU
and t2, t0, t1
beqz t2, 1f
nor t1, zero, t1
and t0, t0, t1 beqz a3, 1f
LONG_S t0, TI_FLAGS(t3)
PTR_L t3, TASK_THREAD_INFO(a0)
/* /*
* clear saved user stack CU1 bit * clear saved user stack CU1 bit
*/ */
......
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#include <linux/smp.h> #include <linux/smp.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/cpu.h> #include <linux/cpu.h>
#include <linux/cpumask.h> #include <linux/cpumask.h>
#include <linux/reboot.h> #include <linux/reboot.h>
...@@ -197,13 +196,6 @@ static void bmips_init_secondary(void) ...@@ -197,13 +196,6 @@ static void bmips_init_secondary(void)
write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
#endif #endif
/* make sure there won't be a timer interrupt for a little while */
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
irq_enable_hazard();
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
irq_enable_hazard();
} }
/* /*
...@@ -212,6 +204,13 @@ static void bmips_init_secondary(void) ...@@ -212,6 +204,13 @@ static void bmips_init_secondary(void)
static void bmips_smp_finish(void) static void bmips_smp_finish(void)
{ {
pr_info("SMP: CPU%d is running\n", smp_processor_id()); pr_info("SMP: CPU%d is running\n", smp_processor_id());
/* make sure there won't be a timer interrupt for a little while */
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
irq_enable_hazard();
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
irq_enable_hazard();
} }
/* /*
......
...@@ -122,13 +122,21 @@ asmlinkage __cpuinit void start_secondary(void) ...@@ -122,13 +122,21 @@ asmlinkage __cpuinit void start_secondary(void)
notify_cpu_starting(cpu); notify_cpu_starting(cpu);
mp_ops->smp_finish(); set_cpu_online(cpu, true);
set_cpu_sibling_map(cpu); set_cpu_sibling_map(cpu);
cpu_set(cpu, cpu_callin_map); cpu_set(cpu, cpu_callin_map);
synchronise_count_slave(); synchronise_count_slave();
/*
* irq will be enabled in ->smp_finish(), enabling it too early
* is dangerous.
*/
WARN_ON_ONCE(!irqs_disabled());
mp_ops->smp_finish();
cpu_idle(); cpu_idle();
} }
...@@ -196,8 +204,6 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) ...@@ -196,8 +204,6 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
while (!cpu_isset(cpu, cpu_callin_map)) while (!cpu_isset(cpu, cpu_callin_map))
udelay(100); udelay(100);
set_cpu_online(cpu, true);
return 0; return 0;
} }
......
...@@ -322,7 +322,7 @@ int __init smtc_build_cpu_map(int start_cpu_slot) ...@@ -322,7 +322,7 @@ int __init smtc_build_cpu_map(int start_cpu_slot)
/* /*
* Common setup before any secondaries are started * Common setup before any secondaries are started
* Make sure all CPU's are in a sensible state before we boot any of the * Make sure all CPUs are in a sensible state before we boot any of the
* secondaries. * secondaries.
* *
* For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
...@@ -340,12 +340,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu) ...@@ -340,12 +340,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
/* /*
* TCContext gets an offset from the base of the IPIQ array * TCContext gets an offset from the base of the IPIQ array
* to be used in low-level code to detect the presence of * to be used in low-level code to detect the presence of
* an active IPI queue * an active IPI queue.
*/ */
write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
/* Bind tc to vpe */ /* Bind tc to vpe */
write_tc_c0_tcbind(vpe); write_tc_c0_tcbind(vpe);
/* In general, all TCs should have the same cpu_data indications */ /* In general, all TCs should have the same cpu_data indications. */
memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
/* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
if (cpu_data[0].cputype == CPU_34K || if (cpu_data[0].cputype == CPU_34K ||
...@@ -358,8 +358,8 @@ static void smtc_tc_setup(int vpe, int tc, int cpu) ...@@ -358,8 +358,8 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
} }
/* /*
* Tweak to get Count registes in as close a sync as possible. * Tweak to get Count registes in as close a sync as possible. The
* Value seems good for 34K-class cores. * value seems good for 34K-class cores.
*/ */
#define CP0_SKEW 8 #define CP0_SKEW 8
...@@ -615,7 +615,6 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) ...@@ -615,7 +615,6 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
void smtc_init_secondary(void) void smtc_init_secondary(void)
{ {
local_irq_enable();
} }
void smtc_smp_finish(void) void smtc_smp_finish(void)
...@@ -631,6 +630,8 @@ void smtc_smp_finish(void) ...@@ -631,6 +630,8 @@ void smtc_smp_finish(void)
if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id)) if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
local_irq_enable();
printk("TC %d going on-line as CPU %d\n", printk("TC %d going on-line as CPU %d\n",
cpu_data[smp_processor_id()].tc_id, smp_processor_id()); cpu_data[smp_processor_id()].tc_id, smp_processor_id());
} }
......
...@@ -111,7 +111,6 @@ void __cpuinit synchronise_count_master(void) ...@@ -111,7 +111,6 @@ void __cpuinit synchronise_count_master(void)
void __cpuinit synchronise_count_slave(void) void __cpuinit synchronise_count_slave(void)
{ {
int i; int i;
unsigned long flags;
unsigned int initcount; unsigned int initcount;
int ncpus; int ncpus;
...@@ -123,8 +122,6 @@ void __cpuinit synchronise_count_slave(void) ...@@ -123,8 +122,6 @@ void __cpuinit synchronise_count_slave(void)
return; return;
#endif #endif
local_irq_save(flags);
/* /*
* Not every cpu is online at the time this gets called, * Not every cpu is online at the time this gets called,
* so we first wait for the master to say everyone is ready * so we first wait for the master to say everyone is ready
...@@ -154,7 +151,5 @@ void __cpuinit synchronise_count_slave(void) ...@@ -154,7 +151,5 @@ void __cpuinit synchronise_count_slave(void)
} }
/* Arrange for an interrupt in a short while */ /* Arrange for an interrupt in a short while */
write_c0_compare(read_c0_count() + COUNTON); write_c0_compare(read_c0_count() + COUNTON);
local_irq_restore(flags);
} }
#undef NR_LOOPS #undef NR_LOOPS
...@@ -132,6 +132,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) ...@@ -132,6 +132,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
unsigned long ra = regs->regs[31]; unsigned long ra = regs->regs[31];
unsigned long pc = regs->cp0_epc; unsigned long pc = regs->cp0_epc;
if (!task)
task = current;
if (raw_show_trace || !__kernel_text_address(pc)) { if (raw_show_trace || !__kernel_text_address(pc)) {
show_raw_backtrace(sp); show_raw_backtrace(sp);
return; return;
...@@ -1249,6 +1252,7 @@ static inline void parity_protection_init(void) ...@@ -1249,6 +1252,7 @@ static inline void parity_protection_init(void)
break; break;
case CPU_5KC: case CPU_5KC:
case CPU_5KE:
write_c0_ecc(0x80000000); write_c0_ecc(0x80000000);
back_to_back_c0_hazard(); back_to_back_c0_hazard();
/* Set the PE bit (bit 31) in the c0_errctl register. */ /* Set the PE bit (bit 31) in the c0_errctl register. */
...@@ -1498,6 +1502,7 @@ extern void flush_tlb_handlers(void); ...@@ -1498,6 +1502,7 @@ extern void flush_tlb_handlers(void);
* Timer interrupt * Timer interrupt
*/ */
int cp0_compare_irq; int cp0_compare_irq;
EXPORT_SYMBOL_GPL(cp0_compare_irq);
int cp0_compare_irq_shift; int cp0_compare_irq_shift;
/* /*
...@@ -1597,7 +1602,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) ...@@ -1597,7 +1602,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
cp0_perfcount_irq = -1; cp0_perfcount_irq = -1;
} else { } else {
cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
cp0_compare_irq_shift = cp0_compare_irq; cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
cp0_perfcount_irq = -1; cp0_perfcount_irq = -1;
} }
......
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/thread_info.h>
#include <asm-generic/vmlinux.lds.h> #include <asm-generic/vmlinux.lds.h>
#undef mips #undef mips
...@@ -72,7 +73,7 @@ SECTIONS ...@@ -72,7 +73,7 @@ SECTIONS
.data : { /* Data */ .data : { /* Data */
. = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
INIT_TASK_DATA(PAGE_SIZE) INIT_TASK_DATA(THREAD_SIZE)
NOSAVE_DATA NOSAVE_DATA
CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
......
...@@ -3,8 +3,8 @@ ...@@ -3,8 +3,8 @@
# #
obj-y += cache.o dma-default.o extable.o fault.o \ obj-y += cache.o dma-default.o extable.o fault.o \
gup.o init.o mmap.o page.o tlbex.o \ gup.o init.o mmap.o page.o page-funcs.o \
tlbex-fault.o uasm.o tlbex.o tlbex-fault.o uasm.o
obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_64BIT) += pgtable-64.o
......
...@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) ...@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
c->icache.linesz = 2 << lsize; c->icache.linesz = 2 << lsize;
else else
c->icache.linesz = lsize; c->icache.linesz = lsize;
c->icache.sets = 64 << ((config1 >> 22) & 7); c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
c->icache.ways = 1 + ((config1 >> 16) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7);
icache_size = c->icache.sets * icache_size = c->icache.sets *
...@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) ...@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
c->dcache.linesz = 2 << lsize; c->dcache.linesz = 2 << lsize;
else else
c->dcache.linesz= lsize; c->dcache.linesz= lsize;
c->dcache.sets = 64 << ((config1 >> 13) & 7); c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
c->dcache.ways = 1 + ((config1 >> 7) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7);
dcache_size = c->dcache.sets * dcache_size = c->dcache.sets *
...@@ -1051,6 +1051,7 @@ static void __cpuinit probe_pcache(void) ...@@ -1051,6 +1051,7 @@ static void __cpuinit probe_pcache(void)
case CPU_R14000: case CPU_R14000:
break; break;
case CPU_M14KC:
case CPU_24K: case CPU_24K:
case CPU_34K: case CPU_34K:
case CPU_74K: case CPU_74K:
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Micro-assembler generated clear_page/copy_page functions.
*
* Copyright (C) 2012 MIPS Technologies, Inc.
* Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
#define cpu_clear_page_function_name clear_page_cpu
#define cpu_copy_page_function_name copy_page_cpu
#else
#define cpu_clear_page_function_name clear_page
#define cpu_copy_page_function_name copy_page
#endif
/*
* Maximum sizes:
*
* R4000 128 bytes S-cache: 0x058 bytes
* R4600 v1.7: 0x05c bytes
* R4600 v2.0: 0x060 bytes
* With prefetching, 16 word strides 0x120 bytes
*/
EXPORT(__clear_page_start)
LEAF(cpu_clear_page_function_name)
1: j 1b /* Dummy, will be replaced. */
.space 288
END(cpu_clear_page_function_name)
EXPORT(__clear_page_end)
/*
* Maximum sizes:
*
* R4000 128 bytes S-cache: 0x11c bytes
* R4600 v1.7: 0x080 bytes
* R4600 v2.0: 0x07c bytes
* With prefetching, 16 word strides 0x540 bytes
*/
EXPORT(__copy_page_start)
LEAF(cpu_copy_page_function_name)
1: j 1b /* Dummy, will be replaced. */
.space 1344
END(cpu_copy_page_function_name)
EXPORT(__copy_page_end)
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
* Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2007 Maciej W. Rozycki * Copyright (C) 2007 Maciej W. Rozycki
* Copyright (C) 2008 Thiemo Seufer * Copyright (C) 2008 Thiemo Seufer
* Copyright (C) 2012 MIPS Technologies, Inc.
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
...@@ -71,45 +72,6 @@ static struct uasm_reloc __cpuinitdata relocs[5]; ...@@ -71,45 +72,6 @@ static struct uasm_reloc __cpuinitdata relocs[5];
#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
/*
* Maximum sizes:
*
* R4000 128 bytes S-cache: 0x058 bytes
* R4600 v1.7: 0x05c bytes
* R4600 v2.0: 0x060 bytes
* With prefetching, 16 word strides 0x120 bytes
*/
static u32 clear_page_array[0x120 / 4];
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
void clear_page_cpu(void *page) __attribute__((alias("clear_page_array")));
#else
void clear_page(void *page) __attribute__((alias("clear_page_array")));
#endif
EXPORT_SYMBOL(clear_page);
/*
* Maximum sizes:
*
* R4000 128 bytes S-cache: 0x11c bytes
* R4600 v1.7: 0x080 bytes
* R4600 v2.0: 0x07c bytes
* With prefetching, 16 word strides 0x540 bytes
*/
static u32 copy_page_array[0x540 / 4];
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
void
copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array")));
#else
void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
#endif
EXPORT_SYMBOL(copy_page);
static int pref_bias_clear_store __cpuinitdata; static int pref_bias_clear_store __cpuinitdata;
static int pref_bias_copy_load __cpuinitdata; static int pref_bias_copy_load __cpuinitdata;
static int pref_bias_copy_store __cpuinitdata; static int pref_bias_copy_store __cpuinitdata;
...@@ -282,10 +244,15 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off) ...@@ -282,10 +244,15 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
} }
} }
extern u32 __clear_page_start;
extern u32 __clear_page_end;
extern u32 __copy_page_start;
extern u32 __copy_page_end;
void __cpuinit build_clear_page(void) void __cpuinit build_clear_page(void)
{ {
int off; int off;
u32 *buf = (u32 *)&clear_page_array; u32 *buf = &__clear_page_start;
struct uasm_label *l = labels; struct uasm_label *l = labels;
struct uasm_reloc *r = relocs; struct uasm_reloc *r = relocs;
int i; int i;
...@@ -356,17 +323,17 @@ void __cpuinit build_clear_page(void) ...@@ -356,17 +323,17 @@ void __cpuinit build_clear_page(void)
uasm_i_jr(&buf, RA); uasm_i_jr(&buf, RA);
uasm_i_nop(&buf); uasm_i_nop(&buf);
BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array)); BUG_ON(buf > &__clear_page_end);
uasm_resolve_relocs(relocs, labels); uasm_resolve_relocs(relocs, labels);
pr_debug("Synthesized clear page handler (%u instructions).\n", pr_debug("Synthesized clear page handler (%u instructions).\n",
(u32)(buf - clear_page_array)); (u32)(buf - &__clear_page_start));
pr_debug("\t.set push\n"); pr_debug("\t.set push\n");
pr_debug("\t.set noreorder\n"); pr_debug("\t.set noreorder\n");
for (i = 0; i < (buf - clear_page_array); i++) for (i = 0; i < (buf - &__clear_page_start); i++)
pr_debug("\t.word 0x%08x\n", clear_page_array[i]); pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
pr_debug("\t.set pop\n"); pr_debug("\t.set pop\n");
} }
...@@ -427,7 +394,7 @@ static inline void build_copy_store_pref(u32 **buf, int off) ...@@ -427,7 +394,7 @@ static inline void build_copy_store_pref(u32 **buf, int off)
void __cpuinit build_copy_page(void) void __cpuinit build_copy_page(void)
{ {
int off; int off;
u32 *buf = (u32 *)&copy_page_array; u32 *buf = &__copy_page_start;
struct uasm_label *l = labels; struct uasm_label *l = labels;
struct uasm_reloc *r = relocs; struct uasm_reloc *r = relocs;
int i; int i;
...@@ -595,21 +562,23 @@ void __cpuinit build_copy_page(void) ...@@ -595,21 +562,23 @@ void __cpuinit build_copy_page(void)
uasm_i_jr(&buf, RA); uasm_i_jr(&buf, RA);
uasm_i_nop(&buf); uasm_i_nop(&buf);
BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array)); BUG_ON(buf > &__copy_page_end);
uasm_resolve_relocs(relocs, labels); uasm_resolve_relocs(relocs, labels);
pr_debug("Synthesized copy page handler (%u instructions).\n", pr_debug("Synthesized copy page handler (%u instructions).\n",
(u32)(buf - copy_page_array)); (u32)(buf - &__copy_page_start));
pr_debug("\t.set push\n"); pr_debug("\t.set push\n");
pr_debug("\t.set noreorder\n"); pr_debug("\t.set noreorder\n");
for (i = 0; i < (buf - copy_page_array); i++) for (i = 0; i < (buf - &__copy_page_start); i++)
pr_debug("\t.word 0x%08x\n", copy_page_array[i]); pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
pr_debug("\t.set pop\n"); pr_debug("\t.set pop\n");
} }
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
extern void clear_page_cpu(void *page);
extern void copy_page_cpu(void *to, void *from);
/* /*
* Pad descriptors to cacheline, since each is exclusively owned by a * Pad descriptors to cacheline, since each is exclusively owned by a
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2008, 2009 Cavium Networks, Inc. * Copyright (C) 2008, 2009 Cavium Networks, Inc.
* Copyright (C) 2011 MIPS Technologies, Inc.
* *
* ... and the days got worse and worse and now you see * ... and the days got worse and worse and now you see
* I've gone completly out of my mind. * I've gone completly out of my mind.
...@@ -494,6 +495,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, ...@@ -494,6 +495,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R14000: case CPU_R14000:
case CPU_4KC: case CPU_4KC:
case CPU_4KEC: case CPU_4KEC:
case CPU_M14KC:
case CPU_SB1: case CPU_SB1:
case CPU_SB1A: case CPU_SB1A:
case CPU_4KSC: case CPU_4KSC:
......
...@@ -241,8 +241,9 @@ void __init mips_pcibios_init(void) ...@@ -241,8 +241,9 @@ void __init mips_pcibios_init(void)
return; return;
} }
if (controller->io_resource->start < 0x00001000UL) /* FIXME */ /* Change start address to avoid conflicts with ACPI and SMB devices */
controller->io_resource->start = 0x00001000UL; if (controller->io_resource->start < 0x00002000UL)
controller->io_resource->start = 0x00002000UL;
iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
ioport_resource.end = controller->io_resource->end; ioport_resource.end = controller->io_resource->end;
...@@ -253,7 +254,7 @@ void __init mips_pcibios_init(void) ...@@ -253,7 +254,7 @@ void __init mips_pcibios_init(void)
} }
/* Enable PCI 2.1 compatibility in PIIX4 */ /* Enable PCI 2.1 compatibility in PIIX4 */
static void __init quirk_dlcsetup(struct pci_dev *dev) static void __devinit quirk_dlcsetup(struct pci_dev *dev)
{ {
u8 odlc, ndlc; u8 odlc, ndlc;
(void) pci_read_config_byte(dev, 0x82, &odlc); (void) pci_read_config_byte(dev, 0x82, &odlc);
......
...@@ -111,7 +111,7 @@ static void __init pci_clock_check(void) ...@@ -111,7 +111,7 @@ static void __init pci_clock_check(void)
unsigned int __iomem *jmpr_p = unsigned int __iomem *jmpr_p =
(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
static const int pciclocks[] __initdata = { static const int pciclocks[] __initconst = {
33, 20, 25, 30, 12, 16, 37, 10 33, 20, 25, 30, 12, 16, 37, 10
}; };
int pciclock = pciclocks[jmpr]; int pciclock = pciclocks[jmpr];
......
...@@ -82,8 +82,10 @@ void __init prom_free_prom_memory(void) ...@@ -82,8 +82,10 @@ void __init prom_free_prom_memory(void)
void xlp_mmu_init(void) void xlp_mmu_init(void)
{ {
/* enable extended TLB and Large Fixed TLB */
write_c0_config6(read_c0_config6() | 0x24); write_c0_config6(read_c0_config6() | 0x24);
current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
/* set page mask of Fixed TLB in config7 */
write_c0_config7(PM_DEFAULT_MASK >> write_c0_config7(PM_DEFAULT_MASK >>
(13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
} }
...@@ -100,6 +102,10 @@ void __init prom_init(void) ...@@ -100,6 +102,10 @@ void __init prom_init(void)
nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
nlm_wakeup_secondary_cpus(0xffffffff); nlm_wakeup_secondary_cpus(0xffffffff);
/* update TLB size after waking up threads */
current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
register_smp_ops(&nlm_smp_ops); register_smp_ops(&nlm_smp_ops);
#endif #endif
} }
...@@ -78,6 +78,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) ...@@ -78,6 +78,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
switch (current_cpu_type()) { switch (current_cpu_type()) {
case CPU_5KC: case CPU_5KC:
case CPU_M14KC:
case CPU_20KC: case CPU_20KC:
case CPU_24K: case CPU_24K:
case CPU_25KF: case CPU_25KF:
......
...@@ -322,6 +322,10 @@ static int __init mipsxx_init(void) ...@@ -322,6 +322,10 @@ static int __init mipsxx_init(void)
op_model_mipsxx_ops.num_counters = counters; op_model_mipsxx_ops.num_counters = counters;
switch (current_cpu_type()) { switch (current_cpu_type()) {
case CPU_M14KC:
op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
break;
case CPU_20KC: case CPU_20KC:
op_model_mipsxx_ops.cpu_type = "mips/20K"; op_model_mipsxx_ops.cpu_type = "mips/20K";
break; break;
......
...@@ -48,7 +48,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) ...@@ -48,7 +48,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
return 0; return 0;
} }
static void __init loongson2e_nec_fixup(struct pci_dev *pdev) static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev)
{ {
unsigned int val; unsigned int val;
...@@ -60,7 +60,7 @@ static void __init loongson2e_nec_fixup(struct pci_dev *pdev) ...@@ -60,7 +60,7 @@ static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
pci_write_config_dword(pdev, 0xe4, 1 << 5); pci_write_config_dword(pdev, 0xe4, 1 << 5);
} }
static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev)
{ {
unsigned char c; unsigned char c;
...@@ -135,7 +135,7 @@ static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) ...@@ -135,7 +135,7 @@ static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
printk(KERN_INFO"via686b fix: ISA bridge done\n"); printk(KERN_INFO"via686b fix: ISA bridge done\n");
} }
static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev)
{ {
printk(KERN_INFO"via686b fix: IDE\n"); printk(KERN_INFO"via686b fix: IDE\n");
...@@ -168,19 +168,19 @@ static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) ...@@ -168,19 +168,19 @@ static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
printk(KERN_INFO"via686b fix: IDE done\n"); printk(KERN_INFO"via686b fix: IDE done\n");
} }
static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev) static void __devinit loongson2e_686b_func2_fixup(struct pci_dev *pdev)
{ {
/* irq routing */ /* irq routing */
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
} }
static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev) static void __devinit loongson2e_686b_func3_fixup(struct pci_dev *pdev)
{ {
/* irq routing */ /* irq routing */
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
} }
static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) static void __devinit loongson2e_686b_func5_fixup(struct pci_dev *pdev)
{ {
unsigned int val; unsigned int val;
unsigned char c; unsigned char c;
......
...@@ -96,21 +96,21 @@ int pcibios_plat_dev_init(struct pci_dev *dev) ...@@ -96,21 +96,21 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
} }
/* CS5536 SPEC. fixup */ /* CS5536 SPEC. fixup */
static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) static void __devinit loongson_cs5536_isa_fixup(struct pci_dev *pdev)
{ {
/* the uart1 and uart2 interrupt in PIC is enabled as default */ /* the uart1 and uart2 interrupt in PIC is enabled as default */
pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
} }
static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) static void __devinit loongson_cs5536_ide_fixup(struct pci_dev *pdev)
{ {
/* setting the mutex pin as IDE function */ /* setting the mutex pin as IDE function */
pci_write_config_dword(pdev, PCI_IDE_CFG_REG, pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
CS5536_IDE_FLASH_SIGNATURE); CS5536_IDE_FLASH_SIGNATURE);
} }
static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev)
{ {
/* enable the AUDIO interrupt in PIC */ /* enable the AUDIO interrupt in PIC */
pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
...@@ -118,14 +118,14 @@ static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) ...@@ -118,14 +118,14 @@ static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
} }
static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) static void __devinit loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
{ {
/* enable the OHCI interrupt in PIC */ /* enable the OHCI interrupt in PIC */
/* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
} }
static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
{ {
u32 hi, lo; u32 hi, lo;
...@@ -137,7 +137,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) ...@@ -137,7 +137,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
} }
static void __init loongson_nec_fixup(struct pci_dev *pdev) static void __devinit loongson_nec_fixup(struct pci_dev *pdev)
{ {
unsigned int val; unsigned int val;
......
...@@ -49,10 +49,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev) ...@@ -49,10 +49,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
return 0; return 0;
} }
static void __init malta_piix_func0_fixup(struct pci_dev *pdev) static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev)
{ {
unsigned char reg_val; unsigned char reg_val;
static int piixirqmap[16] __initdata = { /* PIIX PIRQC[A:D] irq mappings */ static int piixirqmap[16] __devinitdata = { /* PIIX PIRQC[A:D] irq mappings */
0, 0, 0, 3, 0, 0, 0, 3,
4, 5, 6, 7, 4, 5, 6, 7,
0, 9, 10, 11, 0, 9, 10, 11,
...@@ -83,7 +83,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev) ...@@ -83,7 +83,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
malta_piix_func0_fixup); malta_piix_func0_fixup);
static void __init malta_piix_func1_fixup(struct pci_dev *pdev) static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
{ {
unsigned char reg_val; unsigned char reg_val;
......
...@@ -22,13 +22,13 @@ ...@@ -22,13 +22,13 @@
#include <asm/vr41xx/mpc30x.h> #include <asm/vr41xx/mpc30x.h>
static const int internal_func_irqs[] __initdata = { static const int internal_func_irqs[] __initconst = {
VRC4173_CASCADE_IRQ, VRC4173_CASCADE_IRQ,
VRC4173_AC97_IRQ, VRC4173_AC97_IRQ,
VRC4173_USB_IRQ, VRC4173_USB_IRQ,
}; };
static const int irq_tab_mpc30x[] __initdata = { static const int irq_tab_mpc30x[] __initconst = {
[12] = VRC4173_PCMCIA1_IRQ, [12] = VRC4173_PCMCIA1_IRQ,
[13] = VRC4173_PCMCIA2_IRQ, [13] = VRC4173_PCMCIA2_IRQ,
[29] = MQ200_IRQ, [29] = MQ200_IRQ,
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
* Set the BCM1250, etc. PCI host bridge's TRDY timeout * Set the BCM1250, etc. PCI host bridge's TRDY timeout
* to the finite max. * to the finite max.
*/ */
static void __init quirk_sb1250_pci(struct pci_dev *dev) static void __devinit quirk_sb1250_pci(struct pci_dev *dev)
{ {
pci_write_config_byte(dev, 0x40, 0xff); pci_write_config_byte(dev, 0x40, 0xff);
} }
...@@ -25,7 +25,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI, ...@@ -25,7 +25,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
/* /*
* The BCM1250, etc. PCI/HT bridge reports as a host bridge. * The BCM1250, etc. PCI/HT bridge reports as a host bridge.
*/ */
static void __init quirk_sb1250_ht(struct pci_dev *dev) static void __devinit quirk_sb1250_ht(struct pci_dev *dev)
{ {
dev->class = PCI_CLASS_BRIDGE_PCI << 8; dev->class = PCI_CLASS_BRIDGE_PCI << 8;
} }
...@@ -35,7 +35,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT, ...@@ -35,7 +35,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
/* /*
* Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max. * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
*/ */
static void __init quirk_sp1011(struct pci_dev *dev) static void __devinit quirk_sp1011(struct pci_dev *dev)
{ {
pci_write_config_byte(dev, 0x64, 0xff); pci_write_config_byte(dev, 0x64, 0xff);
} }
......
...@@ -495,7 +495,7 @@ irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id) ...@@ -495,7 +495,7 @@ irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
} }
#ifdef CONFIG_TOSHIBA_FPCIB0 #ifdef CONFIG_TOSHIBA_FPCIB0
static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
{ {
struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
......
...@@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev) ...@@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev)
bridge->b_widget.w_tflush; /* Flush */ bridge->b_widget.w_tflush; /* Flush */
} }
static void __init pci_fixup_ioc3(struct pci_dev *d) static void __devinit pci_fixup_ioc3(struct pci_dev *d)
{ {
pci_disable_swapping(d); pci_disable_swapping(d);
} }
......
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/irqdesc.h> #include <linux/irqdesc.h>
#include <linux/console.h> #include <linux/console.h>
#include <linux/pci_regs.h>
#include <asm/io.h> #include <asm/io.h>
...@@ -156,35 +157,55 @@ struct pci_controller nlm_pci_controller = { ...@@ -156,35 +157,55 @@ struct pci_controller nlm_pci_controller = {
.io_offset = 0x00000000UL, .io_offset = 0x00000000UL,
}; };
/*
* The top level PCIe links on the XLS PCIe controller appear as
* bridges. Given a device, this function finds which link it is
* on.
*/
static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev)
{
struct pci_bus *bus, *p;
/* Find the bridge on bus 0 */
bus = dev->bus;
for (p = bus->parent; p && p->number != 0; p = p->parent)
bus = p;
return p ? bus->self : NULL;
}
static int get_irq_vector(const struct pci_dev *dev) static int get_irq_vector(const struct pci_dev *dev)
{ {
struct pci_dev *lnk;
if (!nlm_chip_is_xls()) if (!nlm_chip_is_xls())
return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ return PIC_PCIX_IRQ; /* for XLR just one IRQ */
/* /*
* For XLS PCIe, there is an IRQ per Link, find out which * For XLS PCIe, there is an IRQ per Link, find out which
* link the device is on to assign interrupts * link the device is on to assign interrupts
*/ */
if (dev->bus->self == NULL) lnk = xls_get_pcie_link(dev);
if (lnk == NULL)
return 0; return 0;
switch (dev->bus->self->devfn) { switch (PCI_SLOT(lnk->devfn)) {
case 0x0: case 0:
return PIC_PCIE_LINK0_IRQ; return PIC_PCIE_LINK0_IRQ;
case 0x8: case 1:
return PIC_PCIE_LINK1_IRQ; return PIC_PCIE_LINK1_IRQ;
case 0x10: case 2:
if (nlm_chip_is_xls_b()) if (nlm_chip_is_xls_b())
return PIC_PCIE_XLSB0_LINK2_IRQ; return PIC_PCIE_XLSB0_LINK2_IRQ;
else else
return PIC_PCIE_LINK2_IRQ; return PIC_PCIE_LINK2_IRQ;
case 0x18: case 3:
if (nlm_chip_is_xls_b()) if (nlm_chip_is_xls_b())
return PIC_PCIE_XLSB0_LINK3_IRQ; return PIC_PCIE_XLSB0_LINK3_IRQ;
else else
return PIC_PCIE_LINK3_IRQ; return PIC_PCIE_LINK3_IRQ;
} }
WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); WARN(1, "Unexpected devfn %d\n", lnk->devfn);
return 0; return 0;
} }
...@@ -202,7 +223,27 @@ void arch_teardown_msi_irq(unsigned int irq) ...@@ -202,7 +223,27 @@ void arch_teardown_msi_irq(unsigned int irq)
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
{ {
struct msi_msg msg; struct msi_msg msg;
struct pci_dev *lnk;
int irq, ret; int irq, ret;
u16 val;
/* MSI not supported on XLR */
if (!nlm_chip_is_xls())
return 1;
/*
* Enable MSI on the XLS PCIe controller bridge which was disabled
* at enumeration, the bridge MSI capability is at 0x50
*/
lnk = xls_get_pcie_link(dev);
if (lnk == NULL)
return 1;
pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val);
if ((val & PCI_MSI_FLAGS_ENABLE) == 0) {
val |= PCI_MSI_FLAGS_ENABLE;
pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val);
}
irq = get_irq_vector(dev); irq = get_irq_vector(dev);
if (irq <= 0) if (irq <= 0)
...@@ -327,7 +368,7 @@ static int __init pcibios_init(void) ...@@ -327,7 +368,7 @@ static int __init pcibios_init(void)
} }
} else { } else {
/* XLR PCI controller ACK */ /* XLR PCI controller ACK */
irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack);
} }
return 0; return 0;
......
...@@ -115,11 +115,11 @@ static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action) ...@@ -115,11 +115,11 @@ static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
*/ */
static void __cpuinit yos_init_secondary(void) static void __cpuinit yos_init_secondary(void)
{ {
set_c0_status(ST0_CO | ST0_IE | ST0_IM);
} }
static void __cpuinit yos_smp_finish(void) static void __cpuinit yos_smp_finish(void)
{ {
set_c0_status(ST0_CO | ST0_IM | ST0_IE);
} }
/* Hook for after all CPUs are online */ /* Hook for after all CPUs are online */
......
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x)) #define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
const struct register_map calliope_register_map __initdata = { const struct register_map calliope_register_map __initconst = {
.eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)}, .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
.eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)}, .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
.eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)}, .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
......
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) #define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
const struct register_map cronus_register_map __initdata = { const struct register_map cronus_register_map __initconst = {
.eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
.eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
.eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)}, .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
......
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/mach-powertv/asic.h> #include <asm/mach-powertv/asic.h>
const struct register_map gaia_register_map __initdata = { const struct register_map gaia_register_map __initconst = {
.eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
.eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
.eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C}, .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
......
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x)) #define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
const struct register_map zeus_register_map __initdata = { const struct register_map zeus_register_map __initconst = {
.eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)}, .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
.eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)}, .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
.eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)}, .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
......
...@@ -269,7 +269,7 @@ txx9_i8259_irq_setup(int irq) ...@@ -269,7 +269,7 @@ txx9_i8259_irq_setup(int irq)
return err; return err;
} }
static void __init quirk_slc90e66_bridge(struct pci_dev *dev) static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
{ {
int irq; /* PCI/ISA Bridge interrupt */ int irq; /* PCI/ISA Bridge interrupt */
u8 reg_64; u8 reg_64;
......
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