Commit d9f2a202 authored by Arnaud Mouiche's avatar Arnaud Mouiche Committed by Mark Brown

ASoC: fsl_ssi: Fix samples being dropped at Playback startup

If the capture is already running while playback is started, it is highly
probable (>80% in a 8 channels scenario) that samples are lost between
the DMA and TX fifo.

The reason is that SIER.TDMAE is set before STCR.TFEN0, leaving a time
window where the FIFO doesn't receive the samples written by the DMA.

This particular case happened only if capture is already enabled as
SCR.SSIEN is already set at the playback startup instant.
Signed-off-by: default avatarArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Tested-by: default avatarCaleb Crome <caleb@crome.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0096b693
...@@ -475,9 +475,9 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, ...@@ -475,9 +475,9 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
* (online configuration) * (online configuration)
*/ */
if (enable) { if (enable) {
regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
} else { } else {
u32 sier; u32 sier;
u32 srcr; u32 srcr;
......
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