Commit db1c1a8f authored by leiyaoyao's avatar leiyaoyao Committed by Alex Deucher

drm/amdgpu: Stop clearing kiq position during fini

Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform
IDLE-SAVE after VF fini.
Otherwise it could cause GFX hang if another Win guest is rendering.
Signed-off-by: default avatarleiyaoyao <yaoyao.lei@amd.com>
Acked-by: default avatarZhenGuo Yin <zhenguo.yin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c0d5c293
...@@ -7285,17 +7285,9 @@ static int gfx_v10_0_hw_fini(void *handle) ...@@ -7285,17 +7285,9 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_sriov_vf(adev)) { if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_cp_gfx_enable(adev, false); gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ /* Remove the steps of clearing KIQ position.
if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { * It causes GFX hang when another Win guest is rendering.
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); */
tmp &= 0xffffff00;
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
} else {
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
tmp &= 0xffffff00;
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
}
return 0; return 0;
} }
gfx_v10_0_cp_enable(adev, false); gfx_v10_0_cp_enable(adev, false);
......
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