Commit dc4edad6 authored by Jammy Zhou's avatar Jammy Zhou Committed by Alex Deucher

drm/radeon: set correct CE ram size for CIK

CE ram size is 32k/0k/0k for GFX/CS0/CS1 with CIK

Ported from amdgpu driver.
Signed-off-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 66338fee
...@@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev) ...@@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
/* init the CE partitions. CE only used for gfx on CIK */ /* init the CE partitions. CE only used for gfx on CIK */
radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
radeon_ring_write(ring, 0xc000); radeon_ring_write(ring, 0x8000);
radeon_ring_write(ring, 0xc000); radeon_ring_write(ring, 0x8000);
/* setup clear context state */ /* setup clear context state */
radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
......
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