Commit dc7101bb authored by Mike Frysinger's avatar Mike Frysinger

Blackfin: update anomaly lists to latest public info

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 5369fba1
...@@ -5,13 +5,13 @@ ...@@ -5,13 +5,13 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/ */
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
...@@ -24,6 +24,8 @@ ...@@ -24,6 +24,8 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
...@@ -52,6 +54,8 @@ ...@@ -52,6 +54,8 @@
#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) #define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1) #define ANOMALY_05000431 (1)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) #define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
...@@ -74,14 +78,21 @@ ...@@ -74,14 +78,21 @@
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1) #define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ /* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
#define ANOMALY_05000119 (0)
#define ANOMALY_05000120 (0) #define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0) #define ANOMALY_05000149 (0)
...@@ -94,6 +105,7 @@ ...@@ -94,6 +105,7 @@
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0) #define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
...@@ -143,5 +155,6 @@ ...@@ -143,5 +155,6 @@
#define ANOMALY_05000467 (0) #define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0) #define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0) #define ANOMALY_05000475 (0)
#define ANOMALY_05000485 (0)
#endif #endif
...@@ -5,13 +5,13 @@ ...@@ -5,13 +5,13 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
*/ */
...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ #define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
...@@ -168,6 +168,8 @@ ...@@ -168,6 +168,8 @@
#define ANOMALY_05000431 (1) #define ANOMALY_05000431 (1)
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) #define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) #define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* Preboot Cannot be Used to Alter the PLL_DIV Register */ /* Preboot Cannot be Used to Alter the PLL_DIV Register */
...@@ -204,10 +206,22 @@ ...@@ -204,10 +206,22 @@
#define ANOMALY_05000467 (1) #define ANOMALY_05000467 (1)
/* PLL Latches Incorrect Settings During Reset */ /* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1) #define ANOMALY_05000469 (1)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -223,6 +237,7 @@ ...@@ -223,6 +237,7 @@
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0) #define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
...@@ -259,6 +274,5 @@ ...@@ -259,6 +274,5 @@
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000474 (0) #define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#endif #endif
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
...@@ -208,8 +208,14 @@ ...@@ -208,8 +208,14 @@
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are /* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible. * here to show running on older silicon just isn't feasible.
...@@ -358,6 +364,6 @@ ...@@ -358,6 +364,6 @@
#define ANOMALY_05000465 (0) #define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0) #define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0) #define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0) #define ANOMALY_05000485 (0)
#endif #endif
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
...@@ -162,8 +162,14 @@ ...@@ -162,8 +162,14 @@
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -179,6 +185,7 @@ ...@@ -179,6 +185,7 @@
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0) #define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
...@@ -211,6 +218,6 @@ ...@@ -211,6 +218,6 @@
#define ANOMALY_05000465 (0) #define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0) #define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0) #define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0) #define ANOMALY_05000485 (0)
#endif #endif
...@@ -5,14 +5,14 @@ ...@@ -5,14 +5,14 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
* - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
...@@ -132,10 +132,18 @@ ...@@ -132,10 +132,18 @@
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -185,6 +193,6 @@ ...@@ -185,6 +193,6 @@
#define ANOMALY_05000465 (0) #define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0) #define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0) #define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0) #define ANOMALY_05000485 (0)
#endif #endif
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000220 (1) #define ANOMALY_05000220 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1) #define ANOMALY_05000245 (1)
...@@ -210,10 +210,16 @@ ...@@ -210,10 +210,16 @@
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ /* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
#define ANOMALY_05000474 (1) #define ANOMALY_05000474 (1)
/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -229,6 +235,7 @@ ...@@ -229,6 +235,7 @@
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0) #define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
...@@ -263,5 +270,6 @@ ...@@ -263,5 +270,6 @@
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0) #define ANOMALY_05000435 (0)
#define ANOMALY_05000475 (0)
#endif #endif
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2009 Analog Devices Inc. * Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license. * Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/ */
...@@ -152,8 +152,8 @@ ...@@ -152,8 +152,8 @@
#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) #define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
/* NMI Event at Boot Time Results in Unpredictable State */ /* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) #define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) #define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
/* Incorrect Pulse-Width of UART Start Bit */ /* Incorrect Pulse-Width of UART Start Bit */
#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) #define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
/* Scratchpad Memory Bank Reads May Return Incorrect Data */ /* Scratchpad Memory Bank Reads May Return Incorrect Data */
...@@ -290,10 +290,14 @@ ...@@ -290,10 +290,14 @@
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1) #define ANOMALY_05000473 (1)
/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ /* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) #define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
/* TESTSET Instruction Cannot Be Interrupted */ /* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1) #define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0) #define ANOMALY_05000119 (0)
...@@ -319,5 +323,6 @@ ...@@ -319,5 +323,6 @@
#define ANOMALY_05000465 (0) #define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0) #define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0) #define ANOMALY_05000474 (0)
#define ANOMALY_05000485 (0)
#endif #endif
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