Commit dda4fb85 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher

drm/amd/display: DML changes for DCN32/321

DML is required for display configuration modelling for things like
bandwidth management and validation.
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 58efeea3
...@@ -72,6 +72,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) ...@@ -72,6 +72,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag) CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags)
...@@ -93,6 +96,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags) ...@@ -93,6 +96,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags)
...@@ -116,6 +122,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o ...@@ -116,6 +122,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o
DML += dcn31/dcn31_fpu.o DML += dcn31/dcn31_fpu.o
DML += dcn301/dcn301_fpu.o DML += dcn301/dcn301_fpu.o
DML += dcn302/dcn302_fpu.o DML += dcn302/dcn302_fpu.o
......
...@@ -438,8 +438,8 @@ static void UseMinimumDCFCLK( ...@@ -438,8 +438,8 @@ static void UseMinimumDCFCLK(
int dpte_group_bytes[], int dpte_group_bytes[],
double PrefetchLinesY[][2][DC__NUM_DPP__MAX], double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
double PrefetchLinesC[][2][DC__NUM_DPP__MAX], double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
int BytePerPixelY[], int BytePerPixelY[],
int BytePerPixelC[], int BytePerPixelC[],
int HTotal[], int HTotal[],
...@@ -6696,8 +6696,8 @@ static void UseMinimumDCFCLK( ...@@ -6696,8 +6696,8 @@ static void UseMinimumDCFCLK(
int dpte_group_bytes[], int dpte_group_bytes[],
double PrefetchLinesY[][2][DC__NUM_DPP__MAX], double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
double PrefetchLinesC[][2][DC__NUM_DPP__MAX], double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
int BytePerPixelY[], int BytePerPixelY[],
int BytePerPixelC[], int BytePerPixelC[],
int HTotal[], int HTotal[],
......
...@@ -2996,7 +2996,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman ...@@ -2996,7 +2996,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->ImmediateFlipSupported)) ? true : false; v->ImmediateFlipSupported)) ? true : false;
#ifdef __DML_VBA_DEBUG__ #ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported); dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required); dml_print("DML::%s: ImmediateFlipRequirement[0] %d\n", __func__, v->ImmediateFlipRequirement[0] == dm_immediate_flip_required);
dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported); dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport); dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable); dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
......
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/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DML32_DISPLAY_MODE_VBA_H__
#define __DML32_DISPLAY_MODE_VBA_H__
#include "../display_mode_enums.h"
// To enable a lot of debug msg
//#define __DML_VBA_DEBUG__
// For DML-C changes that hasn't been propagated to VBA yet
//#define __DML_VBA_ALLOW_DELTA__
// Move these to ip parameters/constant
// At which vstartup the DML start to try if the mode can be supported
#define __DML_VBA_MIN_VSTARTUP__ 9
// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
#define __DML_ARB_TO_RET_DELAY__ 7 + 95
// fudge factor for min dcfclk calclation
#define __DML_MIN_DCFCLK_FACTOR__ 1.15
// Prefetch schedule max vratio
#define __DML_MAX_VRATIO_PRE__ 4.0
#define BPP_INVALID 0
#define BPP_BLENDED_PIPE 0xffffffff
struct display_mode_lib;
void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
void dml32_recalculate(struct display_mode_lib *mode_lib);
#endif
/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DML32_DISPLAY_RQ_DLG_CALC_H__
#define __DML32_DISPLAY_RQ_DLG_CALC_H__
#include "../display_rq_dlg_helpers.h"
struct display_mode_lib;
/*
* Function: dml_rq_dlg_get_rq_reg
* Main entry point for test to get the register values out of this DML class.
* This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
* and then populate the rq_regs struct
* Input:
* pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
* Output:
* rq_regs - struct that holds all the RQ registers field value.
* See also: <display_rq_regs_st>
*/
void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx);
/*
* Function: dml_rq_dlg_get_dlg_reg
* Calculate and return DLG and TTU register struct given the system setting
* Output:
* dlg_regs - output DLG register struct
* ttu_regs - output DLG TTU register struct
* Input:
* e2e_pipe_param - "compacted" array of e2e pipe param struct
* num_pipes - num of active "pipe" or "route"
* pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
* cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
* Added for legacy or unrealistic timing tests.
*/
void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
display_dlg_regs_st *dlg_regs,
display_ttu_regs_st *ttu_regs,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx);
#endif
...@@ -26,7 +26,11 @@ ...@@ -26,7 +26,11 @@
#define __DISPLAY_MODE_ENUMS_H__ #define __DISPLAY_MODE_ENUMS_H__
enum output_encoder_class { enum output_encoder_class {
dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp dm_dp = 0,
dm_hdmi = 1,
dm_wb = 2,
dm_edp = 3,
dm_dp2p0 = 5,
}; };
enum output_format_class { enum output_format_class {
dm_444 = 0, dm_420 = 1, dm_n422, dm_s422 dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
...@@ -105,6 +109,10 @@ enum clock_change_support { ...@@ -105,6 +109,10 @@ enum clock_change_support {
dm_dram_clock_change_uninitialized = 0, dm_dram_clock_change_uninitialized = 0,
dm_dram_clock_change_vactive, dm_dram_clock_change_vactive,
dm_dram_clock_change_vblank, dm_dram_clock_change_vblank,
dm_dram_clock_change_vactive_w_mall_full_frame,
dm_dram_clock_change_vactive_w_mall_sub_vp,
dm_dram_clock_change_vblank_w_mall_full_frame,
dm_dram_clock_change_vblank_w_mall_sub_vp,
dm_dram_clock_change_unsupported dm_dram_clock_change_unsupported
}; };
...@@ -169,6 +177,9 @@ enum odm_combine_mode { ...@@ -169,6 +177,9 @@ enum odm_combine_mode {
dm_odm_combine_mode_disabled, dm_odm_combine_mode_disabled,
dm_odm_combine_mode_2to1, dm_odm_combine_mode_2to1,
dm_odm_combine_mode_4to1, dm_odm_combine_mode_4to1,
dm_odm_split_mode_1to2,
dm_odm_mode_mso_1to2,
dm_odm_mode_mso_1to4
}; };
enum odm_combine_policy { enum odm_combine_policy {
...@@ -176,11 +187,15 @@ enum odm_combine_policy { ...@@ -176,11 +187,15 @@ enum odm_combine_policy {
dm_odm_combine_policy_none, dm_odm_combine_policy_none,
dm_odm_combine_policy_2to1, dm_odm_combine_policy_2to1,
dm_odm_combine_policy_4to1, dm_odm_combine_policy_4to1,
dm_odm_split_policy_1to2,
dm_odm_mso_policy_1to2,
dm_odm_mso_policy_1to4,
}; };
enum immediate_flip_requirement { enum immediate_flip_requirement {
dm_immediate_flip_not_required, dm_immediate_flip_not_required,
dm_immediate_flip_required, dm_immediate_flip_required,
dm_immediate_flip_opportunistic,
}; };
enum unbounded_requesting_policy { enum unbounded_requesting_policy {
...@@ -189,4 +204,75 @@ enum unbounded_requesting_policy { ...@@ -189,4 +204,75 @@ enum unbounded_requesting_policy {
dm_unbounded_requesting_disable dm_unbounded_requesting_disable
}; };
enum dm_rotation_angle {
dm_rotation_0,
dm_rotation_90,
dm_rotation_180,
dm_rotation_270,
dm_rotation_0m,
dm_rotation_90m,
dm_rotation_180m,
dm_rotation_270m,
};
enum dm_use_mall_for_pstate_change_mode {
dm_use_mall_pstate_change_disable,
dm_use_mall_pstate_change_full_frame,
dm_use_mall_pstate_change_sub_viewport,
dm_use_mall_pstate_change_phantom_pipe
};
enum dm_use_mall_for_static_screen_mode {
dm_use_mall_static_screen_disable,
dm_use_mall_static_screen_optimize,
dm_use_mall_static_screen_enable,
};
enum dm_output_link_dp_rate {
dm_dp_rate_na,
dm_dp_rate_hbr,
dm_dp_rate_hbr2,
dm_dp_rate_hbr3,
dm_dp_rate_uhbr10,
dm_dp_rate_uhbr13p5,
dm_dp_rate_uhbr20,
};
enum dm_fclock_change_support {
dm_fclock_change_vactive,
dm_fclock_change_vblank,
dm_fclock_change_unsupported,
};
enum dm_prefetch_modes {
dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
dm_prefetch_support_uclk_fclk_and_stutter,
dm_prefetch_support_fclk_and_stutter,
dm_prefetch_support_stutter,
dm_prefetch_support_none,
};
enum dm_output_type {
dm_output_type_unknown,
dm_output_type_dp,
dm_output_type_edp,
dm_output_type_dp2p0,
dm_output_type_hdmi,
dm_output_type_hdmifrl,
};
enum dm_output_rate {
dm_output_rate_unknown,
dm_output_rate_dp_rate_hbr,
dm_output_rate_dp_rate_hbr2,
dm_output_rate_dp_rate_hbr3,
dm_output_rate_dp_rate_uhbr10,
dm_output_rate_dp_rate_uhbr13p5,
dm_output_rate_dp_rate_uhbr20,
dm_output_rate_hdmi_rate_3x3,
dm_output_rate_hdmi_rate_6x3,
dm_output_rate_hdmi_rate_6x4,
dm_output_rate_hdmi_rate_8x4,
dm_output_rate_hdmi_rate_10x4,
dm_output_rate_hdmi_rate_12x4,
};
#endif #endif
...@@ -35,6 +35,8 @@ ...@@ -35,6 +35,8 @@
#include "dcn30/display_rq_dlg_calc_30.h" #include "dcn30/display_rq_dlg_calc_30.h"
#include "dcn31/display_mode_vba_31.h" #include "dcn31/display_mode_vba_31.h"
#include "dcn31/display_rq_dlg_calc_31.h" #include "dcn31/display_rq_dlg_calc_31.h"
#include "dcn32/display_mode_vba_32.h"
#include "dcn32/display_rq_dlg_calc_32.h"
#include "dml_logger.h" #include "dml_logger.h"
const struct dml_funcs dml20_funcs = { const struct dml_funcs dml20_funcs = {
...@@ -72,6 +74,13 @@ const struct dml_funcs dml31_funcs = { ...@@ -72,6 +74,13 @@ const struct dml_funcs dml31_funcs = {
.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg .rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
}; };
const struct dml_funcs dml32_funcs = {
.validate = dml32_ModeSupportAndSystemConfigurationFull,
.recalculate = dml32_recalculate,
.rq_dlg_get_dlg_reg_v2 = dml32_rq_dlg_get_dlg_reg,
.rq_dlg_get_rq_reg_v2 = dml32_rq_dlg_get_rq_reg
};
void dml_init_instance(struct display_mode_lib *lib, void dml_init_instance(struct display_mode_lib *lib,
const struct _vcs_dpi_soc_bounding_box_st *soc_bb, const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
const struct _vcs_dpi_ip_params_st *ip_params, const struct _vcs_dpi_ip_params_st *ip_params,
...@@ -98,6 +107,9 @@ void dml_init_instance(struct display_mode_lib *lib, ...@@ -98,6 +107,9 @@ void dml_init_instance(struct display_mode_lib *lib,
case DML_PROJECT_DCN31_FPGA: case DML_PROJECT_DCN31_FPGA:
lib->funcs = dml31_funcs; lib->funcs = dml31_funcs;
break; break;
case DML_PROJECT_DCN32:
lib->funcs = dml32_funcs;
break;
default: default:
break; break;
......
...@@ -41,6 +41,7 @@ enum dml_project { ...@@ -41,6 +41,7 @@ enum dml_project {
DML_PROJECT_DCN30, DML_PROJECT_DCN30,
DML_PROJECT_DCN31, DML_PROJECT_DCN31,
DML_PROJECT_DCN31_FPGA, DML_PROJECT_DCN31_FPGA,
DML_PROJECT_DCN32,
}; };
struct display_mode_lib; struct display_mode_lib;
...@@ -62,6 +63,20 @@ struct dml_funcs { ...@@ -62,6 +63,20 @@ struct dml_funcs {
struct display_mode_lib *mode_lib, struct display_mode_lib *mode_lib,
display_rq_regs_st *rq_regs, display_rq_regs_st *rq_regs,
const display_pipe_params_st *pipe_param); const display_pipe_params_st *pipe_param);
// DLG interfaces have different function parameters in DCN32.
// Create new function pointers to address the changes
void (*rq_dlg_get_dlg_reg_v2)(
struct display_mode_lib *mode_lib,
display_dlg_regs_st *dlg_regs,
display_ttu_regs_st *ttu_regs,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx);
void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx);
void (*recalculate)(struct display_mode_lib *mode_lib); void (*recalculate)(struct display_mode_lib *mode_lib);
void (*validate)(struct display_mode_lib *mode_lib); void (*validate)(struct display_mode_lib *mode_lib);
}; };
......
...@@ -54,12 +54,102 @@ typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; ...@@ -54,12 +54,102 @@ typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
typedef struct {
double UrgentWatermark;
double WritebackUrgentWatermark;
double DRAMClockChangeWatermark;
double FCLKChangeWatermark;
double WritebackDRAMClockChangeWatermark;
double WritebackFCLKChangeWatermark;
double StutterExitWatermark;
double StutterEnterPlusExitWatermark;
double Z8StutterExitWatermark;
double Z8StutterEnterPlusExitWatermark;
double USRRetrainingWatermark;
} Watermarks;
typedef struct {
double UrgentLatency;
double ExtraLatency;
double WritebackLatency;
double DRAMClockChangeLatency;
double FCLKChangeLatency;
double SRExitTime;
double SREnterPlusExitTime;
double SRExitZ8Time;
double SREnterPlusExitZ8Time;
double USRRetrainingLatencyPlusSMNLatency;
} Latencies;
typedef struct {
double Dppclk;
double Dispclk;
double PixelClock;
double DCFClkDeepSleep;
unsigned int DPPPerSurface;
bool ScalerEnabled;
enum dm_rotation_angle SourceRotation;
unsigned int ViewportHeight;
unsigned int ViewportHeightChroma;
unsigned int BlockWidth256BytesY;
unsigned int BlockHeight256BytesY;
unsigned int BlockWidth256BytesC;
unsigned int BlockHeight256BytesC;
unsigned int BlockWidthY;
unsigned int BlockHeightY;
unsigned int BlockWidthC;
unsigned int BlockHeightC;
unsigned int InterlaceEnable;
unsigned int NumberOfCursors;
unsigned int VBlank;
unsigned int HTotal;
unsigned int HActive;
bool DCCEnable;
enum odm_combine_mode ODMMode;
enum source_format_class SourcePixelFormat;
enum dm_swizzle_mode SurfaceTiling;
unsigned int BytePerPixelY;
unsigned int BytePerPixelC;
bool ProgressiveToInterlaceUnitInOPP;
double VRatio;
double VRatioChroma;
unsigned int VTaps;
unsigned int VTapsChroma;
unsigned int PitchY;
unsigned int DCCMetaPitchY;
unsigned int PitchC;
unsigned int DCCMetaPitchC;
bool ViewportStationary;
unsigned int ViewportXStart;
unsigned int ViewportYStart;
unsigned int ViewportXStartC;
unsigned int ViewportYStartC;
bool FORCE_ONE_ROW_FOR_FRAME;
unsigned int SwathHeightY;
unsigned int SwathHeightC;
} DmlPipe;
typedef struct {
double UrgentLatency;
double ExtraLatency;
double WritebackLatency;
double DRAMClockChangeLatency;
double FCLKChangeLatency;
double SRExitTime;
double SREnterPlusExitTime;
double SRExitZ8Time;
double SREnterPlusExitZ8Time;
double USRRetrainingLatency;
double SMNLatency;
} SOCParametersList;
struct _vcs_dpi_voltage_scaling_st { struct _vcs_dpi_voltage_scaling_st {
int state; int state;
double dscclk_mhz; double dscclk_mhz;
double dcfclk_mhz; double dcfclk_mhz;
double socclk_mhz; double socclk_mhz;
double phyclk_d18_mhz; double phyclk_d18_mhz;
double phyclk_d32_mhz;
double dram_speed_mts; double dram_speed_mts;
double fabricclk_mhz; double fabricclk_mhz;
double dispclk_mhz; double dispclk_mhz;
...@@ -80,6 +170,15 @@ struct _vcs_dpi_soc_bounding_box_st { ...@@ -80,6 +170,15 @@ struct _vcs_dpi_soc_bounding_box_st {
double urgent_latency_pixel_data_only_us; double urgent_latency_pixel_data_only_us;
double urgent_latency_pixel_mixed_with_vm_data_us; double urgent_latency_pixel_mixed_with_vm_data_us;
double urgent_latency_vm_data_only_us; double urgent_latency_vm_data_only_us;
double usr_retraining_latency_us;
double smn_latency_us;
double fclk_change_latency_us;
double mall_allocated_for_dcn_mbytes;
double pct_ideal_fabric_bw_after_urgent;
double pct_ideal_dram_bw_after_urgent_strobe;
double max_avg_fabric_bw_use_normal_percent;
double max_avg_dram_bw_use_normal_strobe_percent;
enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
double writeback_latency_us; double writeback_latency_us;
double ideal_dram_bw_after_urgent_percent; double ideal_dram_bw_after_urgent_percent;
double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
...@@ -148,6 +247,9 @@ struct _vcs_dpi_ip_params_st { ...@@ -148,6 +247,9 @@ struct _vcs_dpi_ip_params_st {
unsigned int dpp_output_buffer_pixels; unsigned int dpp_output_buffer_pixels;
unsigned int opp_output_buffer_lines; unsigned int opp_output_buffer_lines;
unsigned int pixel_chunk_size_kbytes; unsigned int pixel_chunk_size_kbytes;
unsigned int alpha_pixel_chunk_size_kbytes;
unsigned int min_pixel_chunk_size_bytes;
unsigned int dcc_meta_buffer_size_bytes;
unsigned char pte_enable; unsigned char pte_enable;
unsigned int pte_chunk_size_kbytes; unsigned int pte_chunk_size_kbytes;
unsigned int meta_chunk_size_kbytes; unsigned int meta_chunk_size_kbytes;
...@@ -168,6 +270,7 @@ struct _vcs_dpi_ip_params_st { ...@@ -168,6 +270,7 @@ struct _vcs_dpi_ip_params_st {
double writeback_min_hscl_ratio; double writeback_min_hscl_ratio;
double writeback_min_vscl_ratio; double writeback_min_vscl_ratio;
unsigned int maximum_dsc_bits_per_component; unsigned int maximum_dsc_bits_per_component;
unsigned int maximum_pixels_per_line_per_dsc_unit;
unsigned int writeback_max_hscl_taps; unsigned int writeback_max_hscl_taps;
unsigned int writeback_max_vscl_taps; unsigned int writeback_max_vscl_taps;
unsigned int writeback_line_buffer_luma_buffer_size; unsigned int writeback_line_buffer_luma_buffer_size;
...@@ -224,6 +327,8 @@ struct _vcs_dpi_ip_params_st { ...@@ -224,6 +327,8 @@ struct _vcs_dpi_ip_params_st {
unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
unsigned int bug_forcing_LC_req_same_size_fixed; unsigned int bug_forcing_LC_req_same_size_fixed;
unsigned int number_of_cursors; unsigned int number_of_cursors;
unsigned int max_num_dp2p0_outputs;
unsigned int max_num_dp2p0_streams;
}; };
struct _vcs_dpi_display_xfc_params_st { struct _vcs_dpi_display_xfc_params_st {
...@@ -250,6 +355,7 @@ struct _vcs_dpi_display_pipe_source_params_st { ...@@ -250,6 +355,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
bool hostvm_levels_force_en; bool hostvm_levels_force_en;
unsigned int hostvm_levels_force; unsigned int hostvm_levels_force;
int source_scan; int source_scan;
int source_rotation; // new in dml32
int sw_mode; int sw_mode;
int macro_tile_size; int macro_tile_size;
unsigned int surface_width_y; unsigned int surface_width_y;
...@@ -264,6 +370,15 @@ struct _vcs_dpi_display_pipe_source_params_st { ...@@ -264,6 +370,15 @@ struct _vcs_dpi_display_pipe_source_params_st {
unsigned int viewport_height_c; unsigned int viewport_height_c;
unsigned int viewport_width_max; unsigned int viewport_width_max;
unsigned int viewport_height_max; unsigned int viewport_height_max;
unsigned int viewport_x_y;
unsigned int viewport_x_c;
bool viewport_stationary;
unsigned int dcc_rate_luma;
unsigned int gpuvm_min_page_size_kbytes;
unsigned int use_mall_for_pstate_change;
unsigned int use_mall_for_static_screen;
bool force_one_row_for_frame;
bool pte_buffer_mode;
unsigned int data_pitch; unsigned int data_pitch;
unsigned int data_pitch_c; unsigned int data_pitch_c;
unsigned int meta_pitch; unsigned int meta_pitch;
...@@ -296,10 +411,17 @@ struct writeback_st { ...@@ -296,10 +411,17 @@ struct writeback_st {
int wb_vtaps_luma; int wb_vtaps_luma;
int wb_htaps_chroma; int wb_htaps_chroma;
int wb_vtaps_chroma; int wb_vtaps_chroma;
unsigned int wb_htaps;
unsigned int wb_vtaps;
double wb_hratio; double wb_hratio;
double wb_vratio; double wb_vratio;
}; };
struct display_audio_params_st {
unsigned int audio_sample_rate_khz;
int audio_sample_layout;
};
struct _vcs_dpi_display_output_params_st { struct _vcs_dpi_display_output_params_st {
int dp_lanes; int dp_lanes;
double output_bpp; double output_bpp;
...@@ -313,6 +435,11 @@ struct _vcs_dpi_display_output_params_st { ...@@ -313,6 +435,11 @@ struct _vcs_dpi_display_output_params_st {
int dsc_slices; int dsc_slices;
int max_audio_sample_rate; int max_audio_sample_rate;
struct writeback_st wb; struct writeback_st wb;
struct display_audio_params_st audio;
unsigned int output_bpc;
int dp_rate;
unsigned int dp_multistream_id;
bool dp_multistream_en;
}; };
struct _vcs_dpi_scaler_ratio_depth_st { struct _vcs_dpi_scaler_ratio_depth_st {
...@@ -361,6 +488,8 @@ struct _vcs_dpi_display_pipe_dest_params_st { ...@@ -361,6 +488,8 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned char use_maximum_vstartup; unsigned char use_maximum_vstartup;
unsigned int vtotal_max; unsigned int vtotal_max;
unsigned int vtotal_min; unsigned int vtotal_min;
unsigned int refresh_rate;
bool synchronize_timings;
}; };
struct _vcs_dpi_display_pipe_params_st { struct _vcs_dpi_display_pipe_params_st {
...@@ -558,6 +687,9 @@ struct _vcs_dpi_display_arb_params_st { ...@@ -558,6 +687,9 @@ struct _vcs_dpi_display_arb_params_st {
int max_req_outstanding; int max_req_outstanding;
int min_req_outstanding; int min_req_outstanding;
int sat_level_us; int sat_level_us;
int hvm_min_req_outstand_commit_threshold;
int hvm_max_qos_commit_threshold;
int compbuf_reserved_space_kbytes;
}; };
#endif /*__DISPLAY_MODE_STRUCTS_H__*/ #endif /*__DISPLAY_MODE_STRUCTS_H__*/
...@@ -23,7 +23,6 @@ ...@@ -23,7 +23,6 @@
* *
*/ */
#include "dml_wrapper.h"
#include "resource.h" #include "resource.h"
#include "core_types.h" #include "core_types.h"
#include "dsc.h" #include "dsc.h"
...@@ -86,25 +85,6 @@ static void get_pixel_clock_parameters( ...@@ -86,25 +85,6 @@ static void get_pixel_clock_parameters(
} }
static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
{
get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
if (pipe_ctx->clock_source)
pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
pipe_ctx->clock_source,
&pipe_ctx->stream_res.pix_clk_params,
&pipe_ctx->pll_settings);
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
&pipe_ctx->stream->bit_depth_params);
build_clamping_params(pipe_ctx->stream);
return DC_OK;
}
static void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, static void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
struct bit_depth_reduction_params *fmt_bit_depth) struct bit_depth_reduction_params *fmt_bit_depth)
{ {
...@@ -231,6 +211,30 @@ static void resource_build_bit_depth_reduction_params(struct dc_stream_state *st ...@@ -231,6 +211,30 @@ static void resource_build_bit_depth_reduction_params(struct dc_stream_state *st
fmt_bit_depth->pixel_encoding = pixel_encoding; fmt_bit_depth->pixel_encoding = pixel_encoding;
} }
/* Move this after the above function as VS complains about
* declaration issues for resource_build_bit_depth_reduction_params.
*/
static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
{
get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
if (pipe_ctx->clock_source)
pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
pipe_ctx->clock_source,
&pipe_ctx->stream_res.pix_clk_params,
&pipe_ctx->pll_settings);
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
&pipe_ctx->stream->bit_depth_params);
build_clamping_params(pipe_ctx->stream);
return DC_OK;
}
bool dml_validate_dsc(struct dc *dc, struct dc_state *new_ctx) bool dml_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
{ {
int i; int i;
...@@ -1130,7 +1134,7 @@ static int dml_populate_dml_pipes_from_context( ...@@ -1130,7 +1134,7 @@ static int dml_populate_dml_pipes_from_context(
{ {
int i, pipe_cnt; int i, pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx; struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe; struct pipe_ctx *pipe = NULL; // Fix potentially uninitialized error from VS
populate_dml_pipes_from_context_base(dc, context, pipes, fast_validate); populate_dml_pipes_from_context_base(dc, context, pipes, fast_validate);
...@@ -1296,6 +1300,7 @@ static void dml_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) ...@@ -1296,6 +1300,7 @@ static void dml_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
} }
} }
...@@ -1593,11 +1598,8 @@ static void dml_calculate_dlg_params( ...@@ -1593,11 +1598,8 @@ static void dml_calculate_dlg_params(
context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW; context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
*/ */
context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
/* TODO : Uncomment the below line and make changes context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support =
* as per DML nomenclature once it is available. context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
* context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = context->bw_ctx.dml.vba.fclk_pstate_support;
*/
if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
...@@ -1699,12 +1701,11 @@ static void dml_calculate_wm_and_dlg( ...@@ -1699,12 +1701,11 @@ static void dml_calculate_wm_and_dlg(
context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
//context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; //context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */ /* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 4; //context->bw_ctx.bw.dcn.watermarks.b.usr_retraining = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
/* Set D: /* Set D:
* All clocks min. * All clocks min.
...@@ -1736,13 +1737,11 @@ static void dml_calculate_wm_and_dlg( ...@@ -1736,13 +1737,11 @@ static void dml_calculate_wm_and_dlg(
context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
//context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; //context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */ /* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 4; //context->bw_ctx.bw.dcn.watermarks.d.usr_retraining = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
/* Set C, for Dummy P-State: /* Set C, for Dummy P-State:
* All clocks min. * All clocks min.
* DCFCLK: Min, as reported by PM FW, when available * DCFCLK: Min, as reported by PM FW, when available
...@@ -1773,13 +1772,11 @@ static void dml_calculate_wm_and_dlg( ...@@ -1773,13 +1772,11 @@ static void dml_calculate_wm_and_dlg(
context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
//context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; //context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */ /* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 4; //context->bw_ctx.bw.dcn.watermarks.c.usr_retraining = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
/* The only difference between A and C is p-state latency, if p-state is not supported /* The only difference between A and C is p-state latency, if p-state is not supported
* with full p-state latency we want to calculate DLG based on dummy p-state latency, * with full p-state latency we want to calculate DLG based on dummy p-state latency,
......
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