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Commit de9b1214 authored by Nicolin Chen's avatar Nicolin Chen Committed by Mark Brown
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ASoC: cs53l30: Add codec driver support for Cirrus CS53L30 

CS53L30 is a Quad-Channel ADC from Cirrus Logic with an I2S/TDM DAI.
So this patch adds a codec driver for CS53L30 that includes 4-channel
24-bit recording and TDM mode supports.
Signed-off-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1a695a90
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Documentation/devicetree/bindings/sound/cs53l30.txt 0 → 100644
View file @ de9b1214
CS53L30 audio CODEC
Required properties:
- compatible : "cirrus,cs53l30"
- reg : the I2C address of the device
- VA-supply, VP-supply : power supplies for the device,
as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
Optional properties:
- reset-gpios : a GPIO spec for the reset pin.
- cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin.
0 = Hi-Z
1 = 1.80 V
2 = 2.75 V
- cirrus,use-sdout2 : This is a boolean property. If present, it indicates
the hardware design connects both SDOUT1 and SDOUT2
pins to output data. Otherwise, it indicates that
only SDOUT1 is connected for data output.
* CS53l30 supports 4-channel data output in the same
* frame using two different ways:
* 1) Normal I2S mode on two data pins -- each SDOUT
* carries 2-channel data in the same time.
* 2) TDM mode on one signle data pin -- SDOUT1 carries
* 4-channel data per frame.
Example:
codec: cs53l30@48 {
compatible = "cirrus,cs53l30";
reg = <0x48>;
reset-gpios = <&gpio 54 0>;
VA-supply = <&cs53l30_va>;
VP-supply = <&cs53l30_vp>;
};
sound/soc/codecs/Kconfig
View file @ de9b1214
......@@ -57,6 +57,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS42XX8_I2C if I2C
select SND_SOC_CS4349 if I2C
select SND_SOC_CS47L24 if MFD_CS47L24
select SND_SOC_CS53L30 if I2C
select SND_SOC_CX20442 if TTY
select SND_SOC_DA7210 if SND_SOC_I2C_AND_SPI
select SND_SOC_DA7213 if I2C
......@@ -450,6 +451,11 @@ config SND_SOC_CS4349
config SND_SOC_CS47L24
tristate
# Cirrus Logic Quad-Channel ADC
config SND_SOC_CS53L30
tristate "Cirrus Logic CS53L30 CODEC"
depends on I2C
config SND_SOC_CX20442
tristate
depends on TTY
......
sound/soc/codecs/Makefile
View file @ de9b1214
......@@ -49,6 +49,7 @@ snd-soc-cs42xx8-objs := cs42xx8.o
snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
snd-soc-cs4349-objs := cs4349.o
snd-soc-cs47l24-objs := cs47l24.o
snd-soc-cs53l30-objs := cs53l30.o
snd-soc-cx20442-objs := cx20442.o
snd-soc-da7210-objs := da7210.o
snd-soc-da7213-objs := da7213.o
......@@ -264,6 +265,7 @@ obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o
obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o
......
sound/soc/codecs/cs53l30.c 0 → 100644
View file @ de9b1214
/*
* cs53l30.c -- CS53l30 ALSA Soc Audio driver
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Authors: Paul Handrigan <Paul.Handrigan@cirrus.com>,
* Tim Howe <Tim.Howe@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "cs53l30.h"
#define CS53L30_NUM_SUPPLIES 2
static const char *const cs53l30_supply_names[CS53L30_NUM_SUPPLIES] = {
"VA",
"VP",
};
struct cs53l30_private {
struct regulator_bulk_data supplies[CS53L30_NUM_SUPPLIES];
struct regmap *regmap;
struct gpio_desc *reset_gpio;
struct clk *mclk;
bool use_sdout2;
u32 mclk_rate;
};
static const struct reg_default cs53l30_reg_defaults[] = {
{ CS53L30_PWRCTL, CS53L30_PWRCTL_DEFAULT },
{ CS53L30_MCLKCTL, CS53L30_MCLKCTL_DEFAULT },
{ CS53L30_INT_SR_CTL, CS53L30_INT_SR_CTL_DEFAULT },
{ CS53L30_MICBIAS_CTL, CS53L30_MICBIAS_CTL_DEFAULT },
{ CS53L30_ASPCFG_CTL, CS53L30_ASPCFG_CTL_DEFAULT },
{ CS53L30_ASP_CTL1, CS53L30_ASP_CTL1_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL1, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL2, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL3, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL4, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN1, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN2, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN3, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN4, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN5, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN6, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_CTL2, CS53L30_ASP_CTL2_DEFAULT },
{ CS53L30_SFT_RAMP, CS53L30_SFT_RMP_DEFAULT },
{ CS53L30_LRCK_CTL1, CS53L30_LRCK_CTLx_DEFAULT },
{ CS53L30_LRCK_CTL2, CS53L30_LRCK_CTLx_DEFAULT },
{ CS53L30_MUTEP_CTL1, CS53L30_MUTEP_CTL1_DEFAULT },
{ CS53L30_MUTEP_CTL2, CS53L30_MUTEP_CTL2_DEFAULT },
{ CS53L30_INBIAS_CTL1, CS53L30_INBIAS_CTL1_DEFAULT },
{ CS53L30_INBIAS_CTL2, CS53L30_INBIAS_CTL2_DEFAULT },
{ CS53L30_DMIC1_STR_CTL, CS53L30_DMIC1_STR_CTL_DEFAULT },
{ CS53L30_DMIC2_STR_CTL, CS53L30_DMIC2_STR_CTL_DEFAULT },
{ CS53L30_ADCDMIC1_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
{ CS53L30_ADCDMIC1_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
{ CS53L30_ADC1_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
{ CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
{ CS53L30_ADC1A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC1A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADC1B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADCDMIC2_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
{ CS53L30_ADCDMIC2_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
{ CS53L30_ADC2_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
{ CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
{ CS53L30_ADC2A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC2A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADC2B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_INT_MASK, CS53L30_DEVICE_INT_MASK },
};
static bool cs53l30_volatile_register(struct device *dev, unsigned int reg)
{
if (reg == CS53L30_IS)
return true;
else
return false;
}
static bool cs53l30_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS53L30_DEVID_AB:
case CS53L30_DEVID_CD:
case CS53L30_DEVID_E:
case CS53L30_REVID:
case CS53L30_IS:
return false;
default:
return true;
}
}
static bool cs53l30_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS53L30_DEVID_AB:
case CS53L30_DEVID_CD:
case CS53L30_DEVID_E:
case CS53L30_REVID:
case CS53L30_PWRCTL:
case CS53L30_MCLKCTL:
case CS53L30_INT_SR_CTL:
case CS53L30_MICBIAS_CTL:
case CS53L30_ASPCFG_CTL:
case CS53L30_ASP_CTL1:
case CS53L30_ASP_TDMTX_CTL1:
case CS53L30_ASP_TDMTX_CTL2:
case CS53L30_ASP_TDMTX_CTL3:
case CS53L30_ASP_TDMTX_CTL4:
case CS53L30_ASP_TDMTX_EN1:
case CS53L30_ASP_TDMTX_EN2:
case CS53L30_ASP_TDMTX_EN3:
case CS53L30_ASP_TDMTX_EN4:
case CS53L30_ASP_TDMTX_EN5:
case CS53L30_ASP_TDMTX_EN6:
case CS53L30_ASP_CTL2:
case CS53L30_SFT_RAMP:
case CS53L30_LRCK_CTL1:
case CS53L30_LRCK_CTL2:
case CS53L30_MUTEP_CTL1:
case CS53L30_MUTEP_CTL2:
case CS53L30_INBIAS_CTL1:
case CS53L30_INBIAS_CTL2:
case CS53L30_DMIC1_STR_CTL:
case CS53L30_DMIC2_STR_CTL:
case CS53L30_ADCDMIC1_CTL1:
case CS53L30_ADCDMIC1_CTL2:
case CS53L30_ADC1_CTL3:
case CS53L30_ADC1_NG_CTL:
case CS53L30_ADC1A_AFE_CTL:
case CS53L30_ADC1B_AFE_CTL:
case CS53L30_ADC1A_DIG_VOL:
case CS53L30_ADC1B_DIG_VOL:
case CS53L30_ADCDMIC2_CTL1:
case CS53L30_ADCDMIC2_CTL2:
case CS53L30_ADC2_CTL3:
case CS53L30_ADC2_NG_CTL:
case CS53L30_ADC2A_AFE_CTL:
case CS53L30_ADC2B_AFE_CTL:
case CS53L30_ADC2A_DIG_VOL:
case CS53L30_ADC2B_DIG_VOL:
case CS53L30_INT_MASK:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0);
static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0);
static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1);
static DECLARE_TLV_DB_SCALE(pga_preamp_tlv, 0, 10000, 0);
static const char * const input1_sel_text[] = {
"DMIC1 On AB In",
"DMIC1 On A In",
"DMIC1 On B In",
"ADC1 On AB In",
"ADC1 On A In",
"ADC1 On B In",
"DMIC1 Off ADC1 Off",
};
unsigned int const input1_sel_values[] = {
CS53L30_CH_TYPE,
CS53L30_ADCxB_PDN | CS53L30_CH_TYPE,
CS53L30_ADCxA_PDN | CS53L30_CH_TYPE,
CS53L30_DMICx_PDN,
CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
};
static const char * const input2_sel_text[] = {
"DMIC2 On AB In",
"DMIC2 On A In",
"DMIC2 On B In",
"ADC2 On AB In",
"ADC2 On A In",
"ADC2 On B In",
"DMIC2 Off ADC2 Off",
};
unsigned int const input2_sel_values[] = {
0x0,
CS53L30_ADCxB_PDN,
CS53L30_ADCxA_PDN,
CS53L30_DMICx_PDN,
CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
};
static const char * const input1_route_sel_text[] = {
"ADC1_SEL", "DMIC1_SEL",
};
static const struct soc_enum input1_route_sel_enum =
SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, CS53L30_CH_TYPE_SHIFT,
ARRAY_SIZE(input1_route_sel_text),
input1_route_sel_text);
static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0,
CS53L30_ADCDMICx_PDN_MASK, input1_sel_text,
input1_sel_values);
static const struct snd_kcontrol_new input1_route_sel_mux =
SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum);
static const char * const input2_route_sel_text[] = {
"ADC2_SEL", "DMIC2_SEL",
};
/* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */
static const struct soc_enum input2_route_sel_enum =
SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0,
ARRAY_SIZE(input2_route_sel_text),
input2_route_sel_text);
static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0,
CS53L30_ADCDMICx_PDN_MASK, input2_sel_text,
input2_sel_values);
static const struct snd_kcontrol_new input2_route_sel_mux =
SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum);
/*
* TB = 6144*(MCLK(int) scaling factor)/MCLK(internal)
* TB - Time base
* NOTE: If MCLK_INT_SCALE = 0, then TB=1
*/
static const char * const cs53l30_ng_delay_text[] = {
"TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms",
};
static const struct soc_enum adc1_ng_delay_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
ARRAY_SIZE(cs53l30_ng_delay_text),
cs53l30_ng_delay_text);
static const struct soc_enum adc2_ng_delay_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
ARRAY_SIZE(cs53l30_ng_delay_text),
cs53l30_ng_delay_text);
/* The noise gate threshold selected will depend on NG Boost */
static const char * const cs53l30_ng_thres_text[] = {
"-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB",
"-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB",
};
static const struct soc_enum adc1_ng_thres_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
ARRAY_SIZE(cs53l30_ng_thres_text),
cs53l30_ng_thres_text);
static const struct soc_enum adc2_ng_thres_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
ARRAY_SIZE(cs53l30_ng_thres_text),
cs53l30_ng_thres_text);
/* Corner frequencies are with an Fs of 48kHz. */
static const char * const hpf_corner_freq_text[] = {
"1.86Hz", "120Hz", "235Hz", "466Hz",
};
static const struct soc_enum adc1_hpf_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
static const struct soc_enum adc2_hpf_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
static const struct snd_kcontrol_new cs53l30_snd_controls[] = {
SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP,
CS53L30_DIGSFT_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Noise Gate Ganging Switch", CS53L30_ADC1_CTL3,
CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
SOC_SINGLE("ADC2 Noise Gate Ganging Switch", CS53L30_ADC2_CTL3,
CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
SOC_SINGLE("ADC1A Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
CS53L30_ADCxA_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC1B Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
CS53L30_ADCxB_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC2A Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
CS53L30_ADCxA_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC2B Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
CS53L30_ADCxB_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Notch Filter Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
SOC_SINGLE("ADC2 Notch Filter Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
SOC_SINGLE("ADC1A Invert Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxA_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC1B Invert Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxB_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC2A Invert Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxA_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC2B Invert Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxB_INV_SHIFT, 1, 0),
SOC_SINGLE_TLV("ADC1A Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC1B Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC2A Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC2B Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC1 NG Boost Volume", CS53L30_ADC1_NG_CTL,
CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
SOC_SINGLE_TLV("ADC2 NG Boost Volume", CS53L30_ADC2_NG_CTL,
CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
SOC_DOUBLE_R_TLV("ADC1 Pre Amp Gain", CS53L30_ADC1A_AFE_CTL,
CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
2, 0, pga_preamp_tlv),
SOC_DOUBLE_R_TLV("ADC2 Pre Amp Gain", CS53L30_ADC2A_AFE_CTL,
CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
2, 0, pga_preamp_tlv),
SOC_ENUM("Input 1 Channel Select", input1_sel_enum),
SOC_ENUM("Input 2 Channel Select", input2_sel_enum),
SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum),
SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum),
SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum),
SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum),
SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum),
SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum),
SOC_SINGLE_SX_TLV("ADC1A PGA Volume",
CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
SOC_SINGLE_SX_TLV("ADC1B PGA Volume",
CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
SOC_SINGLE_SX_TLV("ADC2A PGA Volume",
CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
SOC_SINGLE_SX_TLV("ADC2B PGA Volume",
CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
SOC_SINGLE_SX_TLV("ADC1A Digital Volume",
CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC1B Digital Volume",
CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC2A Digital Volume",
CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC2B Digital Volume",
CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
};
static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1_DMIC1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_INPUT("IN3_DMIC2"),
SND_SOC_DAPM_INPUT("IN4"),
SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC1_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC2_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC3_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC4_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_AIF_OUT("ASP_SDOUT1", NULL, 0, CS53L30_ASP_CTL1,
CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT("ASP_SDOUT2", NULL, 0, CS53L30_ASP_CTL2,
CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0,
&input1_route_sel_mux),
SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0,
&input2_route_sel_mux),
SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_ADCxA_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_ADCxB_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_ADCxA_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_ADCxB_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_DMICx_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_DMICx_PDN_SHIFT, 1),
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes[] = {
/* ADC Input Paths */
{"ADC1A", NULL, "IN1_DMIC1"},
{"Input Mux 1", "ADC1_SEL", "ADC1A"},
{"ADC1B", NULL, "IN2"},
{"ADC2A", NULL, "IN3_DMIC2"},
{"Input Mux 2", "ADC2_SEL", "ADC2A"},
{"ADC2B", NULL, "IN4"},
/* MIC Bias Paths */
{"ADC1A", NULL, "MIC1 Bias"},
{"ADC1B", NULL, "MIC2 Bias"},
{"ADC2A", NULL, "MIC3 Bias"},
{"ADC2B", NULL, "MIC4 Bias"},
/* DMIC Paths */
{"DMIC1", NULL, "IN1_DMIC1"},
{"Input Mux 1", "DMIC1_SEL", "DMIC1"},
{"DMIC2", NULL, "IN3_DMIC2"},
{"Input Mux 2", "DMIC2_SEL", "DMIC2"},
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout1[] = {
/* Output Paths when using SDOUT1 only */
{"ASP_SDOUT1", NULL, "ADC1A" },
{"ASP_SDOUT1", NULL, "Input Mux 1"},
{"ASP_SDOUT1", NULL, "ADC1B"},
{"ASP_SDOUT1", NULL, "ADC2A"},
{"ASP_SDOUT1", NULL, "Input Mux 2"},
{"ASP_SDOUT1", NULL, "ADC2B"},
{"Capture", NULL, "ASP_SDOUT1"},
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout2[] = {
/* Output Paths when using both SDOUT1 and SDOUT2 */
{"ASP_SDOUT1", NULL, "ADC1A" },
{"ASP_SDOUT1", NULL, "Input Mux 1"},
{"ASP_SDOUT1", NULL, "ADC1B"},
{"ASP_SDOUT2", NULL, "ADC2A"},
{"ASP_SDOUT2", NULL, "Input Mux 2"},
{"ASP_SDOUT2", NULL, "ADC2B"},
{"Capture", NULL, "ASP_SDOUT1"},
{"Capture", NULL, "ASP_SDOUT2"},
};
struct cs53l30_mclk_div {
u32 mclk_rate;
u32 srate;
u8 asp_rate;
u8 internal_fs_ratio;
u8 mclk_int_scale;
};
static struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = {
/* NOTE: Enable MCLK_INT_SCALE to save power. */
/* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */
{5644800, 11025, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{5644800, 22050, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{5644800, 44100, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6000000, 8000, 0x1, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 11025, 0x2, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 12000, 0x4, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 16000, 0x5, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 22050, 0x6, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 24000, 0x8, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 32000, 0x9, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 44100, 0xA, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 48000, 0xC, 0, CS53L30_MCLK_INT_SCALE},
{6144000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
};
struct cs53l30_mclkx_div {
u32 mclkx;
u8 ratio;
u8 mclkdiv;
};
static struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = {
{5644800, 1, CS53L30_MCLK_DIV_BY_1},
{6000000, 1, CS53L30_MCLK_DIV_BY_1},
{6144000, 1, CS53L30_MCLK_DIV_BY_1},
{11289600, 2, CS53L30_MCLK_DIV_BY_2},
{12288000, 2, CS53L30_MCLK_DIV_BY_2},
{12000000, 2, CS53L30_MCLK_DIV_BY_2},
{19200000, 3, CS53L30_MCLK_DIV_BY_3},
};
static int cs53l30_get_mclkx_coeff(int mclkx)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) {
if (cs53l30_mclkx_coeffs[i].mclkx == mclkx)
return i;
}
return -EINVAL;
}
static int cs53l30_get_mclk_coeff(int mclk_rate, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) {
if (cs53l30_mclk_coeffs[i].mclk_rate == mclk_rate &&
cs53l30_mclk_coeffs[i].srate == srate)
return i;
}
return -EINVAL;
}
static int cs53l30_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
int mclkx_coeff;
u32 mclk_rate;
/* MCLKX -> MCLK */
mclkx_coeff = cs53l30_get_mclkx_coeff(freq);
if (mclkx_coeff < 0)
return mclkx_coeff;
mclk_rate = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx /
cs53l30_mclkx_coeffs[mclkx_coeff].ratio;
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIV_MASK,
cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv);
priv->mclk_rate = mclk_rate;
return 0;
}
static int cs53l30_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
u8 aspcfg = 0, aspctl1 = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aspcfg |= CS53L30_ASP_MS;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* Set TDM_PDN to turn off TDM mode -- Reset default */
aspctl1 |= CS53L30_ASP_TDM_PDN;
break;
case SND_SOC_DAIFMT_DSP_A:
/* Clear TDM_PDN and SHIFT_LEFT, invert SCLK */
aspcfg |= CS53L30_ASP_SCLK_INV;
break;
default:
return -EINVAL;
}
/* Check to see if the SCLK is inverted */
if (fmt & (SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_IB_IF))
aspcfg ^= CS53L30_ASP_SCLK_INV;
regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
CS53L30_ASP_MS | CS53L30_ASP_SCLK_INV, aspcfg);
regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
CS53L30_ASP_TDM_PDN | CS53L30_SHIFT_LEFT, aspctl1);
return 0;
}
static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
int srate = params_rate(params);
int mclk_coeff;
/* MCLK -> srate */
mclk_coeff = cs53l30_get_mclk_coeff(priv->mclk_rate, srate);
if (mclk_coeff < 0)
return -EINVAL;
regmap_update_bits(priv->regmap, CS53L30_INT_SR_CTL,
CS53L30_INTRNL_FS_RATIO_MASK,
cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio);
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_INT_SCALE_MASK,
cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale);
regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
CS53L30_ASP_RATE_MASK,
cs53l30_mclk_coeffs[mclk_coeff].asp_rate);
return 0;
}
static int cs53l30_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec);
unsigned int reg;
int i, inter_max_check, ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY)
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_LP_MASK, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (dapm->bias_level == SND_SOC_BIAS_OFF) {
ret = clk_prepare_enable(priv->mclk);
if (ret) {
dev_err(codec->dev,
"failed to enable MCLK: %d\n", ret);
return ret;
}
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIS_MASK, 0);
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK, 0);
msleep(50);
} else {
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK,
CS53L30_PDN_ULP);
}
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
CS53L30_PDN_DONE, 0);
/*
* If digital softramp is set, the amount of time required
* for power down increases and depends on the digital
* volume setting.
*/
/* Set the max possible time if digsft is set */
regmap_read(priv->regmap, CS53L30_SFT_RAMP, &reg);
if (reg & CS53L30_DIGSFT_MASK)
inter_max_check = CS53L30_PDN_POLL_MAX;
else
inter_max_check = 10;
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK,
CS53L30_PDN_ULP);
/* PDN_DONE will take a min of 20ms to be set.*/
msleep(20);
/* Clr status */
regmap_read(priv->regmap, CS53L30_IS, &reg);
for (i = 0; i < inter_max_check; i++) {
if (inter_max_check < 10) {
usleep_range(1000, 1100);
regmap_read(priv->regmap, CS53L30_IS, &reg);
if (reg & CS53L30_PDN_DONE)
break;
} else {
usleep_range(10000, 10100);
regmap_read(priv->regmap, CS53L30_IS, &reg);
if (reg & CS53L30_PDN_DONE)
break;
}
}
/* PDN_DONE is set. We now can disable the MCLK */
regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
CS53L30_PDN_DONE, CS53L30_PDN_DONE);
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIS_MASK,
CS53L30_MCLK_DIS);
clk_disable_unprepare(priv->mclk);
break;
}
return 0;
}
static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
u8 val = tristate ? CS53L30_ASP_3ST : 0;
return regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
CS53L30_ASP_3ST_MASK, val);
}
unsigned int const cs53l30_src_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
};
static struct snd_pcm_hw_constraint_list src_constraints = {
.count = ARRAY_SIZE(cs53l30_src_rates),
.list = cs53l30_src_rates,
};
static int cs53l30_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &src_constraints);
return 0;
}
/*
* Note: CS53L30 counts the slot number per byte while ASoC counts the slot
* number per slot_width. So there is a difference between the slots of ASoC
* and the slots of CS53L30.
*/
static int cs53l30_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
unsigned int loc[CS53L30_TDM_SLOT_MAX] = {48, 48, 48, 48};
unsigned int slot_next, slot_step;
u64 tx_enable = 0;
int i;
if (!rx_mask) {
dev_err(dai->dev, "rx masks must not be 0\n");
return -EINVAL;
}
/* Assuming slot_width is not supposed to be greater than 64 */
if (slots <= 0 || slot_width <= 0 || slot_width > 64) {
dev_err(dai->dev, "invalid slot number or slot width\n");
return -EINVAL;
}
if (slot_width & 0x7) {
dev_err(dai->dev, "slot width must count in byte\n");
return -EINVAL;
}
/* How many bytes in each ASoC slot */
slot_step = slot_width >> 3;
for (i = 0; rx_mask && i < CS53L30_TDM_SLOT_MAX; i++) {
/* Find the first slot from LSB */
slot_next = __ffs(rx_mask);
/* Save the slot location by converting to CS53L30 slot */
loc[i] = slot_next * slot_step;
/* Create the mask of CS53L30 slot */
tx_enable |= (u64)((u64)(1 << slot_step) - 1) << (u64)loc[i];
/* Clear this slot from rx_mask */
rx_mask &= ~(1 << slot_next);
}
/* Error out to avoid slot shift */
if (rx_mask && i == CS53L30_TDM_SLOT_MAX) {
dev_err(dai->dev, "rx_mask exceeds max slot number: %d\n",
CS53L30_TDM_SLOT_MAX);
return -EINVAL;
}
/* Validate the last CS53L30 slot */
slot_next = loc[CS53L30_TDM_SLOT_MAX - 1] + slot_step - 1;
if (slot_next > 47) {
dev_err(dai->dev, "slot selection out of bounds: %u\n",
slot_next);
return -EINVAL;
}
for (i = 0; i < CS53L30_TDM_SLOT_MAX && loc[i] != 48; i++) {
regmap_update_bits(priv->regmap, CS53L30_ASP_TDMTX_CTL(i),
CS53L30_ASP_CHx_TX_LOC_MASK, loc[i]);
dev_dbg(dai->dev, "loc[%d]=%x\n", i, loc[i]);
}
for (i = 0; i < CS53L30_ASP_TDMTX_ENx_MAX && tx_enable; i++) {
regmap_write(priv->regmap, CS53L30_ASP_TDMTX_ENx(i),
tx_enable & 0xff);
tx_enable >>= 8;
dev_dbg(dai->dev, "en_reg=%x, tx_enable=%llx\n",
CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff);
}
return 0;
}
/* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
#define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
#define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops cs53l30_ops = {
.startup = cs53l30_pcm_startup,
.hw_params = cs53l30_pcm_hw_params,
.set_fmt = cs53l30_set_dai_fmt,
.set_sysclk = cs53l30_set_sysclk,
.set_tristate = cs53l30_set_tristate,
.set_tdm_slot = cs53l30_set_dai_tdm_slot,
};
static struct snd_soc_dai_driver cs53l30_dai = {
.name = "cs53l30",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = CS53L30_RATES,
.formats = CS53L30_FORMATS,
},
.ops = &cs53l30_ops,
.symmetric_rates = 1,
};
static int cs53l30_codec_probe(struct snd_soc_codec *codec)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec);
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
if (priv->use_sdout2)
snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout2,
ARRAY_SIZE(cs53l30_dapm_routes_sdout2));
else
snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout1,
ARRAY_SIZE(cs53l30_dapm_routes_sdout1));
return 0;
}
static struct snd_soc_codec_driver cs53l30_driver = {
.probe = cs53l30_codec_probe,
.set_bias_level = cs53l30_set_bias_level,
.dapm_widgets = cs53l30_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets),
.dapm_routes = cs53l30_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs53l30_dapm_routes),
.controls = cs53l30_snd_controls,
.num_controls = ARRAY_SIZE(cs53l30_snd_controls),
};
static struct regmap_config cs53l30_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS53L30_MAX_REGISTER,
.reg_defaults = cs53l30_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults),
.volatile_reg = cs53l30_volatile_register,
.writeable_reg = cs53l30_writeable_register,
.readable_reg = cs53l30_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int cs53l30_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
const struct device_node *np = client->dev.of_node;
struct device *dev = &client->dev;
struct cs53l30_private *cs53l30;
unsigned int devid = 0;
unsigned int reg;
int ret = 0, i;
u8 val;
cs53l30 = devm_kzalloc(dev, sizeof(*cs53l30), GFP_KERNEL);
if (!cs53l30)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(cs53l30->supplies); i++)
cs53l30->supplies[i].supply = cs53l30_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
/* Reset the Device */
cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs53l30->reset_gpio)) {
ret = PTR_ERR(cs53l30->reset_gpio);
goto error;
}
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
i2c_set_clientdata(client, cs53l30);
cs53l30->mclk_rate = 0;
cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap);
if (IS_ERR(cs53l30->regmap)) {
ret = PTR_ERR(cs53l30->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
goto error;
}
/* Initialize codec */
ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, &reg);
devid = reg << 12;
ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, &reg);
devid |= reg << 4;
ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, &reg);
devid |= (reg & 0xF0) >> 4;
if (devid != CS53L30_DEVID) {
ret = -ENODEV;
dev_err(dev, "Device ID (%X). Expected %X\n",
devid, CS53L30_DEVID);
goto error;
}
ret = regmap_read(cs53l30->regmap, CS53L30_REVID, &reg);
if (ret < 0) {
dev_err(dev, "failed to get Revision ID: %d\n", ret);
goto error;
}
/* Check if MCLK provided */
cs53l30->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(cs53l30->mclk)) {
if (PTR_ERR(cs53l30->mclk) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto error;
}
/* Otherwise mark the mclk pointer to NULL */
cs53l30->mclk = NULL;
}
if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val))
regmap_update_bits(cs53l30->regmap, CS53L30_MICBIAS_CTL,
CS53L30_MIC_BIAS_CTRL_MASK, val);
if (of_property_read_bool(np, "cirrus,use-sdout2"))
cs53l30->use_sdout2 = true;
dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF);
ret = snd_soc_register_codec(dev, &cs53l30_driver, &cs53l30_dai, 1);
if (ret) {
dev_err(dev, "failed to register codec: %d\n", ret);
goto error;
}
return 0;
error:
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return ret;
}
static int cs53l30_i2c_remove(struct i2c_client *client)
{
struct cs53l30_private *cs53l30 = i2c_get_clientdata(client);
snd_soc_unregister_codec(&client->dev);
/* Hold down reset */
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return 0;
}
#ifdef CONFIG_PM
static int cs53l30_runtime_suspend(struct device *dev)
{
struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
regcache_cache_only(cs53l30->regmap, true);
/* Hold down reset */
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return 0;
}
static int cs53l30_runtime_resume(struct device *dev)
{
struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
regcache_cache_only(cs53l30->regmap, false);
regcache_sync(cs53l30->regmap);
return 0;
}
#endif
static const struct dev_pm_ops cs53l30_runtime_pm = {
SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume,
NULL)
};
static const struct of_device_id cs53l30_of_match[] = {
{ .compatible = "cirrus,cs53l30", },
{},
};
MODULE_DEVICE_TABLE(of, cs53l30_of_match);
static const struct i2c_device_id cs53l30_id[] = {
{ "cs53l30", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs53l30_id);
static struct i2c_driver cs53l30_i2c_driver = {
.driver = {
.name = "cs53l30",
.pm = &cs53l30_runtime_pm,
},
.id_table = cs53l30_id,
.probe = cs53l30_i2c_probe,
.remove = cs53l30_i2c_remove,
};
module_i2c_driver(cs53l30_i2c_driver);
MODULE_DESCRIPTION("ASoC CS53L30 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/cs53l30.h 0 → 100644
View file @ de9b1214
/*
* ALSA SoC CS53L30 codec driver
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Author: Paul Handrigan <Paul.Handrigan@cirrus.com>,
* Tim Howe <Tim.Howe@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __CS53L30_H__
#define __CS53L30_H__
/* I2C Registers */
#define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */
#define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */
#define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */
#define CS53L30_REVID 0x05 /* Revision ID [RO]. */
#define CS53L30_PWRCTL 0x06 /* Power Control. */
#define CS53L30_MCLKCTL 0x07 /* MCLK Control. */
#define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */
#define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */
#define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */
#define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */
#define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */
#define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */
#define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */
#define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */
#define CS53L30_ASP_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */
#define CS53L30_ASP_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */
#define CS53L30_ASP_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */
#define CS53L30_ASP_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */
#define CS53L30_ASP_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */
#define CS53L30_ASP_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */
#define CS53L30_ASP_CTL2 0x18 /* ASP2 Control. */
#define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */
#define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */
#define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */
#define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */
#define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */
#define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */
#define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */
#define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */
#define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */
#define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */
#define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */
#define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */
#define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */
#define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */
#define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */
#define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */
#define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */
#define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */
#define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */
#define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */
#define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */
#define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */
#define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */
#define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */
#define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */
#define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */
#define CS53L30_IS 0x36 /* Interrupt Status. */
#define CS53L30_MAX_REGISTER 0x36
#define CS53L30_TDM_SLOT_MAX 4
#define CS53L30_ASP_TDMTX_CTL(x) (CS53L30_ASP_TDMTX_CTL1 + (x))
/* x : index for registers; n : index for slot; 8 slots per register */
#define CS53L30_ASP_TDMTX_ENx(x) (CS53L30_ASP_TDMTX_EN6 - (x))
#define CS53L30_ASP_TDMTX_ENn(n) CS53L30_ASP_TDMTX_ENx((n) >> 3)
#define CS53L30_ASP_TDMTX_ENx_MAX 6
/* Device ID */
#define CS53L30_DEVID 0x53A30
/* PDN_DONE Poll Maximum
* If soft ramp is set it will take much longer to power down
* the system.
*/
#define CS53L30_PDN_POLL_MAX 90
/* Bitfield Definitions */
/* R6 (0x06) CS53L30_PWRCTL - Power Control */
#define CS53L30_PDN_ULP_SHIFT 7
#define CS53L30_PDN_ULP_MASK (1 << CS53L30_PDN_ULP_SHIFT)
#define CS53L30_PDN_ULP (1 << CS53L30_PDN_ULP_SHIFT)
#define CS53L30_PDN_LP_SHIFT 6
#define CS53L30_PDN_LP_MASK (1 << CS53L30_PDN_LP_SHIFT)
#define CS53L30_PDN_LP (1 << CS53L30_PDN_LP_SHIFT)
#define CS53L30_DISCHARGE_FILT_SHIFT 5
#define CS53L30_DISCHARGE_FILT_MASK (1 << CS53L30_DISCHARGE_FILT_SHIFT)
#define CS53L30_DISCHARGE_FILT (1 << CS53L30_DISCHARGE_FILT_SHIFT)
#define CS53L30_THMS_PDN_SHIFT 4
#define CS53L30_THMS_PDN_MASK (1 << CS53L30_THMS_PDN_SHIFT)
#define CS53L30_THMS_PDN (1 << CS53L30_THMS_PDN_SHIFT)
#define CS53L30_PWRCTL_DEFAULT (CS53L30_THMS_PDN)
/* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */
#define CS53L30_MCLK_DIS_SHIFT 7
#define CS53L30_MCLK_DIS_MASK (1 << CS53L30_MCLK_DIS_SHIFT)
#define CS53L30_MCLK_DIS (1 << CS53L30_MCLK_DIS_SHIFT)
#define CS53L30_MCLK_INT_SCALE_SHIFT 6
#define CS53L30_MCLK_INT_SCALE_MASK (1 << CS53L30_MCLK_INT_SCALE_SHIFT)
#define CS53L30_MCLK_INT_SCALE (1 << CS53L30_MCLK_INT_SCALE_SHIFT)
#define CS53L30_DMIC_DRIVE_SHIFT 5
#define CS53L30_DMIC_DRIVE_MASK (1 << CS53L30_DMIC_DRIVE_SHIFT)
#define CS53L30_DMIC_DRIVE (1 << CS53L30_DMIC_DRIVE_SHIFT)
#define CS53L30_MCLK_DIV_SHIFT 2
#define CS53L30_MCLK_DIV_WIDTH 2
#define CS53L30_MCLK_DIV_MASK (((1 << CS53L30_MCLK_DIV_WIDTH) - 1) << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_MCLK_DIV_BY_1 (0x0 << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_MCLK_DIV_BY_2 (0x1 << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_MCLK_DIV_BY_3 (0x2 << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_SYNC_EN_SHIFT 1
#define CS53L30_SYNC_EN_MASK (1 << CS53L30_SYNC_EN_SHIFT)
#define CS53L30_SYNC_EN (1 << CS53L30_SYNC_EN_SHIFT)
#define CS53L30_MCLKCTL_DEFAULT (CS53L30_MCLK_DIV_BY_2)
/* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */
#define CS53L30_INTRNL_FS_RATIO_SHIFT 4
#define CS53L30_INTRNL_FS_RATIO_MASK (1 << CS53L30_INTRNL_FS_RATIO_SHIFT)
#define CS53L30_INTRNL_FS_RATIO (1 << CS53L30_INTRNL_FS_RATIO_SHIFT)
#define CS53L30_MCLK_19MHZ_EN_SHIFT 0
#define CS53L30_MCLK_19MHZ_EN_MASK (1 << CS53L30_MCLK_19MHZ_EN_SHIFT)
#define CS53L30_MCLK_19MHZ_EN (1 << CS53L30_MCLK_19MHZ_EN_SHIFT)
/* 0x6 << 1 is reserved bits */
#define CS53L30_INT_SR_CTL_DEFAULT (CS53L30_INTRNL_FS_RATIO | 0x6 << 1)
/* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */
#define CS53L30_MIC4_BIAS_PDN_SHIFT 7
#define CS53L30_MIC4_BIAS_PDN_MASK (1 << CS53L30_MIC4_BIAS_PDN_SHIFT)
#define CS53L30_MIC4_BIAS_PDN (1 << CS53L30_MIC4_BIAS_PDN_SHIFT)
#define CS53L30_MIC3_BIAS_PDN_SHIFT 6
#define CS53L30_MIC3_BIAS_PDN_MASK (1 << CS53L30_MIC3_BIAS_PDN_SHIFT)
#define CS53L30_MIC3_BIAS_PDN (1 << CS53L30_MIC3_BIAS_PDN_SHIFT)
#define CS53L30_MIC2_BIAS_PDN_SHIFT 5
#define CS53L30_MIC2_BIAS_PDN_MASK (1 << CS53L30_MIC2_BIAS_PDN_SHIFT)
#define CS53L30_MIC2_BIAS_PDN (1 << CS53L30_MIC2_BIAS_PDN_SHIFT)
#define CS53L30_MIC1_BIAS_PDN_SHIFT 4
#define CS53L30_MIC1_BIAS_PDN_MASK (1 << CS53L30_MIC1_BIAS_PDN_SHIFT)
#define CS53L30_MIC1_BIAS_PDN (1 << CS53L30_MIC1_BIAS_PDN_SHIFT)
#define CS53L30_MICx_BIAS_PDN (0xf << CS53L30_MIC1_BIAS_PDN_SHIFT)
#define CS53L30_VP_MIN_SHIFT 2
#define CS53L30_VP_MIN_MASK (1 << CS53L30_VP_MIN_SHIFT)
#define CS53L30_VP_MIN (1 << CS53L30_VP_MIN_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_SHIFT 0
#define CS53L30_MIC_BIAS_CTRL_WIDTH 2
#define CS53L30_MIC_BIAS_CTRL_MASK (((1 << CS53L30_MIC_BIAS_CTRL_WIDTH) - 1) << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_HIZ (0 << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_1V8 (1 << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_2V75 (2 << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MICBIAS_CTL_DEFAULT (CS53L30_MICx_BIAS_PDN | CS53L30_VP_MIN)
/* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */
#define CS53L30_ASP_MS_SHIFT 7
#define CS53L30_ASP_MS_MASK (1 << CS53L30_ASP_MS_SHIFT)
#define CS53L30_ASP_MS (1 << CS53L30_ASP_MS_SHIFT)
#define CS53L30_ASP_SCLK_INV_SHIFT 4
#define CS53L30_ASP_SCLK_INV_MASK (1 << CS53L30_ASP_SCLK_INV_SHIFT)
#define CS53L30_ASP_SCLK_INV (1 << CS53L30_ASP_SCLK_INV_SHIFT)
#define CS53L30_ASP_RATE_SHIFT 0
#define CS53L30_ASP_RATE_WIDTH 4
#define CS53L30_ASP_RATE_MASK (((1 << CS53L30_ASP_RATE_WIDTH) - 1) << CS53L30_ASP_RATE_SHIFT)
#define CS53L30_ASP_RATE_48K (0xc << CS53L30_ASP_RATE_SHIFT)
#define CS53L30_ASPCFG_CTL_DEFAULT (CS53L30_ASP_RATE_48K)
/* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */
#define CS53L30_ASP_TDM_PDN_SHIFT 7
#define CS53L30_ASP_TDM_PDN_MASK (1 << CS53L30_ASP_TDM_PDN_SHIFT)
#define CS53L30_ASP_TDM_PDN (1 << CS53L30_ASP_TDM_PDN_SHIFT)
#define CS53L30_ASP_SDOUTx_PDN_SHIFT 6
#define CS53L30_ASP_SDOUTx_PDN_MASK (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT)
#define CS53L30_ASP_SDOUTx_PDN (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT)
#define CS53L30_ASP_3ST_SHIFT 5
#define CS53L30_ASP_3ST_MASK (1 << CS53L30_ASP_3ST_SHIFT)
#define CS53L30_ASP_3ST (1 << CS53L30_ASP_3ST_SHIFT)
#define CS53L30_SHIFT_LEFT_SHIFT 4
#define CS53L30_SHIFT_LEFT_MASK (1 << CS53L30_SHIFT_LEFT_SHIFT)
#define CS53L30_SHIFT_LEFT (1 << CS53L30_SHIFT_LEFT_SHIFT)
#define CS53L30_ASP_SDOUTx_DRIVE_SHIFT 0
#define CS53L30_ASP_SDOUTx_DRIVE_MASK (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT)
#define CS53L30_ASP_SDOUTx_DRIVE (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT)
#define CS53L30_ASP_CTL1_DEFAULT (CS53L30_ASP_TDM_PDN)
#define CS53L30_ASP_CTL2_DEFAULT (0)
/* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */
#define CS53L30_ASP_CHx_TX_STATE_SHIFT 7
#define CS53L30_ASP_CHx_TX_STATE_MASK (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT)
#define CS53L30_ASP_CHx_TX_STATE (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT)
#define CS53L30_ASP_CHx_TX_LOC_SHIFT 0
#define CS53L30_ASP_CHx_TX_LOC_WIDTH 6
#define CS53L30_ASP_CHx_TX_LOC_MASK (((1 << CS53L30_ASP_CHx_TX_LOC_WIDTH) - 1) << CS53L30_ASP_CHx_TX_LOC_SHIFT)
#define CS53L30_ASP_CHx_TX_LOC_MAX (47 << CS53L30_ASP_CHx_TX_LOC_SHIFT)
#define CS53L30_ASP_CHx_TX_LOC(x) ((x) << CS53L30_ASP_CHx_TX_LOC_SHIFT)
#define CS53L30_ASP_TDMTX_CTLx_DEFAULT (CS53L30_ASP_CHx_TX_LOC_MAX)
/* R18 (0x12) ~ R23 (0x17) CS53L30_ASP_TDMTX_ENx - ASP TDM TX Enable 1~6 */
#define CS53L30_ASP_TDMTX_ENx_DEFAULT (0)
/* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */
#define CS53L30_DIGSFT_SHIFT 5
#define CS53L30_DIGSFT_MASK (1 << CS53L30_DIGSFT_SHIFT)
#define CS53L30_DIGSFT (1 << CS53L30_DIGSFT_SHIFT)
#define CS53L30_SFT_RMP_DEFAULT (0)
/* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */
#define CS53L30_LRCK_50_NPW_SHIFT 3
#define CS53L30_LRCK_50_NPW_MASK (1 << CS53L30_LRCK_50_NPW_SHIFT)
#define CS53L30_LRCK_50_NPW (1 << CS53L30_LRCK_50_NPW_SHIFT)
#define CS53L30_LRCK_TPWH_SHIFT 0
#define CS53L30_LRCK_TPWH_WIDTH 3
#define CS53L30_LRCK_TPWH_MASK (((1 << CS53L30_LRCK_TPWH_WIDTH) - 1) << CS53L30_LRCK_TPWH_SHIFT)
#define CS53L30_LRCK_TPWH(x) (((x) << CS53L30_LRCK_TPWH_SHIFT) & CS53L30_LRCK_TPWH_MASK)
#define CS53L30_LRCK_CTLx_DEFAULT (0)
/* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */
#define CS53L30_MUTE_PDN_ULP_SHIFT 7
#define CS53L30_MUTE_PDN_ULP_MASK (1 << CS53L30_MUTE_PDN_ULP_SHIFT)
#define CS53L30_MUTE_PDN_ULP (1 << CS53L30_MUTE_PDN_ULP_SHIFT)
#define CS53L30_MUTE_PDN_LP_SHIFT 6
#define CS53L30_MUTE_PDN_LP_MASK (1 << CS53L30_MUTE_PDN_LP_SHIFT)
#define CS53L30_MUTE_PDN_LP (1 << CS53L30_MUTE_PDN_LP_SHIFT)
#define CS53L30_MUTE_M4B_PDN_SHIFT 4
#define CS53L30_MUTE_M4B_PDN_MASK (1 << CS53L30_MUTE_M4B_PDN_SHIFT)
#define CS53L30_MUTE_M4B_PDN (1 << CS53L30_MUTE_M4B_PDN_SHIFT)
#define CS53L30_MUTE_M3B_PDN_SHIFT 3
#define CS53L30_MUTE_M3B_PDN_MASK (1 << CS53L30_MUTE_M3B_PDN_SHIFT)
#define CS53L30_MUTE_M3B_PDN (1 << CS53L30_MUTE_M3B_PDN_SHIFT)
#define CS53L30_MUTE_M2B_PDN_SHIFT 2
#define CS53L30_MUTE_M2B_PDN_MASK (1 << CS53L30_MUTE_M2B_PDN_SHIFT)
#define CS53L30_MUTE_M2B_PDN (1 << CS53L30_MUTE_M2B_PDN_SHIFT)
#define CS53L30_MUTE_M1B_PDN_SHIFT 1
#define CS53L30_MUTE_M1B_PDN_MASK (1 << CS53L30_MUTE_M1B_PDN_SHIFT)
#define CS53L30_MUTE_M1B_PDN (1 << CS53L30_MUTE_M1B_PDN_SHIFT)
/* Note: be careful - x starts from 0 */
#define CS53L30_MUTE_MxB_PDN_SHIFT(x) (CS53L30_MUTE_M1B_PDN_SHIFT + (x))
#define CS53L30_MUTE_MxB_PDN_MASK(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x))
#define CS53L30_MUTE_MxB_PDN(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x))
#define CS53L30_MUTE_MB_ALL_PDN_SHIFT 0
#define CS53L30_MUTE_MB_ALL_PDN_MASK (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT)
#define CS53L30_MUTE_MB_ALL_PDN (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT)
#define CS53L30_MUTEP_CTL1_DEFAULT (0)
/* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */
#define CS53L30_MUTE_PIN_POLARITY_SHIFT 7
#define CS53L30_MUTE_PIN_POLARITY_MASK (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT)
#define CS53L30_MUTE_PIN_POLARITY (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT)
#define CS53L30_MUTE_ASP_TDM_PDN_SHIFT 6
#define CS53L30_MUTE_ASP_TDM_PDN_MASK (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT)
#define CS53L30_MUTE_ASP_TDM_PDN (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT 5
#define CS53L30_MUTE_ASP_SDOUT2_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT2_PDN (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT 4
#define CS53L30_MUTE_ASP_SDOUT1_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT1_PDN (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT)
/* Note: be careful - x starts from 0 */
#define CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x) ((x) + CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUTx_PDN_MASK(x) (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x))
#define CS53L30_MUTE_ASP_SDOUTx_PDN (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x))
#define CS53L30_MUTE_ADC2B_PDN_SHIFT 3
#define CS53L30_MUTE_ADC2B_PDN_MASK (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT)
#define CS53L30_MUTE_ADC2B_PDN (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT)
#define CS53L30_MUTE_ADC2A_PDN_SHIFT 2
#define CS53L30_MUTE_ADC2A_PDN_MASK (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT)
#define CS53L30_MUTE_ADC2A_PDN (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT)
#define CS53L30_MUTE_ADC1B_PDN_SHIFT 1
#define CS53L30_MUTE_ADC1B_PDN_MASK (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT)
#define CS53L30_MUTE_ADC1B_PDN (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT)
#define CS53L30_MUTE_ADC1A_PDN_SHIFT 0
#define CS53L30_MUTE_ADC1A_PDN_MASK (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT)
#define CS53L30_MUTE_ADC1A_PDN (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT)
#define CS53L30_MUTEP_CTL2_DEFAULT (CS53L30_MUTE_PIN_POLARITY)
/* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */
#define CS53L30_IN4M_BIAS_SHIFT 6
#define CS53L30_IN4M_BIAS_WIDTH 2
#define CS53L30_IN4M_BIAS_MASK (((1 << CS53L30_IN4M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4M_BIAS_OPEN (0 << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4M_BIAS_PULL_DOWN (1 << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4M_BIAS_VCM (2 << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_SHIFT 4
#define CS53L30_IN4P_BIAS_WIDTH 2
#define CS53L30_IN4P_BIAS_MASK (((1 << CS53L30_IN4P_BIAS_WIDTH) - 1) << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_OPEN (0 << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_PULL_DOWN (1 << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_VCM (2 << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_SHIFT 2
#define CS53L30_IN3M_BIAS_WIDTH 2
#define CS53L30_IN3M_BIAS_MASK (((1 << CS53L30_IN3M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_OPEN (0 << CS53L30_IN3M_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_PULL_DOWN (1 << CS53L30_IN3M_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_VCM (2 << CS53L30_IN3M_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_SHIFT 0
#define CS53L30_IN3P_BIAS_WIDTH 2
#define CS53L30_IN3P_BIAS_MASK (((1 << CS53L30_IN3P_BIAS_WIDTH) - 1) << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_OPEN (0 << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_PULL_DOWN (1 << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_VCM (2 << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_INBIAS_CTL1_DEFAULT (CS53L30_IN4M_BIAS_VCM | CS53L30_IN4P_BIAS_VCM |\
CS53L30_IN3M_BIAS_VCM | CS53L30_IN3P_BIAS_VCM)
/* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */
#define CS53L30_IN2M_BIAS_SHIFT 6
#define CS53L30_IN2M_BIAS_WIDTH 2
#define CS53L30_IN2M_BIAS_MASK (((1 << CS53L30_IN2M_BIAS_WIDTH) - 1) << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2M_BIAS_OPEN (0 << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2M_BIAS_PULL_DOWN (1 << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2M_BIAS_VCM (2 << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_SHIFT 4
#define CS53L30_IN2P_BIAS_WIDTH 2
#define CS53L30_IN2P_BIAS_MASK (((1 << CS53L30_IN2P_BIAS_WIDTH) - 1) << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_OPEN (0 << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_PULL_DOWN (1 << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_VCM (2 << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_SHIFT 2
#define CS53L30_IN1M_BIAS_WIDTH 2
#define CS53L30_IN1M_BIAS_MASK (((1 << CS53L30_IN1M_BIAS_WIDTH) - 1) << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_OPEN (0 << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_PULL_DOWN (1 << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_VCM (2 << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_SHIFT 0
#define CS53L30_IN1P_BIAS_WIDTH 2
#define CS53L30_IN1P_BIAS_MASK (((1 << CS53L30_IN1P_BIAS_WIDTH) - 1) << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_OPEN (0 << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_PULL_DOWN (1 << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_VCM (2 << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_INBIAS_CTL2_DEFAULT (CS53L30_IN2M_BIAS_VCM | CS53L30_IN2P_BIAS_VCM |\
CS53L30_IN1M_BIAS_VCM | CS53L30_IN1P_BIAS_VCM)
/* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */
#define CS53L30_DMICx_STEREO_ENB_SHIFT 5
#define CS53L30_DMICx_STEREO_ENB_MASK (1 << CS53L30_DMICx_STEREO_ENB_SHIFT)
#define CS53L30_DMICx_STEREO_ENB (1 << CS53L30_DMICx_STEREO_ENB_SHIFT)
/* 0x88 and 0xCC are reserved bits */
#define CS53L30_DMIC1_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0x88)
#define CS53L30_DMIC2_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0xCC)
/* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */
#define CS53L30_ADCxB_PDN_SHIFT 7
#define CS53L30_ADCxB_PDN_MASK (1 << CS53L30_ADCxB_PDN_SHIFT)
#define CS53L30_ADCxB_PDN (1 << CS53L30_ADCxB_PDN_SHIFT)
#define CS53L30_ADCxA_PDN_SHIFT 6
#define CS53L30_ADCxA_PDN_MASK (1 << CS53L30_ADCxA_PDN_SHIFT)
#define CS53L30_ADCxA_PDN (1 << CS53L30_ADCxA_PDN_SHIFT)
#define CS53L30_DMICx_PDN_SHIFT 2
#define CS53L30_DMICx_PDN_MASK (1 << CS53L30_DMICx_PDN_SHIFT)
#define CS53L30_DMICx_PDN (1 << CS53L30_DMICx_PDN_SHIFT)
#define CS53L30_DMICx_SCLK_DIV_SHIFT 1
#define CS53L30_DMICx_SCLK_DIV_MASK (1 << CS53L30_DMICx_SCLK_DIV_SHIFT)
#define CS53L30_DMICx_SCLK_DIV (1 << CS53L30_DMICx_SCLK_DIV_SHIFT)
#define CS53L30_CH_TYPE_SHIFT 0
#define CS53L30_CH_TYPE_MASK (1 << CS53L30_CH_TYPE_SHIFT)
#define CS53L30_CH_TYPE (1 << CS53L30_CH_TYPE_SHIFT)
#define CS53L30_ADCDMICx_PDN_MASK 0xFF
#define CS53L30_ADCDMICx_CTL1_DEFAULT (CS53L30_DMICx_PDN)
/* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */
#define CS53L30_ADCx_NOTCH_DIS_SHIFT 7
#define CS53L30_ADCx_NOTCH_DIS_MASK (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT)
#define CS53L30_ADCx_NOTCH_DIS (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT)
#define CS53L30_ADCxB_INV_SHIFT 5
#define CS53L30_ADCxB_INV_MASK (1 << CS53L30_ADCxB_INV_SHIFT)
#define CS53L30_ADCxB_INV (1 << CS53L30_ADCxB_INV_SHIFT)
#define CS53L30_ADCxA_INV_SHIFT 4
#define CS53L30_ADCxA_INV_MASK (1 << CS53L30_ADCxA_INV_SHIFT)
#define CS53L30_ADCxA_INV (1 << CS53L30_ADCxA_INV_SHIFT)
#define CS53L30_ADCxB_DIG_BOOST_SHIFT 1
#define CS53L30_ADCxB_DIG_BOOST_MASK (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT)
#define CS53L30_ADCxB_DIG_BOOST (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT)
#define CS53L30_ADCxA_DIG_BOOST_SHIFT 0
#define CS53L30_ADCxA_DIG_BOOST_MASK (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT)
#define CS53L30_ADCxA_DIG_BOOST (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT)
#define CS53L30_ADCDMIC1_CTL2_DEFAULT (0)
/* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */
#define CS53L30_ADCx_HPF_EN_SHIFT 3
#define CS53L30_ADCx_HPF_EN_MASK (1 << CS53L30_ADCx_HPF_EN_SHIFT)
#define CS53L30_ADCx_HPF_EN (1 << CS53L30_ADCx_HPF_EN_SHIFT)
#define CS53L30_ADCx_HPF_CF_SHIFT 1
#define CS53L30_ADCx_HPF_CF_WIDTH 2
#define CS53L30_ADCx_HPF_CF_MASK (((1 << CS53L30_ADCx_HPF_CF_WIDTH) - 1) << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_1HZ86 (0 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_120HZ (1 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_235HZ (2 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_466HZ (3 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_NG_ALL_SHIFT 0
#define CS53L30_ADCx_NG_ALL_MASK (1 << CS53L30_ADCx_NG_ALL_SHIFT)
#define CS53L30_ADCx_NG_ALL (1 << CS53L30_ADCx_NG_ALL_SHIFT)
#define CS53L30_ADCx_CTL3_DEFAULT (CS53L30_ADCx_HPF_EN)
/* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */
#define CS53L30_ADCxB_NG_SHIFT 7
#define CS53L30_ADCxB_NG_MASK (1 << CS53L30_ADCxB_NG_SHIFT)
#define CS53L30_ADCxB_NG (1 << CS53L30_ADCxB_NG_SHIFT)
#define CS53L30_ADCxA_NG_SHIFT 6
#define CS53L30_ADCxA_NG_MASK (1 << CS53L30_ADCxA_NG_SHIFT)
#define CS53L30_ADCxA_NG (1 << CS53L30_ADCxA_NG_SHIFT)
#define CS53L30_ADCx_NG_BOOST_SHIFT 5
#define CS53L30_ADCx_NG_BOOST_MASK (1 << CS53L30_ADCx_NG_BOOST_SHIFT)
#define CS53L30_ADCx_NG_BOOST (1 << CS53L30_ADCx_NG_BOOST_SHIFT)
#define CS53L30_ADCx_NG_THRESH_SHIFT 2
#define CS53L30_ADCx_NG_THRESH_WIDTH 3
#define CS53L30_ADCx_NG_THRESH_MASK (((1 << CS53L30_ADCx_NG_THRESH_WIDTH) - 1) << CS53L30_ADCx_NG_THRESH_SHIFT)
#define CS53L30_ADCx_NG_DELAY_SHIFT 0
#define CS53L30_ADCx_NG_DELAY_WIDTH 2
#define CS53L30_ADCx_NG_DELAY_MASK (((1 << CS53L30_ADCx_NG_DELAY_WIDTH) - 1) << CS53L30_ADCx_NG_DELAY_SHIFT)
#define CS53L30_ADCx_NG_CTL_DEFAULT (0)
/* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */
#define CS53L30_ADCxy_PREAMP_SHIFT 6
#define CS53L30_ADCxy_PREAMP_WIDTH 2
#define CS53L30_ADCxy_PREAMP_MASK (((1 << CS53L30_ADCxy_PREAMP_WIDTH) - 1) << CS53L30_ADCxy_PREAMP_SHIFT)
#define CS53L30_ADCxy_PGA_VOL_SHIFT 0
#define CS53L30_ADCxy_PGA_VOL_WIDTH 6
#define CS53L30_ADCxy_PGA_VOL_MASK (((1 << CS53L30_ADCxy_PGA_VOL_WIDTH) - 1) << CS53L30_ADCxy_PGA_VOL_SHIFT)
#define CS53L30_ADCxy_AFE_CTL_DEFAULT (0)
/* R43/R44/R51/R52 (0x2B/0x2C/0x33/0x34) CS53L30_ADCxy_DIG_VOL - ADC1A/1B/2A/2B Digital Volume */
#define CS53L30_ADCxy_VOL_MUTE (0x80)
#define CS53L30_ADCxy_DIG_VOL_DEFAULT (0x0)
/* CS53L30_INT */
#define CS53L30_PDN_DONE (1 << 7)
#define CS53L30_THMS_TRIP (1 << 6)
#define CS53L30_SYNC_DONE (1 << 5)
#define CS53L30_ADC2B_OVFL (1 << 4)
#define CS53L30_ADC2A_OVFL (1 << 3)
#define CS53L30_ADC1B_OVFL (1 << 2)
#define CS53L30_ADC1A_OVFL (1 << 1)
#define CS53L30_MUTE_PIN (1 << 0)
#define CS53L30_DEVICE_INT_MASK 0xFF
#endif /* __CS53L30_H__ */
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