Commit deca8322 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher

drm/amd/amdgpu: Port MMHUB over to new SOC15 macros

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 805cb75c
...@@ -200,8 +200,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) ...@@ -200,8 +200,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
uint32_t tmp; uint32_t tmp;
for (i = 0; i <= 14; i++) { for (i = 0; i <= 14; i++) {
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
+ i);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
ENABLE_CONTEXT, 1); ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
...@@ -223,12 +222,12 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) ...@@ -223,12 +222,12 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
PAGE_TABLE_BLOCK_SIZE, PAGE_TABLE_BLOCK_SIZE,
adev->vm_manager.block_size - 9); adev->vm_manager.block_size - 9);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) + i, tmp); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2, WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
lower_32_bits(adev->vm_manager.max_pfn - 1)); lower_32_bits(adev->vm_manager.max_pfn - 1));
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits(adev->vm_manager.max_pfn - 1));
} }
} }
...@@ -238,11 +237,9 @@ static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) ...@@ -238,11 +237,9 @@ static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
unsigned i; unsigned i;
for (i = 0; i < 18; ++i) { for (i = 0; i < 18; ++i) {
WREG32(SOC15_REG_OFFSET(MMHUB, 0, WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
2 * i, 0xffffffff); 2 * i, 0xffffffff);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
2 * i, 0x1f); 2 * i, 0x1f);
} }
} }
...@@ -282,7 +279,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) ...@@ -282,7 +279,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
/* Disable all tables */ /* Disable all tables */
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL) + i, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
/* Setup TLB control */ /* Setup TLB control */
tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
......
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