Commit dffdeade authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas

arm64/sysreg: Generate definitions for FAR_ELx

Convert FAR_ELx to automatic register generation as per DDI0487H.a. In the
architecture these registers have a single field "named" as "Faulting
Virtual Address for synchronous exceptions taken to ELx" occupying the
entire register, in order to fit in with the requirement to describe the
contents of the register I have created a single field named ADDR.

No functional change.
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220520161639.324236-7-broonie@kernel.orgSigned-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 01baa57a
...@@ -249,7 +249,6 @@ ...@@ -249,7 +249,6 @@
#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
#define SYS_PAR_EL1_F BIT(0) #define SYS_PAR_EL1_F BIT(0)
...@@ -564,7 +563,6 @@ ...@@ -564,7 +563,6 @@
#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
...@@ -619,7 +617,6 @@ ...@@ -619,7 +617,6 @@
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
......
...@@ -228,6 +228,10 @@ Sysreg SMCR_EL1 3 0 1 2 6 ...@@ -228,6 +228,10 @@ Sysreg SMCR_EL1 3 0 1 2 6
Fields SMCR_ELx Fields SMCR_ELx
EndSysreg EndSysreg
Sysreg FAR_EL1 3 0 6 0 0
Field 63:0 ADDR
EndSysreg
SysregFields CONTEXTIDR_ELx SysregFields CONTEXTIDR_ELx
Res0 63:32 Res0 63:32
Field 31:0 PROCID Field 31:0 PROCID
...@@ -322,6 +326,10 @@ Field 3:2 D1 ...@@ -322,6 +326,10 @@ Field 3:2 D1
Field 1:0 D0 Field 1:0 D0
EndSysreg EndSysreg
Sysreg FAR_EL2 3 4 6 0 0
Field 63:0 ADDR
EndSysreg
Sysreg CONTEXTIDR_EL2 3 4 13 0 1 Sysreg CONTEXTIDR_EL2 3 4 13 0 1
Fields CONTEXTIDR_ELx Fields CONTEXTIDR_ELx
EndSysreg EndSysreg
...@@ -338,6 +346,10 @@ Sysreg SMCR_EL12 3 5 1 2 6 ...@@ -338,6 +346,10 @@ Sysreg SMCR_EL12 3 5 1 2 6
Fields SMCR_ELx Fields SMCR_ELx
EndSysreg EndSysreg
Sysreg FAR_EL12 3 5 6 0 0
Field 63:0 ADDR
EndSysreg
Sysreg CONTEXTIDR_EL12 3 5 13 0 1 Sysreg CONTEXTIDR_EL12 3 5 13 0 1
Fields CONTEXTIDR_ELx Fields CONTEXTIDR_ELx
EndSysreg EndSysreg
......
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