Commit e0093a89 authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan Committed by Jani Nikula

drm/i915/psr: Fix register name mess up.

Commit 77affa31 ("drm/i915/psr: Fix compiler warnings for
hsw_psr_disable()") swapped status and control registers while fixing
indentation. The _ctl at the end of the status register name must have to
led to this.

Fixes: 77affa31 ("drm/i915/psr: Fix compiler warnings for hsw_psr_disable()")
References: https://www.mrc-cbu.cam.ac.uk/people/matt.davis/cmabridge/
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171220043520.2599-1-dhinakaran.pandiyan@intel.comReviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 14c6547d)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 30a7acd5
...@@ -590,7 +590,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, ...@@ -590,7 +590,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
if (dev_priv->psr.active) { if (dev_priv->psr.active) {
i915_reg_t psr_ctl; i915_reg_t psr_status;
u32 psr_status_mask; u32 psr_status_mask;
if (dev_priv->psr.aux_frame_sync) if (dev_priv->psr.aux_frame_sync)
...@@ -599,24 +599,24 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, ...@@ -599,24 +599,24 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
0); 0);
if (dev_priv->psr.psr2_support) { if (dev_priv->psr.psr2_support) {
psr_ctl = EDP_PSR2_CTL; psr_status = EDP_PSR2_STATUS_CTL;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
I915_WRITE(psr_ctl, I915_WRITE(EDP_PSR2_CTL,
I915_READ(psr_ctl) & I915_READ(EDP_PSR2_CTL) &
~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
} else { } else {
psr_ctl = EDP_PSR_STATUS_CTL; psr_status = EDP_PSR_STATUS_CTL;
psr_status_mask = EDP_PSR_STATUS_STATE_MASK; psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
I915_WRITE(psr_ctl, I915_WRITE(EDP_PSR_CTL,
I915_READ(psr_ctl) & ~EDP_PSR_ENABLE); I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
} }
/* Wait till PSR is idle */ /* Wait till PSR is idle */
if (intel_wait_for_register(dev_priv, if (intel_wait_for_register(dev_priv,
psr_ctl, psr_status_mask, 0, psr_status, psr_status_mask, 0,
2000)) 2000))
DRM_ERROR("Timed out waiting for PSR Idle State\n"); DRM_ERROR("Timed out waiting for PSR Idle State\n");
......
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