Commit e0127662 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A batch of fixes for -rc4, for various platforms.

  Nothing really substantial and worth pointing out in particular; small
  fixes for various bugs, see shortlog for details"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: sa1100: remove references to the defunct handhelds.org
  bus: uniphier-system-bus: fix condition of overlap check
  ARM: uniphier: drop weird sizeof()
  ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type
  ARM: OMAP: Correct interrupt type for ARM TWD
  ARM: DRA722: Add ID detect for Silicon Rev 2.0
  ARM: dts: am43xx: fix edma memcpy channel allocation
  ARM: dts: AM43x-epos: Fix clk parent for synctimer
  ARM: OMAP2: Fix up interconnect barrier initialization for DRA7
  documentation: Fix pinctrl documentation for Meson8 / Meson8b
  ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
  ARM: mvebu: Correct unit address for linksys
  bus: mvebu-mbus: use %pa to print phys_addr_t
  arm64: dts: vulcan: Update PCI ranges
  ARM: u8500_defconfig: turn on the Synaptics RMI4 driver
  ARM: pxa: fix the number of DMA requestor lines
  ARM: OMAP2+: hwmod: Fix updating of sysconfig register
  ARM: OMAP2+: Use srst_udelay for USB on dm814x
parents 5e1b59ab 0b24f7a8
== Amlogic Meson pinmux controller == == Amlogic Meson pinmux controller ==
Required properties for the root node: Required properties for the root node:
- compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl" - compatible: one of "amlogic,meson8-cbus-pinctrl"
"amlogic,meson8b-cbus-pinctrl"
"amlogic,meson8-aobus-pinctrl"
"amlogic,meson8b-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality - reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes === === GPIO sub-nodes ===
The 2 power domains of the controller (regular and always-on) are The GPIO bank for the controller is represented as a sub-node and it acts as a
represented as sub-nodes and each of them acts as a GPIO controller. GPIO controller.
Required properties for sub-nodes are: Required properties for sub-nodes are:
- reg: should contain address and size for mux, pull-enable, pull and - reg: should contain address and size for mux, pull-enable, pull and
...@@ -18,10 +21,6 @@ Required properties for sub-nodes are: ...@@ -18,10 +21,6 @@ Required properties for sub-nodes are:
- gpio-controller: identifies the node as a gpio controller - gpio-controller: identifies the node as a gpio controller
- #gpio-cells: must be 2 - #gpio-cells: must be 2
Valid sub-node names are:
- "banks" for the regular domain
- "ao-bank" for the always-on domain
=== Other sub-nodes === === Other sub-nodes ===
Child nodes without the "gpio-controller" represent some desired Child nodes without the "gpio-controller" represent some desired
...@@ -45,7 +44,7 @@ pinctrl-bindings.txt ...@@ -45,7 +44,7 @@ pinctrl-bindings.txt
=== Example === === Example ===
pinctrl: pinctrl@c1109880 { pinctrl: pinctrl@c1109880 {
compatible = "amlogic,meson8-pinctrl"; compatible = "amlogic,meson8-cbus-pinctrl";
reg = <0xc1109880 0x10>; reg = <0xc1109880 0x10>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -61,15 +60,6 @@ pinctrl-bindings.txt ...@@ -61,15 +60,6 @@ pinctrl-bindings.txt
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpio_ao: ao-bank@c1108030 {
reg = <0xc8100014 0x4>,
<0xc810002c 0x4>,
<0xc8100024 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
nand { nand {
mux { mux {
groups = "nand_io", "nand_io_ce0", "nand_io_ce1", groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
...@@ -79,18 +69,4 @@ pinctrl-bindings.txt ...@@ -79,18 +69,4 @@ pinctrl-bindings.txt
function = "nand"; function = "nand";
}; };
}; };
uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a",
"uart_cts_ao_a", "uart_rts_ao_a";
function = "uart_ao";
};
conf {
pins = "GPIOAO_0", "GPIOAO_1",
"GPIOAO_2", "GPIOAO_3";
bias-disable;
};
};
}; };
...@@ -470,9 +470,12 @@ &davinci_mdio { ...@@ -470,9 +470,12 @@ &davinci_mdio {
}; };
&cpsw_emac0 { &cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii"; phy-mode = "rmii";
dual_emac_res_vlan = <1>; dual_emac_res_vlan = <1>;
fixed-link {
speed = <100>;
full-duplex;
};
}; };
&cpsw_emac1 { &cpsw_emac1 {
......
...@@ -207,7 +207,7 @@ edma: edma@49000000 { ...@@ -207,7 +207,7 @@ edma: edma@49000000 {
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>; <&edma_tptc2 0>;
ti,edma-memcpy-channels = <32 33>; ti,edma-memcpy-channels = <58 59>;
}; };
edma_tptc0: tptc@49800000 { edma_tptc0: tptc@49800000 {
......
...@@ -794,3 +794,8 @@ &mcasp1 { ...@@ -794,3 +794,8 @@ &mcasp1 {
tx-num-evt = <32>; tx-num-evt = <32>;
rx-num-evt = <32>; rx-num-evt = <32>;
}; };
&synctimer_32kclk {
assigned-clocks = <&mux_synctimer32k_ck>;
assigned-clock-parents = <&clkdiv32k_ick>;
};
...@@ -117,7 +117,7 @@ sata@a8000 { ...@@ -117,7 +117,7 @@ sata@a8000 {
}; };
/* USB part of the eSATA/USB 2.0 port */ /* USB part of the eSATA/USB 2.0 port */
usb@50000 { usb@58000 {
status = "okay"; status = "okay";
}; };
......
...@@ -91,8 +91,8 @@ clk81: clk@0 { ...@@ -91,8 +91,8 @@ clk81: clk@0 {
clock-frequency = <141666666>; clock-frequency = <141666666>;
}; };
pinctrl: pinctrl@c1109880 { pinctrl_cbus: pinctrl@c1109880 {
compatible = "amlogic,meson8-pinctrl"; compatible = "amlogic,meson8-cbus-pinctrl";
reg = <0xc1109880 0x10>; reg = <0xc1109880 0x10>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -108,29 +108,6 @@ gpio: banks@c11080b0 { ...@@ -108,29 +108,6 @@ gpio: banks@c11080b0 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpio_ao: ao-bank@c1108030 {
reg = <0xc8100014 0x4>,
<0xc810002c 0x4>,
<0xc8100024 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
i2c_ao_pins: i2c_mst_ao {
mux {
groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
function = "i2c_mst_ao";
};
};
spi_nor_pins: nor { spi_nor_pins: nor {
mux { mux {
groups = "nor_d", "nor_q", "nor_c", "nor_cs"; groups = "nor_d", "nor_q", "nor_c", "nor_cs";
...@@ -157,4 +134,34 @@ mux { ...@@ -157,4 +134,34 @@ mux {
}; };
}; };
pinctrl_aobus: pinctrl@c8100084 {
compatible = "amlogic,meson8-aobus-pinctrl";
reg = <0xc8100084 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio_ao: ao-bank@c1108030 {
reg = <0xc8100014 0x4>,
<0xc810002c 0x4>,
<0xc8100024 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
i2c_ao_pins: i2c_mst_ao {
mux {
groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
function = "i2c_mst_ao";
};
};
};
}; /* end of / */ }; /* end of / */
...@@ -155,8 +155,8 @@ clkc: clock-controller@c1104000 { ...@@ -155,8 +155,8 @@ clkc: clock-controller@c1104000 {
reg = <0xc1108000 0x4>, <0xc1104000 0x460>; reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
}; };
pinctrl: pinctrl@c1109880 { pinctrl_cbus: pinctrl@c1109880 {
compatible = "amlogic,meson8b-pinctrl"; compatible = "amlogic,meson8b-cbus-pinctrl";
reg = <0xc1109880 0x10>; reg = <0xc1109880 0x10>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -171,6 +171,14 @@ gpio: banks@c11080b0 { ...@@ -171,6 +171,14 @@ gpio: banks@c11080b0 {
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
};
pinctrl_aobus: pinctrl@c8100084 {
compatible = "amlogic,meson8b-aobus-pinctrl";
reg = <0xc8100084 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio_ao: ao-bank@c1108030 { gpio_ao: ao-bank@c1108030 {
reg = <0xc8100014 0x4>, reg = <0xc8100014 0x4>,
......
...@@ -70,7 +70,7 @@ local-timer@48240600 { ...@@ -70,7 +70,7 @@ local-timer@48240600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
clocks = <&mpu_periphclk>; clocks = <&mpu_periphclk>;
reg = <0x48240600 0x20>; reg = <0x48240600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
}; };
......
...@@ -63,6 +63,9 @@ CONFIG_INPUT_TOUCHSCREEN=y ...@@ -63,6 +63,9 @@ CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_BU21013=y CONFIG_TOUCHSCREEN_BU21013=y
CONFIG_INPUT_MISC=y CONFIG_INPUT_MISC=y
CONFIG_INPUT_AB8500_PONKEY=y CONFIG_INPUT_AB8500_PONKEY=y
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_F11=y
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set
......
...@@ -669,9 +669,9 @@ void __init dra7xxx_check_revision(void) ...@@ -669,9 +669,9 @@ void __init dra7xxx_check_revision(void)
case 0: case 0:
omap_revision = DRA722_REV_ES1_0; omap_revision = DRA722_REV_ES1_0;
break; break;
case 1:
default: default:
/* If we have no new revisions */ omap_revision = DRA722_REV_ES2_0;
omap_revision = DRA722_REV_ES1_0;
break; break;
} }
break; break;
......
...@@ -368,6 +368,7 @@ void __init omap5_map_io(void) ...@@ -368,6 +368,7 @@ void __init omap5_map_io(void)
void __init dra7xx_map_io(void) void __init dra7xx_map_io(void)
{ {
iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
omap_barriers_init();
} }
#endif #endif
/* /*
......
...@@ -1416,8 +1416,6 @@ static void _enable_sysc(struct omap_hwmod *oh) ...@@ -1416,8 +1416,6 @@ static void _enable_sysc(struct omap_hwmod *oh)
(sf & SYSC_HAS_CLOCKACTIVITY)) (sf & SYSC_HAS_CLOCKACTIVITY))
_set_clockactivity(oh, oh->class->sysc->clockact, &v); _set_clockactivity(oh, oh->class->sysc->clockact, &v);
/* If the cached value is the same as the new value, skip the write */
if (oh->_sysc_cache != v)
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
/* /*
...@@ -1481,6 +1479,8 @@ static void _idle_sysc(struct omap_hwmod *oh) ...@@ -1481,6 +1479,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
_set_master_standbymode(oh, idlemode, &v); _set_master_standbymode(oh, idlemode, &v);
} }
/* If the cached value is the same as the new value, skip the write */
if (oh->_sysc_cache != v)
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
} }
......
...@@ -582,9 +582,11 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { ...@@ -582,9 +582,11 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
.rev_offs = 0x0, .rev_offs = 0x0,
.sysc_offs = 0x10, .sysc_offs = 0x10,
.srst_udelay = 2,
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET, SYSC_HAS_SOFTRESET,
.idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
......
...@@ -489,6 +489,7 @@ IS_OMAP_TYPE(3430, 0x3430) ...@@ -489,6 +489,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8)) #define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8))
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8)) #define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8)) #define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
#define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8))
void omap2xxx_check_revision(void); void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void); void omap3xxx_check_revision(void);
......
...@@ -1235,5 +1235,6 @@ static struct platform_device pxa2xx_pxa_dma = { ...@@ -1235,5 +1235,6 @@ static struct platform_device pxa2xx_pxa_dma = {
void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors) void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors)
{ {
pxa_dma_pdata.dma_channels = nb_channels; pxa_dma_pdata.dma_channels = nb_channels;
pxa_dma_pdata.nb_requestors = nb_requestors;
pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata); pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
} }
...@@ -61,10 +61,7 @@ config SA1100_H3100 ...@@ -61,10 +61,7 @@ config SA1100_H3100
select MFD_IPAQ_MICRO select MFD_IPAQ_MICRO
help help
Say Y here if you intend to run this kernel on the Compaq iPAQ Say Y here if you intend to run this kernel on the Compaq iPAQ
H3100 handheld computer. Information about this machine and the H3100 handheld computer.
Linux port to this machine can be found at:
<http://www.handhelds.org/Compaq/index.html#iPAQ_H3100>
config SA1100_H3600 config SA1100_H3600
bool "Compaq iPAQ H3600/H3700" bool "Compaq iPAQ H3600/H3700"
...@@ -73,10 +70,7 @@ config SA1100_H3600 ...@@ -73,10 +70,7 @@ config SA1100_H3600
select MFD_IPAQ_MICRO select MFD_IPAQ_MICRO
help help
Say Y here if you intend to run this kernel on the Compaq iPAQ Say Y here if you intend to run this kernel on the Compaq iPAQ
H3600 handheld computer. Information about this machine and the H3600 and H3700 handheld computers.
Linux port to this machine can be found at:
<http://www.handhelds.org/Compaq/index.html#iPAQ_H3600>
config SA1100_BADGE4 config SA1100_BADGE4
bool "HP Labs BadgePAD 4" bool "HP Labs BadgePAD 4"
......
...@@ -120,7 +120,7 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus) ...@@ -120,7 +120,7 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus)
if (ret) if (ret)
return ret; return ret;
uniphier_smp_rom_boot_rsv2 = ioremap(rom_rsv2_phys, sizeof(SZ_4)); uniphier_smp_rom_boot_rsv2 = ioremap(rom_rsv2_phys, SZ_4);
if (!uniphier_smp_rom_boot_rsv2) { if (!uniphier_smp_rom_boot_rsv2) {
pr_err("failed to map ROM_BOOT_RSV2 register\n"); pr_err("failed to map ROM_BOOT_RSV2 register\n");
return -ENOMEM; return -ENOMEM;
......
...@@ -108,12 +108,15 @@ pci { ...@@ -108,12 +108,15 @@ pci {
reg = <0x0 0x30000000 0x0 0x10000000>; reg = <0x0 0x30000000 0x0 0x10000000>;
reg-names = "PCI ECAM"; reg-names = "PCI ECAM";
/* IO 0x4000_0000 - 0x4001_0000 */ /*
ranges = <0x01000000 0 0x40000000 0 0x40000000 0 0x00010000 * PCI ranges:
/* MEM 0x4800_0000 - 0x5000_0000 */ * IO no supported
0x02000000 0 0x48000000 0 0x48000000 0 0x08000000 * MEM 0x4000_0000 - 0x6000_0000
/* MEM64 pref 0x6_0000_0000 - 0x7_0000_0000 */ * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
0x43000000 6 0x00000000 6 0x00000000 1 0x00000000>; */
ranges =
<0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
interrupt-map-mask = <0 0 0 7>; interrupt-map-mask = <0 0 0 7>;
interrupt-map = interrupt-map =
/* addr pin ic icaddr icintr */ /* addr pin ic icaddr icintr */
......
...@@ -972,7 +972,7 @@ int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) ...@@ -972,7 +972,7 @@ int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
} }
} }
pr_err("invalid dram address 0x%x\n", phyaddr); pr_err("invalid dram address %pa\n", &phyaddr);
return -EINVAL; return -EINVAL;
} }
EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info); EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
......
...@@ -108,7 +108,7 @@ static int uniphier_system_bus_check_overlap( ...@@ -108,7 +108,7 @@ static int uniphier_system_bus_check_overlap(
for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) { for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) {
if (priv->bank[i].end > priv->bank[j].base || if (priv->bank[i].end > priv->bank[j].base &&
priv->bank[i].base < priv->bank[j].end) { priv->bank[i].base < priv->bank[j].end) {
dev_err(priv->dev, dev_err(priv->dev,
"region overlap between bank%d and bank%d\n", "region overlap between bank%d and bank%d\n",
......
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