Commit e0bf98fe authored by James Morse's avatar James Morse Committed by Will Deacon

arm64/sysreg: Standardise naming for ID_PFR0_EL1

To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_PFR0_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.

No functional change.
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-9-james.morse@arm.comSigned-off-by: default avatarWill Deacon <will@kernel.org>
parent eef4344f
...@@ -753,12 +753,12 @@ ...@@ -753,12 +753,12 @@
#define ID_MMFR5_EL1_ETS_SHIFT 0 #define ID_MMFR5_EL1_ETS_SHIFT 0
#define ID_PFR0_DIT_SHIFT 24 #define ID_PFR0_EL1_DIT_SHIFT 24
#define ID_PFR0_CSV2_SHIFT 16 #define ID_PFR0_EL1_CSV2_SHIFT 16
#define ID_PFR0_STATE3_SHIFT 12 #define ID_PFR0_EL1_State3_SHIFT 12
#define ID_PFR0_STATE2_SHIFT 8 #define ID_PFR0_EL1_State2_SHIFT 8
#define ID_PFR0_STATE1_SHIFT 4 #define ID_PFR0_EL1_State1_SHIFT 4
#define ID_PFR0_STATE0_SHIFT 0 #define ID_PFR0_EL1_State0_SHIFT 0
#define ID_DFR0_PERFMON_SHIFT 24 #define ID_DFR0_PERFMON_SHIFT 24
#define ID_DFR0_MPROFDBG_SHIFT 20 #define ID_DFR0_MPROFDBG_SHIFT 20
......
...@@ -538,12 +538,12 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = { ...@@ -538,12 +538,12 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
}; };
static const struct arm64_ftr_bits ftr_id_pfr0[] = { static const struct arm64_ftr_bits ftr_id_pfr0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
ARM64_FTR_END, ARM64_FTR_END,
}; };
......
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