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Commit e1ce2a3a authored by Joe Perches's avatar Joe Perches Committed by Greg Kroah-Hartman
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staging: ath6kl: Convert A_UINT32 to u32 

Signed-off-by: default avatarJoe Perches <joe@perches.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 4853ac05
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Showing with 1371 additions and 1380 deletions
drivers/staging/ath6kl/bmi/include/bmi_internal.h
View file @ e1ce2a3a
......@@ -44,12 +44,12 @@ static bool bmiDone;
int
bmiBufferSend(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length);
u32 length);
int
bmiBufferReceive(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length,
u32 length,
bool want_timeout);
#endif
drivers/staging/ath6kl/bmi/src/bmi.c
View file @ e1ce2a3a
This diff is collapsed.
drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
View file @ e1ce2a3a
......@@ -53,10 +53,10 @@ typedef struct bus_request {
struct bus_request *next; /* link list of available requests */
struct bus_request *inusenext; /* link list of in use requests */
struct semaphore sem_req;
A_UINT32 address; /* request data */
u32 address; /* request data */
A_UCHAR *buffer;
A_UINT32 length;
A_UINT32 request;
u32 length;
u32 request;
void *context;
int status;
struct _HIF_SCATTER_REQ_PRIV *pScatterReq; /* this request is a scatter request */
......
drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif.c
View file @ e1ce2a3a
......@@ -67,7 +67,7 @@ static int Func0_CMD52ReadByte(struct mmc_card *card, unsigned int address, unsi
int reset_sdio_on_unload = 0;
module_param(reset_sdio_on_unload, int, 0644);
extern A_UINT32 nohifscattersupport;
extern u32 nohifscattersupport;
/* ------ Static Variables ------ */
......@@ -102,9 +102,9 @@ static struct dev_pm_ops ar6k_device_pm_ops = {
static int registered = 0;
OSDRV_CALLBACKS osdrvCallbacks;
extern A_UINT32 onebitmode;
extern A_UINT32 busspeedlow;
extern A_UINT32 debughif;
extern u32 onebitmode;
extern u32 busspeedlow;
extern u32 debughif;
static void ResetAllCards(void);
static int hifDisableFunc(HIF_DEVICE *device, struct sdio_func *func);
......@@ -154,10 +154,10 @@ int HIFInit(OSDRV_CALLBACKS *callbacks)
static int
__HIFReadWrite(HIF_DEVICE *device,
A_UINT32 address,
u32 address,
A_UCHAR *buffer,
A_UINT32 length,
A_UINT32 request,
u32 length,
u32 request,
void *context)
{
u8 opcode;
......@@ -331,10 +331,10 @@ void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest)
/* queue a read/write request */
int
HIFReadWrite(HIF_DEVICE *device,
A_UINT32 address,
u32 address,
A_UCHAR *buffer,
A_UINT32 length,
A_UINT32 request,
u32 length,
u32 request,
void *context)
{
int status = A_OK;
......@@ -465,7 +465,7 @@ static int async_task(void *param)
return 0;
}
static A_INT32 IssueSDCommand(HIF_DEVICE *device, A_UINT32 opcode, A_UINT32 arg, A_UINT32 flags, A_UINT32 *resp)
static A_INT32 IssueSDCommand(HIF_DEVICE *device, u32 opcode, u32 arg, u32 flags, u32 *resp)
{
struct mmc_command cmd;
A_INT32 err;
......@@ -495,7 +495,7 @@ int ReinitSDIO(HIF_DEVICE *device)
struct mmc_card *card;
struct sdio_func *func;
u8 cmd52_resp;
A_UINT32 clock;
u32 clock;
func = device->func;
card = func->card;
......@@ -506,9 +506,9 @@ int ReinitSDIO(HIF_DEVICE *device)
do {
if (!device->is_suspend) {
A_UINT32 resp;
u32 resp;
u16 rca;
A_UINT32 i;
u32 i;
int bit = fls(host->ocr_avail) - 1;
/* emulate the mmc_power_up(...) */
host->ios.vdd = bit;
......@@ -692,22 +692,22 @@ PowerStateChangeNotify(HIF_DEVICE *device, HIF_DEVICE_POWER_CHANGE_TYPE config)
int
HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
void *config, A_UINT32 configLen)
void *config, u32 configLen)
{
A_UINT32 count;
u32 count;
int status = A_OK;
switch(opcode) {
case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
((u32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
((u32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
((u32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
((u32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
break;
case HIF_DEVICE_GET_MBOX_ADDR:
for (count = 0; count < 4; count ++) {
((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
((u32 *)config)[count] = HIF_MBOX_START_ADDR(count);
}
if (configLen >= sizeof(HIF_DEVICE_MBOX_INFO)) {
......
drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
View file @ e1ce2a3a
......@@ -202,7 +202,7 @@ int DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
static int HifReadWriteScatter(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
{
int status = A_EINVAL;
A_UINT32 request = pReq->Request;
u32 request = pReq->Request;
HIF_SCATTER_REQ_PRIV *pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
do {
......
drivers/staging/ath6kl/htc2/AR6000/ar6k.c
View file @ e1ce2a3a
......@@ -76,7 +76,7 @@ void DevCleanup(AR6K_DEVICE *pDev)
int DevSetup(AR6K_DEVICE *pDev)
{
A_UINT32 blocksizes[AR6K_MAILBOXES];
u32 blocksizes[AR6K_MAILBOXES];
int status = A_OK;
int i;
HTC_CALLBACKS htcCallbacks;
......@@ -488,11 +488,11 @@ int DevEnableRecv(AR6K_DEVICE *pDev, bool AsyncMode)
}
}
int DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,bool *pbIsRecvPending)
int DevWaitForPendingRecv(AR6K_DEVICE *pDev,u32 TimeoutInMs,bool *pbIsRecvPending)
{
int status = A_OK;
A_UCHAR host_int_status = 0x0;
A_UINT32 counter = 0x0;
u32 counter = 0x0;
if(TimeoutInMs < 100)
{
......@@ -612,7 +612,7 @@ int DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, bool FromDMA)
{
u8 *pDMABuffer = NULL;
int i, remaining;
A_UINT32 length;
u32 length;
pDMABuffer = pReq->pScatterBounceBuffer;
......@@ -669,7 +669,7 @@ static int DevReadWriteScatter(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
int status = A_OK;
HTC_PACKET *pIOPacket = NULL;
A_UINT32 request = pReq->Request;
u32 request = pReq->Request;
do {
......@@ -884,13 +884,13 @@ int DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, boo
/* read operation */
pScatterReq->Request = (Async) ? HIF_RD_ASYNC_BLOCK_FIX : HIF_RD_SYNC_BLOCK_FIX;
pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev));
A_ASSERT(pScatterReq->TotalLength <= (u32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev));
} else {
A_UINT32 mailboxWidth;
u32 mailboxWidth;
/* write operation */
pScatterReq->Request = (Async) ? HIF_WR_ASYNC_BLOCK_INC : HIF_WR_SYNC_BLOCK_INC;
A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev));
A_ASSERT(pScatterReq->TotalLength <= (u32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev));
if (pScatterReq->TotalLength > AR6K_LEGACY_MAX_WRITE_LENGTH) {
/* for large writes use the extended address */
pScatterReq->Address = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress;
......@@ -1003,14 +1003,14 @@ int DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, boo
#define TEST_CREDITS_RECV_TIMEOUT 100
static u8 g_Buffer[TOTAL_BYTES];
static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
static u32 g_MailboxAddrs[AR6K_MAILBOXES];
static u32 g_BlockSizes[AR6K_MAILBOXES];
#define BUFFER_PROC_LIST_DEPTH 4
typedef struct _BUFFER_PROC_LIST{
u8 *pBuffer;
A_UINT32 length;
u32 length;
}BUFFER_PROC_LIST;
......@@ -1096,7 +1096,7 @@ static bool CheckBuffers(void)
success = CheckOneBuffer((u16 *)checkList[i].pBuffer, checkList[i].length);
if (!success) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
(A_UINT32)checkList[i].pBuffer, checkList[i].length));
(u32)checkList[i].pBuffer, checkList[i].length));
break;
}
}
......@@ -1128,7 +1128,7 @@ static u16 GetEndMarker(void)
static int SendBuffers(AR6K_DEVICE *pDev, int mbox)
{
int status = A_OK;
A_UINT32 request = HIF_WR_SYNC_BLOCK_INC;
u32 request = HIF_WR_SYNC_BLOCK_INC;
BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
int i;
int totalBytes = 0;
......@@ -1174,7 +1174,7 @@ static int GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
int status = A_OK;
int timeout = TEST_CREDITS_RECV_TIMEOUT;
u8 credits = 0;
A_UINT32 address;
u32 address;
while (true) {
......@@ -1219,7 +1219,7 @@ static int GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
static int RecvBuffers(AR6K_DEVICE *pDev, int mbox)
{
int status = A_OK;
A_UINT32 request = HIF_RD_SYNC_BLOCK_INC;
u32 request = HIF_RD_SYNC_BLOCK_INC;
BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
int curBuffer;
int credits;
......
drivers/staging/ath6kl/htc2/AR6000/ar6k.h
View file @ e1ce2a3a
......@@ -52,8 +52,8 @@ typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
u8 rx_lookahead_valid;
u8 host_int_status2;
u8 gmbox_rx_avail;
A_UINT32 rx_lookahead[2];
A_UINT32 rx_gmbox_lookahead_alias[2];
u32 rx_lookahead[2];
u32 rx_gmbox_lookahead_alias[2];
} POSTPACK AR6K_IRQ_PROC_REGISTERS;
#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
......@@ -113,8 +113,8 @@ typedef struct _AR6K_DEVICE {
AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; /* cache-line safe with pads around */
u8 _Pad3[A_CACHE_LINE_PAD];
void *HIFDevice;
A_UINT32 BlockSize;
A_UINT32 BlockMask;
u32 BlockSize;
u32 BlockMask;
HIF_DEVICE_MBOX_INFO MailBoxInfo;
HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
void *HTCContext;
......@@ -122,7 +122,7 @@ typedef struct _AR6K_DEVICE {
AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
void (*TargetFailureCallback)(void *Context);
int (*MessagePendingCallback)(void *Context,
A_UINT32 LookAheads[],
u32 LookAheads[],
int NumLookAheads,
bool *pAsyncProc,
int *pNumPktsFetched);
......@@ -152,7 +152,7 @@ void DevCleanup(AR6K_DEVICE *pDev);
int DevUnmaskInterrupts(AR6K_DEVICE *pDev);
int DevMaskInterrupts(AR6K_DEVICE *pDev);
int DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
A_UINT32 *pLookAhead,
u32 *pLookAhead,
int TimeoutMS);
int DevRWCompletionHandler(void *context, int status);
int DevDsrHandler(void *context);
......@@ -170,14 +170,14 @@ int DevStopRecv(AR6K_DEVICE *pDev, bool ASyncMode);
int DevEnableRecv(AR6K_DEVICE *pDev, bool ASyncMode);
int DevEnableInterrupts(AR6K_DEVICE *pDev);
int DevDisableInterrupts(AR6K_DEVICE *pDev);
int DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,bool *pbIsRecvPending);
int DevWaitForPendingRecv(AR6K_DEVICE *pDev,u32 TimeoutInMs,bool *pbIsRecvPending);
#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
static INLINE int DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
A_UINT32 paddedLength;
static INLINE int DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, u32 SendLength) {
u32 paddedLength;
bool sync = (pPacket->Completion == NULL) ? true : false;
int status;
......@@ -219,8 +219,8 @@ static INLINE int DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32
return status;
}
static INLINE int DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
A_UINT32 paddedLength;
static INLINE int DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, u32 RecvLength) {
u32 paddedLength;
int status;
bool sync = (pPacket->Completion == NULL) ? true : false;
......@@ -376,8 +376,8 @@ AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle);
#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
int DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength);
int DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength);
int DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, u32 WriteLength);
int DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, u32 ReadLength);
#define PROC_IO_ASYNC true
#define PROC_IO_SYNC false
......
drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c
View file @ e1ce2a3a
......@@ -60,7 +60,7 @@ int DevRWCompletionHandler(void *context, int status)
/* mailbox recv message polling */
int DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
A_UINT32 *pLookAhead,
u32 *pLookAhead,
int TimeoutMS)
{
int status = A_OK;
......@@ -247,7 +247,7 @@ static int DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
static int DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
{
A_UINT32 dummy;
u32 dummy;
int status;
/* Send a target failure event to the application */
......@@ -303,7 +303,7 @@ static int DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
{
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
A_UINT32 lookAhead = 0;
u32 lookAhead = 0;
bool otherInts = false;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
......@@ -471,7 +471,7 @@ static int ProcessPendingIRQs(AR6K_DEVICE *pDev, bool *pDone, bool *pASyncProces
{
int status = A_OK;
u8 host_int_status = 0;
A_UINT32 lookAhead = 0;
u32 lookAhead = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%lX)\n", (unsigned long)pDev));
......
drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c
View file @ e1ce2a3a
......@@ -396,12 +396,12 @@ int DevCheckGMboxInterrupts(AR6K_DEVICE *pDev)
}
int DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength)
int DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, u32 WriteLength)
{
A_UINT32 paddedLength;
u32 paddedLength;
bool sync = (pPacket->Completion == NULL) ? true : false;
int status;
A_UINT32 address;
u32 address;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength);
......@@ -433,10 +433,10 @@ int DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength)
return status;
}
int DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength)
int DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, u32 ReadLength)
{
A_UINT32 paddedLength;
u32 paddedLength;
int status;
bool sync = (pPacket->Completion == NULL) ? true : false;
......
drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
View file @ e1ce2a3a
......@@ -60,8 +60,8 @@ typedef struct {
HCI_TRANSPORT_CONFIG_INFO HCIConfig;
bool HCIAttached;
bool HCIStopped;
A_UINT32 RecvStateFlags;
A_UINT32 SendStateFlags;
u32 RecvStateFlags;
u32 SendStateFlags;
HCI_TRANSPORT_PACKET_TYPE WaitBufferType;
HTC_PACKET_QUEUE SendQueue; /* write queue holding HCI Command and ACL packets */
HTC_PACKET_QUEUE HCIACLRecvBuffers; /* recv queue holding buffers for incomming ACL packets */
......@@ -1230,11 +1230,11 @@ int HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
#define LSB_SCRATCH_IDX 4
#define MSB_SCRATCH_IDX 5
int HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud)
int HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, u32 Baud)
{
GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
HIF_DEVICE *pHIFDevice = (HIF_DEVICE *)(pProt->pDev->HIFDevice);
A_UINT32 scaledBaud, scratchAddr;
u32 scaledBaud, scratchAddr;
int status = A_OK;
/* Divide the desired baud rate by 100
......
drivers/staging/ath6kl/htc2/htc.c
View file @ e1ce2a3a
......@@ -95,8 +95,8 @@ HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo)
HTC_TARGET *target = NULL;
int status = A_OK;
int i;
A_UINT32 ctrl_bufsz;
A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
u32 ctrl_bufsz;
u32 blocksizes[HTC_MAILBOX_NUM_MAX];
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
......
drivers/staging/ath6kl/htc2/htc_internal.h
View file @ e1ce2a3a
......@@ -81,7 +81,7 @@ typedef struct _HTC_ENDPOINT {
int RxProcessCount; /* reference count to allow single processing context */
struct _HTC_TARGET *target; /* back pointer to target */
u8 SeqNo; /* TX seq no (helpful) for debugging */
A_UINT32 LocalConnectionFlags; /* local connection flags */
u32 LocalConnectionFlags; /* local connection flags */
#ifdef HTC_EP_STAT_PROFILING
HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */
#endif
......@@ -123,8 +123,8 @@ typedef struct _HTC_TARGET {
A_MUTEX_T HTCRxLock;
A_MUTEX_T HTCTxLock;
AR6K_DEVICE Device; /* AR6K - specific state */
A_UINT32 OpStateFlags;
A_UINT32 RecvStateFlags;
u32 OpStateFlags;
u32 RecvStateFlags;
HTC_ENDPOINT_ID EpWaitingForBuffers;
bool TargetFailure;
#ifdef HTC_CAPTURE_LAST_FRAME
......@@ -169,7 +169,7 @@ HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
int HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket);
void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
int HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, bool *pAsyncProc, int *pNumPktsFetched);
int HTCRecvMessagePendingHandler(void *Context, u32 MsgLookAheads[], int NumLookAheads, bool *pAsyncProc, int *pNumPktsFetched);
void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
int HTCSendSetupComplete(HTC_TARGET *target);
void HTCFlushRecvBuffers(HTC_TARGET *target);
......
drivers/staging/ath6kl/htc2/htc_recv.c
View file @ e1ce2a3a
......@@ -86,7 +86,7 @@ static void DoRecvCompletion(HTC_ENDPOINT *pEndpoint,
static INLINE int HTCProcessTrailer(HTC_TARGET *target,
u8 *pBuffer,
int Length,
A_UINT32 *pNextLookAheads,
u32 *pNextLookAheads,
int *pNumLookAheads,
HTC_ENDPOINT_ID FromEndpoint)
{
......@@ -228,14 +228,14 @@ static INLINE int HTCProcessTrailer(HTC_TARGET *target,
* note : locks must be released when this function is called */
static int HTCProcessRecvHeader(HTC_TARGET *target,
HTC_PACKET *pPacket,
A_UINT32 *pNextLookAheads,
u32 *pNextLookAheads,
int *pNumLookAheads)
{
u8 temp;
u8 *pBuf;
int status = A_OK;
u16 payloadLen;
A_UINT32 lookAhead;
u32 lookAhead;
pBuf = pPacket->pBuffer;
......@@ -386,7 +386,7 @@ static int HTCProcessRecvHeader(HTC_TARGET *target,
}
static INLINE void HTCAsyncRecvCheckMorePackets(HTC_TARGET *target,
A_UINT32 NextLookAheads[],
u32 NextLookAheads[],
int NumLookAheads,
bool CheckMoreMsgs)
{
......@@ -406,7 +406,7 @@ static INLINE void HTCAsyncRecvCheckMorePackets(HTC_TARGET *target,
("Next look ahead from recv header was INVALID\n"));
#ifdef ATH_DEBUG_MODULE
DebugDumpBytes((u8 *)NextLookAheads,
NumLookAheads * (sizeof(A_UINT32)),
NumLookAheads * (sizeof(u32)),
"BAD lookaheads from lookahead report");
#endif
}
......@@ -496,7 +496,7 @@ static INLINE void DrainRecvIndicationQueue(HTC_TARGET *target, HTC_ENDPOINT *pE
(P)->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS;
/* note: this function can be called with the RX lock held */
static INLINE void SetRxPacketIndicationFlags(A_UINT32 LookAhead,
static INLINE void SetRxPacketIndicationFlags(u32 LookAhead,
HTC_ENDPOINT *pEndpoint,
HTC_PACKET *pPacket)
{
......@@ -519,7 +519,7 @@ void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
{
HTC_TARGET *target = (HTC_TARGET *)Context;
HTC_ENDPOINT *pEndpoint;
A_UINT32 nextLookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
u32 nextLookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
int numLookAheads = 0;
int status;
bool checkMorePkts = true;
......@@ -590,7 +590,7 @@ void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
int HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
{
int status;
A_UINT32 lookAhead;
u32 lookAhead;
HTC_PACKET *pPacket = NULL;
HTC_FRAME_HDR *pHdr;
......@@ -687,7 +687,7 @@ int HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
}
static int AllocAndPrepareRxPackets(HTC_TARGET *target,
A_UINT32 LookAheads[],
u32 LookAheads[],
int Messages,
HTC_ENDPOINT *pEndpoint,
HTC_PACKET_QUEUE *pQueue)
......@@ -724,7 +724,7 @@ static int AllocAndPrepareRxPackets(HTC_TARGET *target,
if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
pHdr->PayloadLen, (A_UINT32)HTC_MAX_PAYLOAD_LENGTH));
pHdr->PayloadLen, (u32)HTC_MAX_PAYLOAD_LENGTH));
status = A_EPROTO;
break;
}
......@@ -832,7 +832,7 @@ static int AllocAndPrepareRxPackets(HTC_TARGET *target,
}
/* make sure this message can fit in the endpoint buffer */
if ((A_UINT32)fullLength > pPacket->BufferLength) {
if ((u32)fullLength > pPacket->BufferLength) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("Payload Length Error : header reports payload of: %d (%d) endpoint buffer size: %d \n",
pHdr->PayloadLen, fullLength, pPacket->BufferLength));
......@@ -884,7 +884,7 @@ static void HTCAsyncRecvScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
int i;
HTC_PACKET *pPacket;
HTC_ENDPOINT *pEndpoint;
A_UINT32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
u32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
int numLookAheads = 0;
HTC_TARGET *target = (HTC_TARGET *)pScatterReq->Context;
int status;
......@@ -1117,14 +1117,14 @@ static INLINE void CheckRecvWaterMark(HTC_ENDPOINT *pEndpoint)
}
/* callback when device layer or lookahead report parsing detects a pending message */
int HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, bool *pAsyncProc, int *pNumPktsFetched)
int HTCRecvMessagePendingHandler(void *Context, u32 MsgLookAheads[], int NumLookAheads, bool *pAsyncProc, int *pNumPktsFetched)
{
HTC_TARGET *target = (HTC_TARGET *)Context;
int status = A_OK;
HTC_PACKET *pPacket;
HTC_ENDPOINT *pEndpoint;
bool asyncProc = false;
A_UINT32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
u32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
int pktsFetched;
HTC_PACKET_QUEUE recvPktQueue, syncCompletedPktsQueue;
bool partialBundle;
......@@ -1155,7 +1155,7 @@ int HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int Nu
}
/* on first entry copy the lookaheads into our temp array for processing */
A_MEMCPY(lookAheads, MsgLookAheads, (sizeof(A_UINT32)) * NumLookAheads);
A_MEMCPY(lookAheads, MsgLookAheads, (sizeof(u32)) * NumLookAheads);
while (true) {
......@@ -1564,7 +1564,7 @@ int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle,
}
int HTCWaitForPendingRecv(HTC_HANDLE HTCHandle,
A_UINT32 TimeoutInMs,
u32 TimeoutInMs,
bool *pbIsRecvPending)
{
int status = A_OK;
......
drivers/staging/ath6kl/htc2/htc_send.c
View file @ e1ce2a3a
......@@ -125,7 +125,7 @@ int HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket)
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
("+-HTCIssueSend: transmit length : %d (%s) \n",
pPacket->ActualLength + (A_UINT32)HTC_HDR_LENGTH,
pPacket->ActualLength + (u32)HTC_HDR_LENGTH,
sync ? "SYNC" : "ASYNC" ));
/* send message to device */
......
drivers/staging/ath6kl/htc2/htc_services.c
View file @ e1ce2a3a
......@@ -44,7 +44,7 @@ void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
if (pPacket->ActualLength > 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("HTCControlRecv, got message with length:%d \n",
pPacket->ActualLength + (A_UINT32)HTC_HDR_LENGTH));
pPacket->ActualLength + (u32)HTC_HDR_LENGTH));
#ifdef ATH_DEBUG_MODULE
/* dump header and message */
......@@ -73,7 +73,7 @@ int HTCSendSetupComplete(HTC_TARGET *target)
if (target->HTCTargetVersion >= HTC_VERSION_2P1) {
HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx;
A_UINT32 setupFlags = 0;
u32 setupFlags = 0;
pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer;
A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
......
drivers/staging/ath6kl/include/a_debug.h
View file @ e1ce2a3a
......@@ -119,7 +119,7 @@ void DebugDumpBytes(A_UCHAR *buffer, u16 length, char *pDescription);
#define ATH_DEBUG_MAX_MOD_DESC_LENGTH 64
typedef struct {
A_UINT32 Mask;
u32 Mask;
char Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH];
} ATH_DEBUG_MASK_DESCRIPTION;
......@@ -129,8 +129,8 @@ typedef struct _ATH_DEBUG_MODULE_DBG_INFO{
struct _ATH_DEBUG_MODULE_DBG_INFO *pNext;
char ModuleName[16];
char ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH];
A_UINT32 Flags;
A_UINT32 CurrentMask;
u32 Flags;
u32 CurrentMask;
int MaxDescriptions;
ATH_DEBUG_MASK_DESCRIPTION *pMaskDescriptions; /* pointer to array of descriptions */
} ATH_DEBUG_MODULE_DBG_INFO;
......@@ -181,8 +181,8 @@ void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
#endif
int a_get_module_mask(char *module_name, A_UINT32 *pMask);
int a_set_module_mask(char *module_name, A_UINT32 Mask);
int a_get_module_mask(char *module_name, u32 *pMask);
int a_set_module_mask(char *module_name, u32 Mask);
void a_dump_module_debug_info_by_name(char *module_name);
void a_module_debug_support_init(void);
void a_module_debug_support_cleanup(void);
......
drivers/staging/ath6kl/include/ar3kconfig.h
View file @ e1ce2a3a
......@@ -39,16 +39,16 @@ extern "C" {
typedef struct {
A_UINT32 Flags; /* config flags */
u32 Flags; /* config flags */
void *pHCIDev; /* HCI bridge device */
HCI_TRANSPORT_PROPERTIES *pHCIProps; /* HCI bridge props */
HIF_DEVICE *pHIFDevice; /* HIF layer device */
A_UINT32 AR3KBaudRate; /* AR3K operational baud rate */
u32 AR3KBaudRate; /* AR3K operational baud rate */
u16 AR6KScale; /* AR6K UART scale value */
u16 AR6KStep; /* AR6K UART step value */
struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */
A_UINT32 PwrMgmtEnabled; /* TLPM enabled? */
u32 PwrMgmtEnabled; /* TLPM enabled? */
u16 IdleTimeout; /* TLPM idle timeout */
u16 WakeupTimeout; /* TLPM wakeup timeout */
u8 bdaddr[6]; /* Bluetooth device address */
......
drivers/staging/ath6kl/include/ar6000_diag.h
View file @ e1ce2a3a
......@@ -26,23 +26,23 @@
int
ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, u32 *address, u32 *data);
int
ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, u32 *address, u32 *data);
int
ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
A_UCHAR *data, A_UINT32 length);
ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, u32 address,
A_UCHAR *data, u32 length);
int
ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
A_UCHAR *data, A_UINT32 length);
ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, u32 address,
A_UCHAR *data, u32 length);
int
ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval);
ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, u32 *regval);
void
ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs);
ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, u32 *targregs);
#endif /*AR6000_DIAG_H_*/
drivers/staging/ath6kl/include/bmi.h
View file @ e1ce2a3a
......@@ -51,81 +51,81 @@ BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
int
BMIReadMemory(HIF_DEVICE *device,
A_UINT32 address,
u32 address,
A_UCHAR *buffer,
A_UINT32 length);
u32 length);
int
BMIWriteMemory(HIF_DEVICE *device,
A_UINT32 address,
u32 address,
A_UCHAR *buffer,
A_UINT32 length);
u32 length);
int
BMIExecute(HIF_DEVICE *device,
A_UINT32 address,
A_UINT32 *param);
u32 address,
u32 *param);
int
BMISetAppStart(HIF_DEVICE *device,
A_UINT32 address);
u32 address);
int
BMIReadSOCRegister(HIF_DEVICE *device,
A_UINT32 address,
A_UINT32 *param);
u32 address,
u32 *param);
int
BMIWriteSOCRegister(HIF_DEVICE *device,
A_UINT32 address,
A_UINT32 param);
u32 address,
u32 param);
int
BMIrompatchInstall(HIF_DEVICE *device,
A_UINT32 ROM_addr,
A_UINT32 RAM_addr,
A_UINT32 nbytes,
A_UINT32 do_activate,
A_UINT32 *patch_id);
u32 ROM_addr,
u32 RAM_addr,
u32 nbytes,
u32 do_activate,
u32 *patch_id);
int
BMIrompatchUninstall(HIF_DEVICE *device,
A_UINT32 rompatch_id);
u32 rompatch_id);
int
BMIrompatchActivate(HIF_DEVICE *device,
A_UINT32 rompatch_count,
A_UINT32 *rompatch_list);
u32 rompatch_count,
u32 *rompatch_list);
int
BMIrompatchDeactivate(HIF_DEVICE *device,
A_UINT32 rompatch_count,
A_UINT32 *rompatch_list);
u32 rompatch_count,
u32 *rompatch_list);
int
BMILZStreamStart(HIF_DEVICE *device,
A_UINT32 address);
u32 address);
int
BMILZData(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length);
u32 length);
int
BMIFastDownload(HIF_DEVICE *device,
A_UINT32 address,
u32 address,
A_UCHAR *buffer,
A_UINT32 length);
u32 length);
int
BMIRawWrite(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length);
u32 length);
int
BMIRawRead(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length,
u32 length,
bool want_timeout);
#ifdef __cplusplus
......
drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h
View file @ e1ce2a3a
......@@ -29,28 +29,28 @@
* This must match the state saved by the target exception handler.
*/
struct XTensa_exception_frame_s {
A_UINT32 xt_pc;
A_UINT32 xt_ps;
A_UINT32 xt_sar;
A_UINT32 xt_vpri;
A_UINT32 xt_a2;
A_UINT32 xt_a3;
A_UINT32 xt_a4;
A_UINT32 xt_a5;
A_UINT32 xt_exccause;
A_UINT32 xt_lcount;
A_UINT32 xt_lbeg;
A_UINT32 xt_lend;
u32 xt_pc;
u32 xt_ps;
u32 xt_sar;
u32 xt_vpri;
u32 xt_a2;
u32 xt_a3;
u32 xt_a4;
u32 xt_a5;
u32 xt_exccause;
u32 xt_lcount;
u32 xt_lbeg;
u32 xt_lend;
A_UINT32 epc1, epc2, epc3, epc4;
u32 epc1, epc2, epc3, epc4;
/* Extra info to simplify post-mortem stack walkback */
#define AR6002_REGDUMP_FRAMES 10
struct {
A_UINT32 a0; /* pc */
A_UINT32 a1; /* sp */
A_UINT32 a2;
A_UINT32 a3;
u32 a0; /* pc */
u32 a1; /* sp */
u32 a2;
u32 a3;
} wb[AR6002_REGDUMP_FRAMES];
};
typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
......
drivers/staging/ath6kl/include/common/AR6002/addrs.h
View file @ e1ce2a3a
......@@ -29,13 +29,13 @@
#if defined(AR6002_REV2)
#define AR6K_RAM_START 0x00500000
#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
#define TARG_RAM_OFFSET(vaddr) ((u32)(vaddr) & 0xfffff)
#define TARG_RAM_SZ (184*1024)
#define TARG_ROM_SZ (80*1024)
#endif
#if defined(AR6002_REV4) || defined(AR6003)
#define AR6K_RAM_START 0x00540000
#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000)
#define TARG_RAM_OFFSET(vaddr) (((u32)(vaddr) & 0xfffff) - 0x40000)
#define TARG_RAM_SZ (256*1024)
#define TARG_ROM_SZ (256*1024)
#endif
......@@ -49,7 +49,7 @@
#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
#define AR6K_ROM_START 0x004e0000
#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000)
#define TARG_ROM_OFFSET(vaddr) (((u32)(vaddr) & 0x1fffff) - 0xe0000)
#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
......
drivers/staging/ath6kl/include/common/a_hci.h
View file @ e1ce2a3a
......@@ -351,9 +351,9 @@ typedef struct flow_spec_t {
u8 id;
u8 service_type;
u16 max_sdu;
A_UINT32 sdu_inter_arrival_time;
A_UINT32 access_latency;
A_UINT32 flush_timeout;
u32 sdu_inter_arrival_time;
u32 access_latency;
u32 flush_timeout;
} POSTPACK FLOW_SPEC;
......@@ -559,15 +559,15 @@ typedef struct hci_event_amp_status_change_t{
typedef struct local_amp_info_resp_t {
u8 status;
u8 amp_status;
A_UINT32 total_bw; /* kbps */
A_UINT32 max_guranteed_bw; /* kbps */
A_UINT32 min_latency;
A_UINT32 max_pdu_size;
u32 total_bw; /* kbps */
u32 max_guranteed_bw; /* kbps */
u32 min_latency;
u32 max_pdu_size;
u8 amp_type;
u16 pal_capabilities;
u16 amp_assoc_len;
A_UINT32 max_flush_timeout; /* in ms */
A_UINT32 be_flush_timeout; /* in ms */
u32 max_flush_timeout; /* in ms */
u32 be_flush_timeout; /* in ms */
} POSTPACK LOCAL_AMP_INFO;
typedef struct amp_assoc_cmd_resp_t{
......
drivers/staging/ath6kl/include/common/bmi_msg.h
View file @ e1ce2a3a
......@@ -65,7 +65,7 @@
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* u32 command (BMI_DONE)
* Response format: none
*/
......@@ -73,9 +73,9 @@
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* u32 command (BMI_READ_MEMORY)
* u32 address
* u32 length, at most BMI_DATASZ_MAX
* Response format:
* u8 data[length]
*/
......@@ -84,9 +84,9 @@
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* u32 command (BMI_WRITE_MEMORY)
* u32 address
* u32 length, at most BMI_DATASZ_MAX
* u8 data[length]
* Response format: none
*/
......@@ -95,19 +95,19 @@
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* u32 command (BMI_EXECUTE)
* u32 address
* u32 parameter
* Response format:
* A_UINT32 return value
* u32 return value
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* u32 command (BMI_SET_APP_START)
* u32 address
* Response format: none
*/
......@@ -115,19 +115,19 @@
/*
* Semantics: Read a 32-bit Target SOC register.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* u32 command (BMI_READ_REGISTER)
* u32 address
* Response format:
* A_UINT32 value
* u32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
/*
* Semantics: Write a 32-bit Target SOC register.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
* u32 command (BMI_WRITE_REGISTER)
* u32 address
* u32 value
*
* Response format: none
*/
......@@ -137,18 +137,18 @@
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
* u32 command (BMI_GET_TARGET_ID/INFO)
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
* u32 TargetVersionID
* Response format2 (newer firmware):
* A_UINT32 TARGET_VERSION_SENTINAL
* u32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
A_UINT32 target_info_byte_count; /* size of this structure */
A_UINT32 target_ver; /* Target Version ID */
A_UINT32 target_type; /* Target type */
u32 target_info_byte_count; /* size of this structure */
u32 target_ver; /* Target Version ID */
u32 target_type; /* Target type */
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_AR6001 1
......@@ -160,14 +160,14 @@ PREPACK struct bmi_target_info {
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* u32 command (BMI_ROMPATCH_INSTALL)
* u32 Target ROM Address
* u32 Target RAM Address or Value (depending on Target Type)
* u32 Size, in bytes
* u32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
* u32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
......@@ -175,8 +175,8 @@ PREPACK struct bmi_target_info {
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
* u32 command (BMI_ROMPATCH_UNINSTALL)
* u32 PatchID
*
* Response format: none
*/
......@@ -185,9 +185,9 @@ PREPACK struct bmi_target_info {
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
* u32 command (BMI_ROMPATCH_ACTIVATE)
* u32 rompatch_count
* u32 PatchID[rompatch_count]
*
* Response format: none
*/
......@@ -196,9 +196,9 @@ PREPACK struct bmi_target_info {
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
* u32 command (BMI_ROMPATCH_DEACTIVATE)
* u32 rompatch_count
* u32 PatchID[rompatch_count]
*
* Response format: none
*/
......@@ -213,8 +213,8 @@ PREPACK struct bmi_target_info {
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* u32 command (BMI_LZ_STREAM_START)
* u32 address
* Note: Not supported on all versions of ROM firmware.
*/
......@@ -226,8 +226,8 @@ PREPACK struct bmi_target_info {
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* u32 command (BMI_LZ_DATA)
* u32 length (of compressed data),
* at most BMI_DATASZ_MAX
* u8 CompressedData[length]
* Response format: none
......
drivers/staging/ath6kl/include/common/btcoexGpio.h
View file @ e1ce2a3a
......@@ -71,8 +71,8 @@
extern void btcoexDbgPulseWord(A_UINT32 gpioPinMask);
extern void btcoexDbgPulse(A_UINT32 pin);
extern void btcoexDbgPulseWord(u32 gpioPinMask);
extern void btcoexDbgPulse(u32 pin);
#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) (btcoexDbgPulseWord(gpioPinMask))
......
drivers/staging/ath6kl/include/common/dbglog.h
View file @ e1ce2a3a
......@@ -90,30 +90,30 @@ extern "C" {
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
u8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
u32 bufsize;
u32 length;
u32 count;
u32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
u32 dropped;
} POSTPACK;
PREPACK struct dbglog_config_s {
A_UINT32 cfgvalid; /* Mask with valid config bits */
u32 cfgvalid; /* Mask with valid config bits */
union {
/* TODO: Take care of endianness */
struct {
A_UINT32 mmask:16; /* Mask of modules with logging on */
A_UINT32 rep:1; /* Reporting enabled or not */
A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */
A_UINT32 size:10; /* Report size in number of messages */
A_UINT32 reserved:2;
u32 mmask:16; /* Mask of modules with logging on */
u32 rep:1; /* Reporting enabled or not */
u32 tsr:3; /* Time stamp resolution. Def: 1 ms */
u32 size:10; /* Report size in number of messages */
u32 reserved:2;
} dbglog_config;
A_UINT32 value;
u32 value;
} u;
} POSTPACK;
......
drivers/staging/ath6kl/include/common/dset_internal.h
View file @ e1ce2a3a
......@@ -48,7 +48,7 @@ typedef PREPACK struct dset_descriptor_s {
DataSet or pointer to original
dset_descriptor for patched
DataSet */
A_UINT32 data_type; /* DSET_TYPE_*, above */
u32 data_type; /* DSET_TYPE_*, above */
void *AuxPtr; /* Additional data that might
needed for data_type. For
......
drivers/staging/ath6kl/include/common/dsetid.h
View file @ e1ce2a3a
......@@ -81,8 +81,8 @@
* This allows for patches to be stored in flash.
*/
PREPACK struct patch_s {
A_UINT32 *address;
A_UINT32 data;
u32 *address;
u32 data;
} POSTPACK ;
/*
......@@ -92,23 +92,23 @@ PREPACK struct patch_s {
* patch code. The "data" in a PATCH_SKIP tells how many
* bytes of length "patch_s" to skip.
*/
#define PATCH_SKIP ((A_UINT32 *)0x00000000)
#define PATCH_SKIP ((u32 *)0x00000000)
/*
* Execute code at the address specified by "data".
* The address of the patch structure is passed as
* the one parameter.
*/
#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001)
#define PATCH_CODE_ABS ((u32 *)0x00000001)
/*
* Same as PATCH_CODE_ABS, but treat "data" as an
* offset from the start of the patch word.
*/
#define PATCH_CODE_REL ((A_UINT32 *)0x00000002)
#define PATCH_CODE_REL ((u32 *)0x00000002)
/* Mark the end of this patch DataSet. */
#define PATCH_END ((A_UINT32 *)0xffffffff)
#define PATCH_END ((u32 *)0xffffffff)
/*
* A DataSet which contains a Binary Patch to some other DataSet
......
drivers/staging/ath6kl/include/common/epping_test.h
View file @ e1ce2a3a
......@@ -54,8 +54,8 @@ typedef PREPACK struct {
u8 _pad[2]; /* padding for alignment */
u8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
u32 HostContext_h; /* 4 byte host context, target echos this back */
u32 SeqNo; /* sequence number (set by host or target) */
u16 Cmd_h; /* ping command (filled by host) */
u16 CmdFlags_h; /* optional flags */
u8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
......
drivers/staging/ath6kl/include/common/htc.h
View file @ e1ce2a3a
......@@ -181,7 +181,7 @@ typedef PREPACK struct {
/* extended setup completion message */
typedef PREPACK struct {
u16 MessageID;
A_UINT32 SetupFlags;
u32 SetupFlags;
u8 MaxMsgsPerBundledRecv;
u8 Rsvd[3];
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
......
drivers/staging/ath6kl/include/common/ini_dset.h
View file @ e1ce2a3a
......@@ -76,7 +76,7 @@ typedef enum {
typedef PREPACK struct {
u16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
u16 offset;
A_UINT32 newValue;
u32 newValue;
} POSTPACK INI_DSET_REG_OVERRIDE;
#endif
drivers/staging/ath6kl/include/common/regdump.h
View file @ e1ce2a3a
......@@ -42,10 +42,10 @@
* the diagnostic window.
*/
PREPACK struct register_dump_s {
A_UINT32 target_id; /* Target ID */
A_UINT32 assline; /* Line number (if assertion failure) */
A_UINT32 pc; /* Program Counter at time of exception */
A_UINT32 badvaddr; /* Virtual address causing exception */
u32 target_id; /* Target ID */
u32 assline; /* Line number (if assertion failure) */
u32 pc; /* Program Counter at time of exception */
u32 badvaddr; /* Virtual address causing exception */
CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
/* Could copy top of stack here, too.... */
......
drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h
View file @ e1ce2a3a
......@@ -145,22 +145,22 @@ typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structure
#define BMZERO {0,0} /* BMLEN zeros */
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
{((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \
(((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \
(((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \
(((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \
(((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \
(((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \
(((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \
(((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \
((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \
(((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \
(((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \
(((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \
(((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \
(((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \
(((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \
(((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))}
{((((_fa >= 0) && (_fa < 32)) ? (((u32) 1) << _fa) : 0) | \
(((_fb >= 0) && (_fb < 32)) ? (((u32) 1) << _fb) : 0) | \
(((_fc >= 0) && (_fc < 32)) ? (((u32) 1) << _fc) : 0) | \
(((_fd >= 0) && (_fd < 32)) ? (((u32) 1) << _fd) : 0) | \
(((_fe >= 0) && (_fe < 32)) ? (((u32) 1) << _fe) : 0) | \
(((_ff >= 0) && (_ff < 32)) ? (((u32) 1) << _ff) : 0) | \
(((_fg >= 0) && (_fg < 32)) ? (((u32) 1) << _fg) : 0) | \
(((_fh >= 0) && (_fh < 32)) ? (((u32) 1) << _fh) : 0)), \
((((_fa > 31) && (_fa < 64)) ? (((u32) 1) << (_fa - 32)) : 0) | \
(((_fb > 31) && (_fb < 64)) ? (((u32) 1) << (_fb - 32)) : 0) | \
(((_fc > 31) && (_fc < 64)) ? (((u32) 1) << (_fc - 32)) : 0) | \
(((_fd > 31) && (_fd < 64)) ? (((u32) 1) << (_fd - 32)) : 0) | \
(((_fe > 31) && (_fe < 64)) ? (((u32) 1) << (_fe - 32)) : 0) | \
(((_ff > 31) && (_ff < 64)) ? (((u32) 1) << (_ff - 32)) : 0) | \
(((_fg > 31) && (_fg < 64)) ? (((u32) 1) << (_fg - 32)) : 0) | \
(((_fh > 31) && (_fh < 64)) ? (((u32) 1) << (_fh - 32)) : 0))}
/*
......@@ -174,7 +174,7 @@ typedef PREPACK struct reg_dmn_pair_mapping {
u16 regDmn2GHz; /* 2GHz reg domain */
u8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */
u8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */
A_UINT32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan
u32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan
flags. This value is used as a mask on the unitary flags*/
} POSTPACK REG_DMN_PAIR_MAPPING;
......@@ -215,8 +215,8 @@ typedef PREPACK struct RegDmnFreqBand {
u8 channelSep; /* Channel separation within the band */
u8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */
u8 mode; /* Mode of operation */
A_UINT32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */
A_UINT32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable
u32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */
u32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable
upper 16 bits: what rate (half/quarter) the channel is */
} POSTPACK REG_DMN_FREQ_BAND;
......@@ -229,9 +229,9 @@ typedef PREPACK struct regDomain {
u8 dfsMask; /* DFS bitmask for 5Ghz tables */
u8 flags; /* Requirement flags (AdHoc disallow etc) */
u16 reserved; /* for alignment */
A_UINT32 pscan; /* Bitmask for passive scan */
A_UINT32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
A_UINT32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
u32 pscan; /* Bitmask for passive scan */
u32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
u32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
} POSTPACK REG_DOMAIN;
#endif /* __REG_DBSCHEMA_H__ */
drivers/staging/ath6kl/include/common/targaddrs.h
View file @ e1ce2a3a
......@@ -83,13 +83,13 @@ PREPACK struct host_interest_s {
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
u32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
u32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
u32 hi_dbglog_hdr; /* 0x08 */
/* Indicates whether or not flash is present on Target.
* NB: flash_is_present indicator is here not just
......@@ -99,36 +99,36 @@ PREPACK struct host_interest_s {
* so that it doesn't get reinitialized with the rest
* of data.
*/
A_UINT32 hi_flash_is_present; /* 0x0c */
u32 hi_flash_is_present; /* 0x0c */
/*
* General-purpose flag bits, similar to AR6000_OPTION_* flags.
* Can be used by application rather than by OS.
*/
A_UINT32 hi_option_flag; /* 0x10 */
u32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
u32 hi_serial_enable; /* 0x14 */
/* Start address of Flash DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
u32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
u32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
u32 hi_skip_clock_init; /* 0x20 */
u32 hi_core_clock_setting; /* 0x24 */
u32 hi_cpu_clock_setting; /* 0x28 */
u32 hi_system_sleep_setting; /* 0x2c */
u32 hi_xtal_control_setting; /* 0x30 */
u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
u32 hi_ref_voltage_trim_setting; /* 0x3c */
u32 hi_clock_info; /* 0x40 */
/*
* Flash configuration overrides, used only
......@@ -136,49 +136,49 @@ PREPACK struct host_interest_s {
* (When using flash, modify the global variables
* with equivalent names.)
*/
A_UINT32 hi_bank0_addr_value; /* 0x44 */
A_UINT32 hi_bank0_read_value; /* 0x48 */
A_UINT32 hi_bank0_write_value; /* 0x4c */
A_UINT32 hi_bank0_config_value; /* 0x50 */
u32 hi_bank0_addr_value; /* 0x44 */
u32 hi_bank0_read_value; /* 0x48 */
u32 hi_bank0_write_value; /* 0x4c */
u32 hi_bank0_config_value; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
A_UINT32 hi_board_data_initialized; /* 0x58 */
u32 hi_board_data; /* 0x54 */
u32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
u32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
u32 hi_desired_baud_rate; /* 0x60 */
u32 hi_dbglog_config; /* 0x64 */
u32 hi_end_RAM_reserve_sz; /* 0x68 */
u32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
u32 hi_num_bpatch_streams; /* 0x70 -- unused */
u32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
u32 hi_refclk_hz; /* 0x78 */
u32 hi_ext_clk_detected; /* 0x7c */
u32 hi_dbg_uart_txpin; /* 0x80 */
u32 hi_dbg_uart_rxpin; /* 0x84 */
u32 hi_hci_uart_baud; /* 0x88 */
u32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
u32 hi_hci_uart_baud_scale_val; /* 0x90 */
u32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
u32 hi_allocram_start; /* 0x98 */
u32 hi_allocram_sz; /* 0x9c */
u32 hi_hci_bridge_flags; /* 0xa0 */
u32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [0]: 1 = enable, 0 = disable
* [1]: 0 = UART FC active low, 1 = UART FC active high
* 0xa9 - [7:0]: wakeup timeout in ms
* 0xaa, 0xab - [15:0]: idle timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_initialized; /* 0xb0 */
u32 hi_board_ext_data; /* 0xac */
u32 hi_board_ext_data_initialized; /* 0xb0 */
} POSTPACK;
/* Bits defined in hi_option_flag */
......@@ -207,10 +207,10 @@ PREPACK struct host_interest_s {
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
(u32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
(u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
......@@ -233,7 +233,7 @@ PREPACK struct host_interest_s {
#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
/* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
......
drivers/staging/ath6kl/include/common/testcmd.h
View file @ e1ce2a3a
......@@ -82,20 +82,20 @@ typedef enum {
} TCMD_WLAN_MODE;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 mode;
A_UINT32 freq;
A_UINT32 dataRate;
u32 testCmdId;
u32 mode;
u32 freq;
u32 dataRate;
A_INT32 txPwr;
A_UINT32 antenna;
A_UINT32 enANI;
A_UINT32 scramblerOff;
A_UINT32 aifsn;
u32 antenna;
u32 enANI;
u32 scramblerOff;
u32 aifsn;
u16 pktSz;
u16 txPattern;
A_UINT32 shortGuard;
A_UINT32 numPackets;
A_UINT32 wlanMode;
u32 shortGuard;
u32 numPackets;
u32 wlanMode;
} POSTPACK TCMD_CONT_TX;
#define TCMD_TXPATTERN_ZERONE 0x1
......@@ -124,20 +124,20 @@ typedef enum {
} TCMD_CONT_RX_ACT;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 act;
A_UINT32 enANI;
u32 testCmdId;
u32 act;
u32 enANI;
PREPACK union {
struct PREPACK TCMD_CONT_RX_PARA {
A_UINT32 freq;
A_UINT32 antenna;
A_UINT32 wlanMode;
u32 freq;
u32 antenna;
u32 wlanMode;
} POSTPACK para;
struct PREPACK TCMD_CONT_RX_REPORT {
A_UINT32 totalPkt;
u32 totalPkt;
A_INT32 rssiInDBm;
A_UINT32 crcErrPkt;
A_UINT32 secErrPkt;
u32 crcErrPkt;
u32 secErrPkt;
u16 rateCnt[TCMD_MAX_RATES];
u16 rateCntShortGuard[TCMD_MAX_RATES];
} POSTPACK report;
......@@ -145,8 +145,8 @@ typedef PREPACK struct {
A_UCHAR addr[ATH_MAC_LEN];
} POSTPACK mac;
struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
A_UINT32 antswitch1;
A_UINT32 antswitch2;
u32 antswitch1;
u32 antswitch2;
}POSTPACK antswitchtable;
} POSTPACK u;
} POSTPACK TCMD_CONT_RX;
......@@ -162,8 +162,8 @@ typedef enum {
} TCMD_PM_MODE;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 mode;
u32 testCmdId;
u32 mode;
} POSTPACK TCMD_PM;
typedef enum {
......
drivers/staging/ath6kl/include/common/wmi.h
View file @ e1ce2a3a
This diff is collapsed.
drivers/staging/ath6kl/include/common/wmi_thin.h
View file @ e1ce2a3a
......@@ -119,14 +119,14 @@ typedef PREPACK struct {
* frames that require partial MAC header construction. These rules
* are used by the target to indicate which fields need to be written. */
typedef PREPACK struct {
A_UINT32 rules; /* combination of WMI_WRT_... values */
u32 rules; /* combination of WMI_WRT_... values */
} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
* frames as to which frames should get forwarded to the host and which
* should get processed internally. */
typedef PREPACK struct {
A_UINT32 rules; /* combination of WMI_FILT_... values */
u32 rules; /* combination of WMI_FILT_... values */
} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
......@@ -138,7 +138,7 @@ typedef PREPACK struct {
#define WMI_THIN_CFG_DECRYPT 0x00000002
#define WMI_THIN_CFG_MAC_RULES 0x00000004
#define WMI_THIN_CFG_FILTER_RULES 0x00000008
A_UINT32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */
u32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */
u16 length; /* length in bytes of appended sub-commands */
u8 reserved[2]; /* align padding */
} POSTPACK WMI_THIN_CONFIG_CMD;
......@@ -180,7 +180,7 @@ typedef PREPACK struct {
} POSTPACK WMI_THIN_MIB_STA_MAC;
typedef PREPACK struct {
A_UINT32 time; // units == msec
u32 time; // units == msec
} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
typedef PREPACK struct {
......@@ -188,7 +188,7 @@ typedef PREPACK struct {
} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
typedef PREPACK struct {
A_UINT32 time; // units == usec
u32 time; // units == usec
} POSTPACK WMI_THIN_MIB_SLOT_TIME;
typedef PREPACK struct {
......@@ -204,7 +204,7 @@ typedef PREPACK struct {
typedef PREPACK struct {
#define FRAME_FILTER_PROMISCUOUS 0x00000001
#define FRAME_FILTER_BSSID 0x00000002
A_UINT32 filterMask;
u32 filterMask;
} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
......@@ -231,13 +231,13 @@ typedef PREPACK struct {
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER;
typedef PREPACK struct {
A_UINT32 count; /* num beacons between deliveries */
u32 count; /* num beacons between deliveries */
u8 enable;
u8 reserved[3];
} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
typedef PREPACK struct {
A_UINT32 count; /* num consec lost beacons after which send event */
u32 count; /* num consec lost beacons after which send event */
} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
typedef PREPACK struct {
......@@ -249,9 +249,9 @@ typedef PREPACK struct {
typedef PREPACK struct {
A_UINT32 cap;
A_UINT32 rxRateField;
A_UINT32 beamForming;
u32 cap;
u32 rxRateField;
u32 beamForming;
u8 addr[ATH_MAC_LEN];
u8 enable;
u8 stbc;
......@@ -262,8 +262,8 @@ typedef PREPACK struct {
} POSTPACK WMI_THIN_MIB_HT_CAP;
typedef PREPACK struct {
A_UINT32 infoField;
A_UINT32 basicRateField;
u32 infoField;
u32 basicRateField;
u8 protection;
u8 secondChanneloffset;
u8 channelWidth;
......@@ -301,8 +301,8 @@ typedef PREPACK struct {
} POSTPACK WMI_THIN_GET_MIB_CMD;
typedef PREPACK struct {
A_UINT32 basicRateMask; /* bit mask of basic rates */
A_UINT32 beaconIntval; /* TUs */
u32 basicRateMask; /* bit mask of basic rates */
u32 beaconIntval; /* TUs */
u16 atimWindow; /* TUs */
u16 channel; /* frequency in Mhz */
u8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
......
drivers/staging/ath6kl/include/common/wmix.h
View file @ e1ce2a3a
......@@ -55,7 +55,7 @@ extern "C" {
* WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
*/
typedef PREPACK struct {
A_UINT32 commandId;
u32 commandId;
} POSTPACK WMIX_CMD_HDR;
typedef enum {
......@@ -96,10 +96,10 @@ typedef enum {
* DataSet Open Request Event
*/
typedef PREPACK struct {
A_UINT32 dset_id;
A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
u32 dset_id;
u32 targ_dset_handle; /* echo'ed, not used by Host, */
u32 targ_reply_fn; /* echo'ed, not used by Host, */
u32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETOPENREQ_EVENT;
/*
......@@ -107,7 +107,7 @@ typedef PREPACK struct {
* DataSet Close Event
*/
typedef PREPACK struct {
A_UINT32 access_cookie;
u32 access_cookie;
} POSTPACK WMIX_DSETCLOSE_EVENT;
/*
......@@ -115,30 +115,30 @@ typedef PREPACK struct {
* DataSet Data Request Event
*/
typedef PREPACK struct {
A_UINT32 access_cookie;
A_UINT32 offset;
A_UINT32 length;
A_UINT32 targ_buf; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
u32 access_cookie;
u32 offset;
u32 length;
u32 targ_buf; /* echo'ed, not used by Host, */
u32 targ_reply_fn; /* echo'ed, not used by Host, */
u32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETDATAREQ_EVENT;
typedef PREPACK struct {
A_UINT32 status;
A_UINT32 targ_dset_handle;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 access_cookie;
A_UINT32 size;
A_UINT32 version;
u32 status;
u32 targ_dset_handle;
u32 targ_reply_fn;
u32 targ_reply_arg;
u32 access_cookie;
u32 size;
u32 version;
} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
typedef PREPACK struct {
A_UINT32 status;
A_UINT32 targ_buf;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 length;
u32 status;
u32 targ_buf;
u32 targ_reply_fn;
u32 targ_reply_arg;
u32 length;
u8 buf[1];
} POSTPACK WMIX_DSETDATA_REPLY_CMD;
......@@ -160,10 +160,10 @@ typedef PREPACK struct {
* clear/disable or disable/enable, results are undefined.
*/
typedef PREPACK struct {
A_UINT32 set_mask; /* pins to set */
A_UINT32 clear_mask; /* pins to clear */
A_UINT32 enable_mask; /* pins to enable for output */
A_UINT32 disable_mask; /* pins to disable/tristate */
u32 set_mask; /* pins to set */
u32 clear_mask; /* pins to clear */
u32 enable_mask; /* pins to enable for output */
u32 disable_mask; /* pins to disable/tristate */
} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
/*
......@@ -172,13 +172,13 @@ typedef PREPACK struct {
* platform-dependent header.
*/
typedef PREPACK struct {
A_UINT32 gpioreg_id; /* GPIO register ID */
A_UINT32 value; /* value to write */
u32 gpioreg_id; /* GPIO register ID */
u32 value; /* value to write */
} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
/* Get a GPIO register. For debug/exceptional cases. */
typedef PREPACK struct {
A_UINT32 gpioreg_id; /* GPIO register to read */
u32 gpioreg_id; /* GPIO register to read */
} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
/*
......@@ -187,7 +187,7 @@ typedef PREPACK struct {
* were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
*/
typedef PREPACK struct {
A_UINT32 ack_mask; /* interrupts to acknowledge */
u32 ack_mask; /* interrupts to acknowledge */
} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
/*
......@@ -197,8 +197,8 @@ typedef PREPACK struct {
* use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
*/
typedef PREPACK struct {
A_UINT32 intr_mask; /* pending GPIO interrupts */
A_UINT32 input_values; /* recent GPIO input values */
u32 intr_mask; /* pending GPIO interrupts */
u32 input_values; /* recent GPIO input values */
} POSTPACK WMIX_GPIO_INTR_EVENT;
/*
......@@ -217,8 +217,8 @@ typedef PREPACK struct {
* simplify Host GPIO support.
*/
typedef PREPACK struct {
A_UINT32 value;
A_UINT32 reg_id;
u32 value;
u32 reg_id;
} POSTPACK WMIX_GPIO_DATA_EVENT;
/*
......@@ -230,8 +230,8 @@ typedef PREPACK struct {
* Heartbeat Challenge Response command
*/
typedef PREPACK struct {
A_UINT32 cookie;
A_UINT32 source;
u32 cookie;
u32 source;
} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
/*
......@@ -249,12 +249,12 @@ typedef PREPACK struct {
*/
typedef PREPACK struct {
A_UINT32 period; /* Time (in 30.5us ticks) between samples */
A_UINT32 nbins;
u32 period; /* Time (in 30.5us ticks) between samples */
u32 nbins;
} POSTPACK WMIX_PROF_CFG_CMD;
typedef PREPACK struct {
A_UINT32 addr;
u32 addr;
} POSTPACK WMIX_PROF_ADDR_SET_CMD;
/*
......@@ -264,8 +264,8 @@ typedef PREPACK struct {
* count set to the corresponding count
*/
typedef PREPACK struct {
A_UINT32 addr;
A_UINT32 count;
u32 addr;
u32 count;
} POSTPACK WMIX_PROF_COUNT_EVENT;
#ifndef ATH_TARGET
......
drivers/staging/ath6kl/include/common_drv.h
View file @ e1ce2a3a
......@@ -66,40 +66,40 @@ extern "C" {
/* OS-independent APIs */
int ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
int ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
int ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, u32 *address, u32 *data);
int ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
int ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, u32 *address, u32 *data);
int ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length);
int ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, u32 address, A_UCHAR *data, u32 length);
int ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, bool waitForCompletion, bool coldReset);
int ar6000_reset_device(HIF_DEVICE *hifDevice, u32 TargetType, bool waitForCompletion, bool coldReset);
void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, u32 TargetType);
int ar6000_set_htc_params(HIF_DEVICE *hifDevice,
A_UINT32 TargetType,
A_UINT32 MboxIsrYieldValue,
u32 TargetType,
u32 MboxIsrYieldValue,
u8 HtcControlBuffers);
int ar6000_prepare_target(HIF_DEVICE *hifDevice,
A_UINT32 TargetType,
A_UINT32 TargetVersion);
u32 TargetType,
u32 TargetVersion);
int ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
A_UINT32 TargetType,
A_UINT32 Flags);
u32 TargetType,
u32 Flags);
void ar6000_copy_cust_data_from_target(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
void ar6000_copy_cust_data_from_target(HIF_DEVICE *hifDevice, u32 TargetType);
u8 *ar6000_get_cust_data_buffer(A_UINT32 TargetType);
u8 *ar6000_get_cust_data_buffer(u32 TargetType);
int ar6000_setBTState(void *context, u8 *pInBuf, A_UINT32 InBufSize);
int ar6000_setBTState(void *context, u8 *pInBuf, u32 InBufSize);
int ar6000_setDevicePowerState(void *context, u8 *pInBuf, A_UINT32 InBufSize);
int ar6000_setDevicePowerState(void *context, u8 *pInBuf, u32 InBufSize);
int ar6000_setWowMode(void *context, u8 *pInBuf, A_UINT32 InBufSize);
int ar6000_setWowMode(void *context, u8 *pInBuf, u32 InBufSize);
int ar6000_setHostMode(void *context, u8 *pInBuf, A_UINT32 InBufSize);
int ar6000_setHostMode(void *context, u8 *pInBuf, u32 InBufSize);
#ifdef __cplusplus
}
......
drivers/staging/ath6kl/include/dset_api.h
View file @ e1ce2a3a
......@@ -40,22 +40,22 @@ extern "C" {
/* Called to send a DataSet Open Reply back to the Target. */
int wmi_dset_open_reply(struct wmi_t *wmip,
A_UINT32 status,
A_UINT32 access_cookie,
A_UINT32 size,
A_UINT32 version,
A_UINT32 targ_handle,
A_UINT32 targ_reply_fn,
A_UINT32 targ_reply_arg);
u32 status,
u32 access_cookie,
u32 size,
u32 version,
u32 targ_handle,
u32 targ_reply_fn,
u32 targ_reply_arg);
/* Called to send a DataSet Data Reply back to the Target. */
int wmi_dset_data_reply(struct wmi_t *wmip,
A_UINT32 status,
u32 status,
u8 *host_buf,
A_UINT32 length,
A_UINT32 targ_buf,
A_UINT32 targ_reply_fn,
A_UINT32 targ_reply_arg);
u32 length,
u32 targ_buf,
u32 targ_reply_fn,
u32 targ_reply_arg);
#ifdef __cplusplus
}
......
drivers/staging/ath6kl/include/gpio_api.h
View file @ e1ce2a3a
......@@ -29,10 +29,10 @@
* Send a command to the Target in order to change output on GPIO pins.
*/
int wmi_gpio_output_set(struct wmi_t *wmip,
A_UINT32 set_mask,
A_UINT32 clear_mask,
A_UINT32 enable_mask,
A_UINT32 disable_mask);
u32 set_mask,
u32 clear_mask,
u32 enable_mask,
u32 disable_mask);
/*
* Send a command to the Target requesting input state of GPIO pins.
......@@ -43,17 +43,17 @@ int wmi_gpio_input_get(struct wmi_t *wmip);
* Send a command to the Target to change the value of a GPIO register.
*/
int wmi_gpio_register_set(struct wmi_t *wmip,
A_UINT32 gpioreg_id,
A_UINT32 value);
u32 gpioreg_id,
u32 value);
/*
* Send a command to the Target to fetch the value of a GPIO register.
*/
int wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
int wmi_gpio_register_get(struct wmi_t *wmip, u32 gpioreg_id);
/*
* Send a command to the Target, acknowledging some GPIO interrupts.
*/
int wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
int wmi_gpio_intr_ack(struct wmi_t *wmip, u32 ack_mask);
#endif /* _GPIO_API_H_ */
drivers/staging/ath6kl/include/hci_transport_api.h
View file @ e1ce2a3a
......@@ -237,7 +237,7 @@ int HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
@example:
@see also:
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
int HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
int HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, u32 Baud);
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@desc: Enable/Disable HCI Transport Power Management
......
drivers/staging/ath6kl/include/hif.h
View file @ e1ce2a3a
......@@ -224,8 +224,8 @@ typedef enum {
*/
typedef struct {
A_UINT32 ExtendedAddress; /* extended address for larger writes */
A_UINT32 ExtendedSize;
u32 ExtendedAddress; /* extended address for larger writes */
u32 ExtendedSize;
} HIF_MBOX_PROPERTIES;
#define HIF_MBOX_FLAG_NO_BUNDLING (1 << 0) /* do not allow bundling over the mailbox */
......@@ -236,16 +236,16 @@ typedef enum _MBOX_BUF_IF_TYPE {
} MBOX_BUF_IF_TYPE;
typedef struct {
A_UINT32 MboxAddresses[4]; /* must be first element for legacy HIFs that return the address in
u32 MboxAddresses[4]; /* must be first element for legacy HIFs that return the address in
and ARRAY of 32-bit words */
/* the following describe extended mailbox properties */
HIF_MBOX_PROPERTIES MboxProp[4];
/* if the HIF supports the GMbox extended address region it can report it
* here, some interfaces cannot support the GMBOX address range and not set this */
A_UINT32 GMboxAddress;
A_UINT32 GMboxSize;
A_UINT32 Flags; /* flags to describe mbox behavior or usage */
u32 GMboxAddress;
u32 GMboxSize;
u32 Flags; /* flags to describe mbox behavior or usage */
MBOX_BUF_IF_TYPE MboxBusIFType; /* mailbox bus interface type */
} HIF_DEVICE_MBOX_INFO;
......@@ -288,10 +288,10 @@ typedef enum _HIF_SCATTER_METHOD {
typedef struct _HIF_SCATTER_REQ {
DL_LIST ListLink; /* link management */
A_UINT32 Address; /* address for the read/write operation */
A_UINT32 Request; /* request flags */
A_UINT32 TotalLength; /* total length of entire transfer */
A_UINT32 CallerFlags; /* caller specific flags can be stored here */
u32 Address; /* address for the read/write operation */
u32 Request; /* request flags */
u32 TotalLength; /* total length of entire transfer */
u32 CallerFlags; /* caller specific flags can be stored here */
HIF_SCATTER_COMP_CB CompletionRoutine; /* completion routine set by caller */
int CompletionStatus; /* status of completion */
void *Context; /* caller context for this request */
......@@ -344,12 +344,12 @@ typedef struct osdrv_callbacks {
#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */
typedef struct _HIF_PENDING_EVENTS_INFO {
A_UINT32 Events;
A_UINT32 LookAhead;
A_UINT32 AvailableRecvBytes;
u32 Events;
u32 LookAhead;
u32 AvailableRecvBytes;
#ifdef THREAD_X
A_UINT32 Polling;
A_UINT32 INT_CAUSE_REG;
u32 Polling;
u32 INT_CAUSE_REG;
#endif
} HIF_PENDING_EVENTS_INFO;
......@@ -400,10 +400,10 @@ void HIFDetachHTC(HIF_DEVICE *device);
*/
int
HIFReadWrite(HIF_DEVICE *device,
A_UINT32 address,
u32 address,
A_UCHAR *buffer,
A_UINT32 length,
A_UINT32 request,
u32 length,
u32 request,
void *context);
/*
......@@ -443,7 +443,7 @@ int HIFRWCompleteEventNotify(void);
int
HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
void *config, A_UINT32 configLen);
void *config, u32 configLen);
/*
* This API wait for the remaining MBOX messages to be drained
......
drivers/staging/ath6kl/include/htc_api.h
View file @ e1ce2a3a
......@@ -146,7 +146,7 @@ typedef struct _HTC_SERVICE_CONNECT_REQ {
u8 MetaDataLength; /* optional meta data length */
HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */
int MaxSendQueueDepth; /* maximum depth of any send queue */
A_UINT32 LocalConnectionFlags; /* HTC flags for the host-side (local) connection */
u32 LocalConnectionFlags; /* HTC flags for the host-side (local) connection */
unsigned int MaxSendMsgSize; /* override max message size in send direction */
} HTC_SERVICE_CONNECT_REQ;
......@@ -168,7 +168,7 @@ typedef struct _HTC_ENDPOINT_CREDIT_DIST {
struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */
HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */
A_UINT32 DistFlags; /* distribution flags, distribution function can
u32 DistFlags; /* distribution flags, distribution function can
set default activity using SET_EP_ACTIVE() macro */
int TxCreditsNorm; /* credits for normal operation, anything above this
indicates the endpoint is over-subscribed, this field
......@@ -197,7 +197,7 @@ typedef struct _HTC_ENDPOINT_CREDIT_DIST {
*/
} HTC_ENDPOINT_CREDIT_DIST;
#define HTC_EP_ACTIVE ((A_UINT32) (1u << 31))
#define HTC_EP_ACTIVE ((u32) (1u << 31))
/* macro to check if an endpoint has gone active, useful for credit
* distributions */
......@@ -232,29 +232,29 @@ typedef enum _HTC_ENDPOINT_STAT_ACTION {
/* endpoint statistics */
typedef struct _HTC_ENDPOINT_STATS {
A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on
u32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on
this endpoint */
A_UINT32 TxIssued; /* running count of total TX packets issued */
A_UINT32 TxPacketsBundled; /* running count of TX packets that were issued in bundles */
A_UINT32 TxBundles; /* running count of TX bundles that were issued */
A_UINT32 TxDropped; /* tx packets that were dropped */
A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */
A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */
A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */
A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */
A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */
A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */
A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */
A_UINT32 TxCreditsConsummed; /* count of consummed credits */
A_UINT32 TxCreditsReturned; /* count of credits returned */
A_UINT32 RxReceived; /* count of RX packets received */
A_UINT32 RxLookAheads; /* count of lookahead records
u32 TxIssued; /* running count of total TX packets issued */
u32 TxPacketsBundled; /* running count of TX packets that were issued in bundles */
u32 TxBundles; /* running count of TX bundles that were issued */
u32 TxDropped; /* tx packets that were dropped */
u32 TxCreditRpts; /* running count of total credit reports received for this endpoint */
u32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */
u32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */
u32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */
u32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */
u32 TxCreditsFromOther; /* count of credits received via another endpoint */
u32 TxCreditsFromEp0; /* count of credits received via another endpoint */
u32 TxCreditsConsummed; /* count of consummed credits */
u32 TxCreditsReturned; /* count of credits returned */
u32 RxReceived; /* count of RX packets received */
u32 RxLookAheads; /* count of lookahead records
found in messages received on this endpoint */
A_UINT32 RxPacketsBundled; /* count of recv packets received in a bundle */
A_UINT32 RxBundleLookAheads; /* count of number of bundled lookaheads */
A_UINT32 RxBundleIndFromHdr; /* count of the number of bundle indications from the HTC header */
A_UINT32 RxAllocThreshHit; /* count of the number of times the recv allocation threshhold was hit */
A_UINT32 RxAllocThreshBytes; /* total number of bytes */
u32 RxPacketsBundled; /* count of recv packets received in a bundle */
u32 RxBundleLookAheads; /* count of number of bundled lookaheads */
u32 RxBundleIndFromHdr; /* count of the number of bundle indications from the HTC header */
u32 RxAllocThreshHit; /* count of the number of times the recv allocation threshhold was hit */
u32 RxAllocThreshBytes; /* total number of bytes */
} HTC_ENDPOINT_STATS;
/* ------ Function Prototypes ------ */
......@@ -565,7 +565,7 @@ int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle,
void HTCEnableRecv(HTC_HANDLE HTCHandle);
void HTCDisableRecv(HTC_HANDLE HTCHandle);
int HTCWaitForPendingRecv(HTC_HANDLE HTCHandle,
A_UINT32 TimeoutInMs,
u32 TimeoutInMs,
bool *pbIsRecvPending);
#ifdef __cplusplus
......
drivers/staging/ath6kl/include/htc_packet.h
View file @ e1ce2a3a
......@@ -60,9 +60,9 @@ typedef struct _HTC_TX_PACKET_INFO {
#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
typedef struct _HTC_RX_PACKET_INFO {
A_UINT32 ExpectedHdr; /* HTC internal use */
A_UINT32 HTCRxFlags; /* HTC internal use */
A_UINT32 IndicationFlags; /* indication flags set on each RX packet indication */
u32 ExpectedHdr; /* HTC internal use */
u32 HTCRxFlags; /* HTC internal use */
u32 IndicationFlags; /* indication flags set on each RX packet indication */
} HTC_RX_PACKET_INFO;
#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) /* more packets on this endpoint are being fetched */
......@@ -86,8 +86,8 @@ typedef struct _HTC_PACKET {
* to the caller points to the start of the payload
*/
u8 *pBuffer; /* payload start (RX/TX) */
A_UINT32 BufferLength; /* length of buffer */
A_UINT32 ActualLength; /* actual length of payload */
u32 BufferLength; /* length of buffer */
u32 ActualLength; /* actual length of payload */
HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */
int Status; /* completion status */
union {
......
drivers/staging/ath6kl/include/target_reg_table.h
View file @ e1ce2a3a
......@@ -30,48 +30,48 @@
/*** WARNING : Add to the end of the TABLE! do not change the order ****/
typedef struct targetdef_s {
A_UINT32 d_RTC_BASE_ADDRESS;
A_UINT32 d_SYSTEM_SLEEP_OFFSET;
A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB;
A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK;
A_UINT32 d_CLOCK_CONTROL_OFFSET;
A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK;
A_UINT32 d_RESET_CONTROL_OFFSET;
A_UINT32 d_RESET_CONTROL_SI0_RST_MASK;
A_UINT32 d_GPIO_BASE_ADDRESS;
A_UINT32 d_GPIO_PIN0_OFFSET;
A_UINT32 d_GPIO_PIN1_OFFSET;
A_UINT32 d_GPIO_PIN0_CONFIG_MASK;
A_UINT32 d_GPIO_PIN1_CONFIG_MASK;
A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
A_UINT32 d_SI_CONFIG_I2C_LSB;
A_UINT32 d_SI_CONFIG_I2C_MASK;
A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB;
A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK;
A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB;
A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK;
A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB;
A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK;
A_UINT32 d_SI_CONFIG_DIVIDER_LSB;
A_UINT32 d_SI_CONFIG_DIVIDER_MASK;
A_UINT32 d_SI_BASE_ADDRESS;
A_UINT32 d_SI_CONFIG_OFFSET;
A_UINT32 d_SI_TX_DATA0_OFFSET;
A_UINT32 d_SI_TX_DATA1_OFFSET;
A_UINT32 d_SI_RX_DATA0_OFFSET;
A_UINT32 d_SI_RX_DATA1_OFFSET;
A_UINT32 d_SI_CS_OFFSET;
A_UINT32 d_SI_CS_DONE_ERR_MASK;
A_UINT32 d_SI_CS_DONE_INT_MASK;
A_UINT32 d_SI_CS_START_LSB;
A_UINT32 d_SI_CS_START_MASK;
A_UINT32 d_SI_CS_RX_CNT_LSB;
A_UINT32 d_SI_CS_RX_CNT_MASK;
A_UINT32 d_SI_CS_TX_CNT_LSB;
A_UINT32 d_SI_CS_TX_CNT_MASK;
A_UINT32 d_BOARD_DATA_SZ;
A_UINT32 d_BOARD_EXT_DATA_SZ;
u32 d_RTC_BASE_ADDRESS;
u32 d_SYSTEM_SLEEP_OFFSET;
u32 d_SYSTEM_SLEEP_DISABLE_LSB;
u32 d_SYSTEM_SLEEP_DISABLE_MASK;
u32 d_CLOCK_CONTROL_OFFSET;
u32 d_CLOCK_CONTROL_SI0_CLK_MASK;
u32 d_RESET_CONTROL_OFFSET;
u32 d_RESET_CONTROL_SI0_RST_MASK;
u32 d_GPIO_BASE_ADDRESS;
u32 d_GPIO_PIN0_OFFSET;
u32 d_GPIO_PIN1_OFFSET;
u32 d_GPIO_PIN0_CONFIG_MASK;
u32 d_GPIO_PIN1_CONFIG_MASK;
u32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
u32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
u32 d_SI_CONFIG_I2C_LSB;
u32 d_SI_CONFIG_I2C_MASK;
u32 d_SI_CONFIG_POS_SAMPLE_LSB;
u32 d_SI_CONFIG_POS_SAMPLE_MASK;
u32 d_SI_CONFIG_INACTIVE_CLK_LSB;
u32 d_SI_CONFIG_INACTIVE_CLK_MASK;
u32 d_SI_CONFIG_INACTIVE_DATA_LSB;
u32 d_SI_CONFIG_INACTIVE_DATA_MASK;
u32 d_SI_CONFIG_DIVIDER_LSB;
u32 d_SI_CONFIG_DIVIDER_MASK;
u32 d_SI_BASE_ADDRESS;
u32 d_SI_CONFIG_OFFSET;
u32 d_SI_TX_DATA0_OFFSET;
u32 d_SI_TX_DATA1_OFFSET;
u32 d_SI_RX_DATA0_OFFSET;
u32 d_SI_RX_DATA1_OFFSET;
u32 d_SI_CS_OFFSET;
u32 d_SI_CS_DONE_ERR_MASK;
u32 d_SI_CS_DONE_INT_MASK;
u32 d_SI_CS_START_LSB;
u32 d_SI_CS_START_MASK;
u32 d_SI_CS_RX_CNT_LSB;
u32 d_SI_CS_RX_CNT_MASK;
u32 d_SI_CS_TX_CNT_LSB;
u32 d_SI_CS_TX_CNT_MASK;
u32 d_BOARD_DATA_SZ;
u32 d_BOARD_EXT_DATA_SZ;
} TARGET_REGISTER_TABLE;
#define BOARD_DATA_SZ_MAX 2048
......
drivers/staging/ath6kl/include/wlan_api.h
View file @ e1ce2a3a
......@@ -70,13 +70,13 @@ typedef struct bss {
u8 *ni_buf;
u16 ni_framelen;
struct ieee80211_node_table *ni_table;
A_UINT32 ni_refcnt;
u32 ni_refcnt;
int ni_scangen;
A_UINT32 ni_tstamp;
A_UINT32 ni_actcnt;
u32 ni_tstamp;
u32 ni_actcnt;
#ifdef OS_ROAM_MANAGEMENT
A_UINT32 ni_si_gen;
u32 ni_si_gen;
#endif
} bss_t;
......@@ -100,16 +100,16 @@ int wlan_parse_beacon(u8 *buf, int framelen,
struct ieee80211_common_ie *cie);
u16 wlan_ieee2freq(int chan);
A_UINT32 wlan_freq2ieee(u16 freq);
u32 wlan_freq2ieee(u16 freq);
void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge);
void wlan_set_nodeage(struct ieee80211_node_table *nt, u32 nodeAge);
void
wlan_refresh_inactive_nodes (struct ieee80211_node_table *nt);
bss_t *
wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
A_UINT32 ssidLength, bool bIsWPA2, bool bMatchSSID);
u32 ssidLength, bool bIsWPA2, bool bMatchSSID);
void
wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
......@@ -118,8 +118,8 @@ bss_t *wlan_node_remove(struct ieee80211_node_table *nt, u8 *bssid);
bss_t *
wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
u32 ssidLength, u32 dot11AuthMode, u32 authMode,
u32 pairwiseCryptoType, u32 grpwiseCryptoTyp);
#ifdef __cplusplus
}
......
drivers/staging/ath6kl/include/wmi_api.h
View file @ e1ce2a3a
......@@ -80,9 +80,9 @@ int wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode);
int wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
int wmi_syncpoint(struct wmi_t *wmip);
int wmi_syncpoint_reset(struct wmi_t *wmip);
u8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, bool wmmEnabled);
u8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, u32 layer2Priority, bool wmmEnabled);
u8 wmi_determine_userPriority (u8 *pkt, A_UINT32 layer2Pri);
u8 wmi_determine_userPriority (u8 *pkt, u32 layer2Pri);
int wmi_control_rx(struct wmi_t *wmip, void *osbuf);
void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
......@@ -114,7 +114,7 @@ int wmi_connect_cmd(struct wmi_t *wmip,
A_UCHAR *ssid,
u8 *bssid,
u16 channel,
A_UINT32 ctrl_flags);
u32 ctrl_flags);
int wmi_reconnect_cmd(struct wmi_t *wmip,
u8 *bssid,
......@@ -123,16 +123,16 @@ int wmi_disconnect_cmd(struct wmi_t *wmip);
int wmi_getrev_cmd(struct wmi_t *wmip);
int wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
u32 forceFgScan, u32 isLegacy,
A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
u32 homeDwellTime, u32 forceScanInterval,
A_INT8 numChan, u16 *channelList);
int wmi_scanparams_cmd(struct wmi_t *wmip, u16 fg_start_sec,
u16 fg_end_sec, u16 bg_sec,
u16 minact_chdw_msec,
u16 maxact_chdw_msec, u16 pas_chdw_msec,
u8 shScanRatio, u8 scanCtrlFlags,
A_UINT32 max_dfsch_act_time,
u32 max_dfsch_act_time,
u16 maxact_scan_per_ssid);
int wmi_bssfilter_cmd(struct wmi_t *wmip, u8 filter, A_UINT32 ieMask);
int wmi_bssfilter_cmd(struct wmi_t *wmip, u8 filter, u32 ieMask);
int wmi_probedSsid_cmd(struct wmi_t *wmip, u8 index, u8 flag,
u8 ssidLength, A_UCHAR *ssid);
int wmi_listeninterval_cmd(struct wmi_t *wmip, u16 listenInterval, u16 listenBeacons);
......@@ -142,8 +142,8 @@ int wmi_associnfo_cmd(struct wmi_t *wmip, u8 ieType,
int wmi_powermode_cmd(struct wmi_t *wmip, u8 powerMode);
int wmi_ibsspmcaps_cmd(struct wmi_t *wmip, u8 pmEnable, u8 ttl,
u16 atim_windows, u16 timeout_value);
int wmi_apps_cmd(struct wmi_t *wmip, u8 psType, A_UINT32 idle_time,
A_UINT32 ps_period, u8 sleep_period);
int wmi_apps_cmd(struct wmi_t *wmip, u8 psType, u32 idle_time,
u32 ps_period, u8 sleep_period);
int wmi_pmparams_cmd(struct wmi_t *wmip, u16 idlePeriod,
u16 psPollNum, u16 dtimPolicy,
u16 wakup_tx_policy, u16 num_tx_to_wakeup,
......@@ -172,14 +172,14 @@ int wmi_set_lq_threshold_params(struct wmi_t *wmip,
int wmi_set_rts_cmd(struct wmi_t *wmip, u16 threshold);
int wmi_set_lpreamble_cmd(struct wmi_t *wmip, u8 status, u8 preamblePolicy);
int wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
int wmi_set_error_report_bitmask(struct wmi_t *wmip, u32 bitmask);
int wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
A_UINT32 source);
int wmi_get_challenge_resp_cmd(struct wmi_t *wmip, u32 cookie,
u32 source);
int wmi_config_debug_module_cmd(struct wmi_t *wmip, u16 mmask,
u16 tsr, bool rep, u16 size,
A_UINT32 valid);
u32 valid);
int wmi_get_stats_cmd(struct wmi_t *wmip);
......@@ -237,7 +237,7 @@ u8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
int wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, int tspecCompliance);
#ifdef CONFIG_HOST_TCMD_SUPPORT
int wmi_test_cmd(struct wmi_t *wmip, u8 *buf, A_UINT32 len);
int wmi_test_cmd(struct wmi_t *wmip, u8 *buf, u32 len);
#endif
int wmi_set_bt_status_cmd(struct wmi_t *wmip, u8 streamType, u8 status);
......@@ -269,12 +269,12 @@ int wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * c
int wmi_get_btcoex_stats_cmd(struct wmi_t * wmip);
int wmi_SGI_cmd(struct wmi_t *wmip, A_UINT32 sgiMask, u8 sgiPERThreshold);
int wmi_SGI_cmd(struct wmi_t *wmip, u32 sgiMask, u8 sgiPERThreshold);
/*
* This function is used to configure the fix rates mask to the target.
*/
int wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask);
int wmi_set_fixrates_cmd(struct wmi_t *wmip, u32 fixRatesMask);
int wmi_get_ratemask_cmd(struct wmi_t *wmip);
int wmi_set_authmode_cmd(struct wmi_t *wmip, u8 mode);
......@@ -307,10 +307,10 @@ int wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
WMI_ADD_WOW_PATTERN_CMD *cmd, u8 *pattern, u8 *mask, u8 pattern_size);
int wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
WMI_DEL_WOW_PATTERN_CMD *cmd);
int wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
int wmi_set_wsc_status_cmd(struct wmi_t *wmip, u32 status);
int
wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, char *buffer);
wmi_set_params_cmd(struct wmi_t *wmip, u32 opcode, u32 length, char *buffer);
int
wmi_set_mcast_filter_cmd(struct wmi_t *wmip, u8 dot1, u8 dot2, u8 dot3, u8 dot4);
......@@ -323,18 +323,18 @@ wmi_mcast_filter_cmd(struct wmi_t *wmip, u8 enable);
bss_t *
wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
A_UINT32 ssidLength, bool bIsWPA2, bool bMatchSSID);
u32 ssidLength, bool bIsWPA2, bool bMatchSSID);
void
wmi_node_return (struct wmi_t *wmip, bss_t *bss);
void
wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge);
wmi_set_nodeage(struct wmi_t *wmip, u32 nodeAge);
#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
int wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins);
int wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr);
int wmi_prof_cfg_cmd(struct wmi_t *wmip, u32 period, u32 nbins);
int wmi_prof_addr_set_cmd(struct wmi_t *wmip, u32 addr);
int wmi_prof_start_cmd(struct wmi_t *wmip);
int wmi_prof_stop_cmd(struct wmi_t *wmip);
int wmi_prof_count_get_cmd(struct wmi_t *wmip);
......@@ -377,10 +377,10 @@ int
wmi_set_pvb_cmd(struct wmi_t *wmip, u16 aid, bool flag);
int
wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period);
wmi_ap_conn_inact_time(struct wmi_t *wmip, u32 period);
int
wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell);
wmi_ap_bgscan_time(struct wmi_t *wmip, u32 period, u32 dwell);
int
wmi_ap_set_dtim(struct wmi_t *wmip, u8 dtim);
......@@ -398,7 +398,7 @@ int
wmi_send_hci_cmd(struct wmi_t *wmip, u8 *buf, u16 sz);
int
wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray);
wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, u32 *pMaskArray);
int
wmi_setup_aggr_cmd(struct wmi_t *wmip, u8 tid);
......@@ -423,14 +423,13 @@ wmi_set_pmk_cmd(struct wmi_t *wmip, u8 *pmk);
u16 wmi_ieee2freq (int chan);
A_UINT32
wmi_freq2ieee (u16 freq);
u32 wmi_freq2ieee (u16 freq);
bss_t *
wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
A_UINT32 ssidLength,
A_UINT32 dot11AuthMode, A_UINT32 authMode,
A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
u32 ssidLength,
u32 dot11AuthMode, u32 authMode,
u32 pairwiseCryptoType, u32 grpwiseCryptoTyp);
#ifdef __cplusplus
}
......
drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
View file @ e1ce2a3a
......@@ -42,7 +42,7 @@
typedef struct {
PSCmdPacket *HciCmdList;
A_UINT32 num_packets;
u32 num_packets;
AR3K_CONFIG_INFO *dev;
}HciCommandListParam;
......@@ -52,11 +52,11 @@ int SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
u8 **ppEventBuffer,
u8 **ppBufferToFree);
A_UINT32 Rom_Version;
A_UINT32 Build_Version;
u32 Rom_Version;
u32 Build_Version;
extern bool BDADDR;
int getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code);
int getDeviceType(AR3K_CONFIG_INFO *pConfig, u32 *code);
int ReadVersionInfo(AR3K_CONFIG_INFO *pConfig);
#ifndef HCI_TRANSPORT_SDIO
......@@ -66,7 +66,7 @@ A_UCHAR *HciEventpacket;
rwlock_t syncLock;
wait_queue_t Eventwait;
int PSHciWritepacket(struct hci_dev*,A_UCHAR* Data, A_UINT32 len);
int PSHciWritepacket(struct hci_dev*,A_UCHAR* Data, u32 len);
extern char *bdaddr;
#endif /* HCI_TRANSPORT_SDIO */
......@@ -75,7 +75,7 @@ int write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr,int type);
int PSSendOps(void *arg);
#ifdef BT_PS_DEBUG
void Hci_log(A_UCHAR * log_string,A_UCHAR *data,A_UINT32 len)
void Hci_log(A_UCHAR * log_string,A_UCHAR *data,u32 len)
{
int i;
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s : ",log_string));
......@@ -135,13 +135,13 @@ int PSSendOps(void *arg)
int status = 0;
PSCmdPacket *HciCmdList; /* List storing the commands */
const struct firmware* firmware;
A_UINT32 numCmds;
u32 numCmds;
u8 *event;
u8 *bufferToFree;
struct hci_dev *device;
A_UCHAR *buffer;
A_UINT32 len;
A_UINT32 DevType;
u32 len;
u32 DevType;
A_UCHAR *PsFileName;
A_UCHAR *patchFileName;
A_UCHAR *path = NULL;
......@@ -531,12 +531,12 @@ int ReadVersionInfo(AR3K_CONFIG_INFO *pConfig)
}
return result;
}
int getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code)
int getDeviceType(AR3K_CONFIG_INFO *pConfig, u32 *code)
{
u8 hciCommand[] = {0x05,0xfc,0x05,0x00,0x00,0x00,0x00,0x04};
u8 *event;
u8 *bufferToFree = NULL;
A_UINT32 reg;
u32 reg;
int result = A_ERROR;
*code = 0;
hciCommand[3] = (u8)(FPGA_REGISTER & 0xFF);
......
drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
View file @ e1ce2a3a
......@@ -87,8 +87,8 @@ enum eType {
typedef struct tPsTagEntry
{
A_UINT32 TagId;
A_UINT32 TagLen;
u32 TagId;
u32 TagLen;
u8 *TagData;
} tPsTagEntry, *tpPsTagEntry;
......@@ -115,25 +115,25 @@ typedef struct ST_READ_STATUS {
/* Stores the number of PS Tags */
static A_UINT32 Tag_Count = 0;
static u32 Tag_Count = 0;
/* Stores the number of patch commands */
static A_UINT32 Patch_Count = 0;
static A_UINT32 Total_tag_lenght = 0;
static u32 Patch_Count = 0;
static u32 Total_tag_lenght = 0;
bool BDADDR = false;
A_UINT32 StartTagId;
u32 StartTagId;
tPsTagEntry PsTagEntry[RAMPS_MAX_PS_TAGS_PER_FILE];
tRamPatch RamPatch[MAX_NUM_PATCH_ENTRY];
int AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat);
char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos);
char *AthGetLine(char *buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos);
static int AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index);
int AthParseFilesUnified(A_UCHAR *srcbuffer,u32 srclen, int FileFormat);
char AthReadChar(A_UCHAR *buffer, u32 len,u32 *pos);
char *AthGetLine(char *buffer, int maxlen, A_UCHAR *srcbuffer,u32 len,u32 *pos);
static int AthPSCreateHCICommand(A_UCHAR Opcode, u32 Param1,PSCmdPacket *PSPatchPacket,u32 *index);
/* Function to reads the next character from the input buffer */
char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos)
char AthReadChar(A_UCHAR *buffer, u32 len,u32 *pos)
{
char Ch;
if(buffer == NULL || *pos >=len )
......@@ -315,14 +315,14 @@ unsigned int uReadDataInSection(char *pCharLine, ST_PS_DATA_FORMAT stPS_DataForm
return (0x0FFF);
}
}
int AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat)
int AthParseFilesUnified(A_UCHAR *srcbuffer,u32 srclen, int FileFormat)
{
char *Buffer;
char *pCharLine;
u8 TagCount;
u16 ByteCount;
u8 ParseSection=RAM_PS_SECTION;
A_UINT32 pos;
u32 pos;
......@@ -558,7 +558,7 @@ int AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat)
/********************/
int GetNextTwoChar(A_UCHAR *srcbuffer,A_UINT32 len, A_UINT32 *pos, char *buffer)
int GetNextTwoChar(A_UCHAR *srcbuffer,u32 len, u32 *pos, char *buffer)
{
unsigned char ch;
......@@ -579,7 +579,7 @@ int GetNextTwoChar(A_UCHAR *srcbuffer,A_UINT32 len, A_UINT32 *pos, char *buffer)
return A_OK;
}
int AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen)
int AthDoParsePatch(A_UCHAR *patchbuffer, u32 patchlen)
{
char Byte[3];
......@@ -588,7 +588,7 @@ int AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen)
int count;
int i,j,k;
int data;
A_UINT32 filepos;
u32 filepos;
Byte[2] = '\0';
j = 0;
filepos = 0;
......@@ -659,7 +659,7 @@ int AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen)
/********************/
int AthDoParsePS(A_UCHAR *srcbuffer, A_UINT32 srclen)
int AthDoParsePS(A_UCHAR *srcbuffer, u32 srclen)
{
int status;
int i;
......@@ -713,7 +713,7 @@ int AthDoParsePS(A_UCHAR *srcbuffer, A_UINT32 srclen)
return status;
}
char *AthGetLine(char *buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos)
char *AthGetLine(char *buffer, int maxlen, A_UCHAR *srcbuffer,u32 len,u32 *pos)
{
int count;
......@@ -764,13 +764,13 @@ static void LoadHeader(A_UCHAR *HCI_PS_Command,A_UCHAR opcode,int length,int ind
/////////////////////////
//
int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets)
int AthCreateCommandList(PSCmdPacket **HciPacketList, u32 *numPackets)
{
u8 count;
A_UINT32 NumcmdEntry = 0;
u32 NumcmdEntry = 0;
A_UINT32 Crc = 0;
u32 Crc = 0;
*numPackets = 0;
......@@ -785,7 +785,7 @@ int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets)
if(Patch_Count > 0) {
NumcmdEntry++; /* Patch Enable Command */
}
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size %d \r\n",NumcmdEntry,(A_UINT32)sizeof(PSCmdPacket) * NumcmdEntry));
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size %d \r\n",NumcmdEntry,(u32)sizeof(PSCmdPacket) * NumcmdEntry));
(*HciPacketList) = A_MALLOC(sizeof(PSCmdPacket) * NumcmdEntry);
if(NULL == *HciPacketList) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("memory allocation failed \r\n"));
......@@ -833,10 +833,10 @@ int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets)
////////////////////////
/////////////
static int AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index)
static int AthPSCreateHCICommand(A_UCHAR Opcode, u32 Param1,PSCmdPacket *PSPatchPacket,u32 *index)
{
A_UCHAR *HCI_PS_Command;
A_UINT32 Length;
u32 Length;
int i,j;
switch(Opcode)
......@@ -955,7 +955,7 @@ static int AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PS
}
return A_OK;
}
int AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets)
int AthFreeCommandList(PSCmdPacket **HciPacketList, u32 numPackets)
{
int i;
if(*HciPacketList == NULL) {
......
drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
View file @ e1ce2a3a
......@@ -48,13 +48,12 @@
/* Helper data type declaration */
#ifndef A_UINT32
#define A_UCHAR unsigned char
#define A_UINT32 unsigned long
#ifndef u32 #define A_UCHAR unsigned char
#define u32 unsigned long
#define u16 unsigned short
#define u8 unsigned char
#define bool unsigned char
#endif /* A_UINT32 */
#endif /* u32 */
#define ATH_DEBUG_ERR (1 << 0)
#define ATH_DEBUG_WARN (1 << 1)
......@@ -104,10 +103,10 @@ typedef struct PSCmdPacket
} PSCmdPacket;
/* Parses a Patch information buffer and store it in global structure */
int AthDoParsePatch(A_UCHAR *, A_UINT32);
int AthDoParsePatch(A_UCHAR *, u32 );
/* parses a PS information buffer and stores it in a global structure */
int AthDoParsePS(A_UCHAR *, A_UINT32);
int AthDoParsePS(A_UCHAR *, u32 );
/*
* Uses the output of Both AthDoParsePS and AthDoParsePatch APIs to form HCI command array with
......@@ -120,8 +119,8 @@ int AthDoParsePS(A_UCHAR *, A_UINT32);
* PS Tag Command(s)
*
*/
int AthCreateCommandList(PSCmdPacket **, A_UINT32 *);
int AthCreateCommandList(PSCmdPacket **, u32 *);
/* Cleanup the dynamically allicated HCI command list */
int AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets);
int AthFreeCommandList(PSCmdPacket **HciPacketList, u32 numPackets);
#endif /* __AR3KPSPARSER_H */
drivers/staging/ath6kl/miscdrv/common_drv.c
View file @ e1ce2a3a
This diff is collapsed.
drivers/staging/ath6kl/miscdrv/miscdrv.h
View file @ e1ce2a3a
......@@ -27,7 +27,7 @@
#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
AR6002_HOST_INTEREST_ITEM_ADDRESS(item)
A_UINT32 ar6kRev2Array[][128] = {
u32 ar6kRev2Array[][128] = {
{0xFFFF, 0xFFFF}, // No Patches
};
......
drivers/staging/ath6kl/os/linux/ar6000_pm.c
View file @ e1ce2a3a
......@@ -194,7 +194,7 @@ static void ar6000_wow_suspend(AR_SOFTC_T *ar)
ar->arWowState = WLAN_WOW_STATE_SUSPENDING;
if (ar->arTxPending[ar->arControlEp]) {
A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
u32 timeleft = wait_event_interruptible_timeout(arEvent,
ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
if (!timeleft || signal_pending(current)) {
/* what can I do? wow resume at once */
......@@ -290,7 +290,7 @@ void ar6000_check_wow_status(AR_SOFTC_T *ar, struct sk_buff *skb, bool isEvent)
}
}
int ar6000_power_change_ev(void *context, A_UINT32 config)
int ar6000_power_change_ev(void *context, u32 config)
{
AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
int status = A_OK;
......@@ -375,7 +375,7 @@ ar6000_setup_cut_power_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
if (status == A_PENDING) {
#ifdef ANDROID_ENV
/* Wait for WMI ready event */
A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
u32 timeleft = wait_event_interruptible_timeout(arEvent,
(ar->arWmiReady == true), wmitimeout * HZ);
if (!timeleft || signal_pending(current)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : Failed to get wmi ready \n"));
......@@ -516,7 +516,7 @@ ar6000_setup_deep_sleep_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
break;
}
if (ar->arTxPending[ar->arControlEp]) {
A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
u32 timeleft = wait_event_interruptible_timeout(arEvent,
ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
if (!timeleft || signal_pending(current)) {
status = A_ERROR;
......@@ -651,7 +651,7 @@ ar6000_update_wlan_pwr_state(struct ar6_softc *ar, AR6000_WLAN_STATE state, bool
}
int
ar6000_set_bt_hw_state(struct ar6_softc *ar, A_UINT32 enable)
ar6000_set_bt_hw_state(struct ar6_softc *ar, u32 enable)
{
#ifdef CONFIG_PM
bool off = (enable == 0);
......
drivers/staging/ath6kl/os/linux/cfg80211.c
View file @ e1ce2a3a
......@@ -183,7 +183,7 @@ ar6k_set_auth_type(AR_SOFTC_T *ar, enum nl80211_auth_type auth_type)
}
static int
ar6k_set_cipher(AR_SOFTC_T *ar, A_UINT32 cipher, bool ucast)
ar6k_set_cipher(AR_SOFTC_T *ar, u32 cipher, bool ucast)
{
u8 *ar_cipher = ucast ? &ar->arPairwiseCrypto :
&ar->arGroupCrypto;
......@@ -225,7 +225,7 @@ ar6k_set_cipher(AR_SOFTC_T *ar, A_UINT32 cipher, bool ucast)
}
static void
ar6k_set_key_mgmt(AR_SOFTC_T *ar, A_UINT32 key_mgmt)
ar6k_set_key_mgmt(AR_SOFTC_T *ar, u32 key_mgmt)
{
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, key_mgmt));
......@@ -726,7 +726,7 @@ ar6k_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
{
AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
int ret = 0;
A_UINT32 forceFgScan = 0;
u32 forceFgScan = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
......@@ -1056,7 +1056,7 @@ ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, u8 keyid, bool ismcast)
}
static int
ar6k_cfg80211_set_wiphy_params(struct wiphy *wiphy, A_UINT32 changed)
ar6k_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
{
AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
......@@ -1365,7 +1365,7 @@ ar6k_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
static const
A_UINT32 cipher_suites[] = {
u32 cipher_suites[] = {
WLAN_CIPHER_SUITE_WEP40,
WLAN_CIPHER_SUITE_WEP104,
WLAN_CIPHER_SUITE_TKIP,
......
drivers/staging/ath6kl/os/linux/eeprom.c
View file @ e1ce2a3a
......@@ -54,7 +54,7 @@ char *p_mac = NULL;
//
static A_UCHAR eeprom_data[EEPROM_SZ];
static A_UINT32 sys_sleep_reg;
static u32 sys_sleep_reg;
static HIF_DEVICE *p_bmi_device;
//
......@@ -127,28 +127,28 @@ update_mac(unsigned char *eeprom, int size, unsigned char *macaddr)
/* Read a Target register and return its value. */
inline void
BMI_read_reg(A_UINT32 address, A_UINT32 *pvalue)
BMI_read_reg(u32 address, u32 *pvalue)
{
BMIReadSOCRegister(p_bmi_device, address, pvalue);
}
/* Write a value to a Target register. */
inline void
BMI_write_reg(A_UINT32 address, A_UINT32 value)
BMI_write_reg(u32 address, u32 value)
{
BMIWriteSOCRegister(p_bmi_device, address, value);
}
/* Read Target memory word and return its value. */
inline void
BMI_read_mem(A_UINT32 address, A_UINT32 *pvalue)
BMI_read_mem(u32 address, u32 *pvalue)
{
BMIReadMemory(p_bmi_device, address, (A_UCHAR*)(pvalue), 4);
}
/* Write a word to a Target memory. */
inline void
BMI_write_mem(A_UINT32 address, u8 *p_data, A_UINT32 sz)
BMI_write_mem(u32 address, u8 *p_data, u32 sz)
{
BMIWriteMemory(p_bmi_device, address, (A_UCHAR*)(p_data), sz);
}
......@@ -160,7 +160,7 @@ BMI_write_mem(A_UINT32 address, u8 *p_data, A_UINT32 sz)
static void
enable_SI(HIF_DEVICE *p_device)
{
A_UINT32 regval;
u32 regval;
printk("%s\n", __FUNCTION__);
......@@ -200,7 +200,7 @@ enable_SI(HIF_DEVICE *p_device)
static void
disable_SI(void)
{
A_UINT32 regval;
u32 regval;
printk("%s\n", __FUNCTION__);
......@@ -218,7 +218,7 @@ disable_SI(void)
static void
request_8byte_read(int offset)
{
A_UINT32 regval;
u32 regval;
// printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
......@@ -241,9 +241,9 @@ request_8byte_read(int offset)
* writing values from Target TX_DATA registers.
*/
static void
request_4byte_write(int offset, A_UINT32 data)
request_4byte_write(int offset, u32 data)
{
A_UINT32 regval;
u32 regval;
printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
......@@ -269,7 +269,7 @@ request_4byte_write(int offset, A_UINT32 data)
static bool
request_in_progress(void)
{
A_UINT32 regval;
u32 regval;
/* Wait for DONE_INT in SI_CS */
BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
......@@ -288,7 +288,7 @@ request_in_progress(void)
static void eeprom_type_detect(void)
{
A_UINT32 regval;
u32 regval;
u8 i = 0;
request_8byte_read(0x100);
......@@ -310,7 +310,7 @@ static void eeprom_type_detect(void)
* and return them to the caller.
*/
inline void
read_8byte_results(A_UINT32 *data)
read_8byte_results(u32 *data)
{
/* Read SI_RX_DATA0 and SI_RX_DATA1 */
BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
......@@ -339,7 +339,7 @@ wait_for_eeprom_completion(void)
* waits for it to complete, and returns the result.
*/
static void
fetch_8bytes(int offset, A_UINT32 *data)
fetch_8bytes(int offset, u32 *data)
{
request_8byte_read(offset);
wait_for_eeprom_completion();
......@@ -354,7 +354,7 @@ fetch_8bytes(int offset, A_UINT32 *data)
* and waits for it to complete.
*/
inline void
commit_4bytes(int offset, A_UINT32 data)
commit_4bytes(int offset, u32 data)
{
request_4byte_write(offset, data);
wait_for_eeprom_completion();
......@@ -363,8 +363,8 @@ commit_4bytes(int offset, A_UINT32 data)
#ifdef ANDROID_ENV
void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
{
A_UINT32 first_word;
A_UINT32 board_data_addr;
u32 first_word;
u32 board_data_addr;
int i;
printk("%s: Enter\n", __FUNCTION__);
......@@ -437,17 +437,17 @@ void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
* Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
*/
fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0]));
fetch_8bytes(0, (u32 *)(&eeprom_data[0]));
/* Check the first word of EEPROM for validity */
first_word = *((A_UINT32 *)eeprom_data);
first_word = *((u32 *)eeprom_data);
if ((first_word == 0) || (first_word == 0xffffffff)) {
printk("Did not find EEPROM with valid Board Data.\n");
}
for (i=8; i<EEPROM_SZ; i+=8) {
fetch_8bytes(i, (A_UINT32 *)(&eeprom_data[i]));
fetch_8bytes(i, (u32 *)(&eeprom_data[i]));
}
}
......@@ -562,9 +562,9 @@ void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
/* Record the fact that Board Data IS initialized */
{
A_UINT32 one = 1;
u32 one = 1;
BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
(u8 *)&one, sizeof(A_UINT32));
(u8 *)&one, sizeof(u32));
}
disable_SI();
......
drivers/staging/ath6kl/os/linux/export_hci_transport.c
View file @ e1ce2a3a
......@@ -46,7 +46,7 @@ int (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, bo
int (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans,
HTC_PACKET *pPacket,
int MaxPollMS);
int (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
int (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, u32 Baud);
int (*_HCI_TransportEnablePowerMgmt)(HCI_TRANSPORT_HANDLE HciTrans, bool Enable);
extern HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks;
......@@ -82,24 +82,24 @@ ar6000_get_hif_dev(HIF_DEVICE *device, void *config)
}
int ar6000_set_uart_config(HIF_DEVICE *hifDevice,
A_UINT32 scale,
A_UINT32 step)
u32 scale,
u32 step)
{
A_UINT32 regAddress;
A_UINT32 regVal;
u32 regAddress;
u32 regVal;
int status;
regAddress = WLAN_UART_BASE_ADDRESS | UART_CLKDIV_ADDRESS;
regVal = ((A_UINT32)scale << 16) | step;
regVal = ((u32)scale << 16) | step;
/* change the HCI UART scale/step values through the diagnostic window */
status = ar6000_WriteRegDiag(hifDevice, &regAddress, &regVal);
return status;
}
int ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data)
int ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, u32 *data)
{
A_UINT32 regAddress;
u32 regAddress;
int status;
regAddress = WLAN_RTC_BASE_ADDRESS | WLAN_CPU_CLOCK_ADDRESS;
......
drivers/staging/ath6kl/os/linux/hci_bridge.c
View file @ e1ce2a3a
......@@ -221,7 +221,7 @@ static int ar6000_hci_transport_ready(HCI_TRANSPORT_HANDLE HCIHandle,
{
AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
int status;
A_UINT32 address, hci_uart_pwr_mgmt_params;
u32 address, hci_uart_pwr_mgmt_params;
// AR3K_CONFIG_INFO ar3kconfig;
pHcidevInfo->pHCIDev = HCIHandle;
......
drivers/staging/ath6kl/os/linux/ioctl.c
View file @ e1ce2a3a
This diff is collapsed.
drivers/staging/ath6kl/os/linux/netbuf.c
View file @ e1ce2a3a
......@@ -89,8 +89,7 @@ a_netbuf_free(void *bufPtr)
dev_kfree_skb(skb);
}
A_UINT32
a_netbuf_to_len(void *bufPtr)
u32 a_netbuf_to_len(void *bufPtr)
{
return (((struct sk_buff *)bufPtr)->len);
}
......
drivers/staging/ath6kl/wlan/src/wlan_node.c
View file @ e1ce2a3a
This diff is collapsed.
drivers/staging/ath6kl/wmi/wmi.c
View file @ e1ce2a3a
This diff is collapsed.
drivers/staging/ath6kl/wmi/wmi_host.h
View file @ e1ce2a3a
This diff is collapsed.
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