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Commit e5edf654 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
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drm/msm/dpu: inline IRQ_n_MASK defines 

IRQ masks are rarely shared between different DPU revisions. Inline them
to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530875/
Link: https://lore.kernel.org/r/20230404130622.509628-36-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent d16b77dd
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Inline Side-by-side
Showing with 99 additions and 86 deletions
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
View file @ e5edf654
......@@ -197,7 +197,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
.vbif = msm8998_vbif,
.reg_dma_count = 0,
.perf = &msm8998_perf_data,
.mdss_irqs = IRQ_SM8250_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
View file @ e5edf654
......@@ -196,7 +196,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sdm845_regdma,
.perf = &sdm845_perf_data,
.mdss_irqs = IRQ_SDM845_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View file @ e5edf654
......@@ -223,7 +223,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sm8150_regdma,
.perf = &sm8150_perf_data,
.mdss_irqs = IRQ_SDM845_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View file @ e5edf654
......@@ -201,7 +201,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sm8150_regdma,
.perf = &sc8180x_perf_data,
.mdss_irqs = IRQ_SC8180X_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR) | \
BIT(MDP_INTF5_INTR) | \
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
View file @ e5edf654
......@@ -231,7 +231,14 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sm8250_regdma,
.perf = &sm8250_perf_data,
.mdss_irqs = IRQ_SM8250_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
View file @ e5edf654
......@@ -146,7 +146,11 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sdm845_regdma,
.perf = &sc7180_perf_data,
.mdss_irqs = IRQ_SC7180_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
View file @ e5edf654
......@@ -119,7 +119,11 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm6115_perf_data,
.mdss_irqs = IRQ_SC7180_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
View file @ e5edf654
......@@ -109,7 +109,11 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &qcm2290_perf_data,
.mdss_irqs = IRQ_SC7180_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
View file @ e5edf654
......@@ -214,7 +214,13 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sm8350_regdma,
.perf = &sm8350_perf_data,
.mdss_irqs = IRQ_SM8350_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
View file @ e5edf654
......@@ -147,7 +147,12 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sc7280_perf_data,
.mdss_irqs = IRQ_SC7280_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF5_7xxx_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
View file @ e5edf654
......@@ -205,7 +205,18 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sc8280xp_regdma,
.perf = &sc8280xp_perf_data,
.mdss_irqs = IRQ_SC8280XP_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR) | \
BIT(MDP_INTF4_7xxx_INTR) | \
BIT(MDP_INTF5_7xxx_INTR) | \
BIT(MDP_INTF6_7xxx_INTR) | \
BIT(MDP_INTF7_7xxx_INTR) | \
BIT(MDP_INTF8_7xxx_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
View file @ e5edf654
......@@ -222,7 +222,13 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sm8450_regdma,
.perf = &sm8450_perf_data,
.mdss_irqs = IRQ_SM8450_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
View file @ e5edf654
......@@ -227,7 +227,13 @@ static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = &sm8450_regdma,
.perf = &sm8550_perf_data,
.mdss_irqs = IRQ_SM8450_MASK,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR),
};
#endif
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View file @ e5edf654
......@@ -102,79 +102,6 @@
#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR))
#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR))
#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF5_7xxx_INTR))
#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR))
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_INTR) | \
BIT(MDP_INTF1_INTR) | \
BIT(MDP_INTF2_INTR) | \
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR) | \
BIT(MDP_INTF5_INTR) | \
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR))
#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR) | \
BIT(MDP_INTF4_7xxx_INTR) | \
BIT(MDP_INTF5_7xxx_INTR) | \
BIT(MDP_INTF6_7xxx_INTR) | \
BIT(MDP_INTF7_7xxx_INTR) | \
BIT(MDP_INTF8_7xxx_INTR))
#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR))
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
......
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