Commit e6a70a02 authored by David S. Miller's avatar David S. Miller

Merge tag 'wireless-drivers-next-2021-08-22' of...

Merge tag 'wireless-drivers-next-2021-08-22' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next

Kalle Valo says:

====================
wireless-drivers-next patches for v5.15

First set of patches for v5.15. This got delayed as I have been mostly
offline for the last few weeks. The biggest change is removal of
prism54 driver, otherwise just smaller changes.

Major changes:

ath5k, ath9k, ath10k, ath11k:

* switch from 'pci_' to 'dma_' API

brcmfmac

* allow per-board firmware binaries

* add support 43752 SDIO device

prism54

* remove the obsoleted driver, everyone should be using p54 driver instead
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 056b29ae 0dc62413
......@@ -14953,13 +14953,6 @@ S: Maintained
F: include/linux/printk.h
F: kernel/printk/
PRISM54 WIRELESS DRIVER
M: Luis Chamberlain <mcgrof@kernel.org>
L: linux-wireless@vger.kernel.org
S: Obsolete
W: https://wireless.wiki.kernel.org/en/users/Drivers/p54
F: drivers/net/wireless/intersil/prism54/
PROC FILESYSTEM
L: linux-kernel@vger.kernel.org
L: linux-fsdevel@vger.kernel.org
......
......@@ -3393,19 +3393,12 @@ static int ath10k_pci_claim(struct ath10k *ar)
}
/* Target expects 32 bit DMA. Enforce it. */
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
goto err_region;
}
ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
if (ret) {
ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
ret);
goto err_region;
}
pci_set_master(pdev);
/* Arrange for access to Target SoC registers. */
......
......@@ -1406,11 +1406,6 @@ ath11k_update_per_peer_tx_stats(struct ath11k *ar,
* Firmware rate's control to be skipped for this?
*/
if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) {
ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
return;
}
if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
return;
......
......@@ -933,20 +933,14 @@ static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
goto disable_device;
}
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
ret = dma_set_mask_and_coherent(&pdev->dev,
DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
if (ret) {
ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
ATH11K_PCI_DMA_MASK, ret);
goto release_region;
}
ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
if (ret) {
ath11k_err(ab, "failed to set pci consistent dma mask to %d: %d\n",
ATH11K_PCI_DMA_MASK, ret);
goto release_region;
}
pci_set_master(pdev);
ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
......
......@@ -191,7 +191,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
}
/* XXX 32-bit addressing only */
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(&pdev->dev, "32-bit DMA not available\n");
goto err_dis;
......
......@@ -896,18 +896,12 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (pcim_enable_device(pdev))
return -EIO;
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
pr_err("32-bit DMA not available\n");
return ret;
}
ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
if (ret) {
pr_err("32-bit DMA consistent DMA enable failed\n");
return ret;
}
/*
* Cache line size is used to size and align various
* structures used to communicate with the hardware.
......
......@@ -23,7 +23,8 @@ brcmfmac-objs += \
feature.o \
btcoex.o \
vendor.o \
pno.o
pno.o \
xtlv.o
brcmfmac-$(CONFIG_BRCMFMAC_PROTO_BCDC) += \
bcdc.o \
fwsignal.o
......
......@@ -128,7 +128,8 @@ int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev)
if (sdiodev->bus_if->chip == BRCM_CC_43362_CHIP_ID) {
/* assign GPIO to SDIO core */
addr = CORE_CC_REG(SI_ENUM_BASE, gpiocontrol);
addr = brcmf_chip_enum_base(sdiodev->func1->device);
addr = CORE_CC_REG(addr, gpiocontrol);
gpiocontrol = brcmf_sdiod_readl(sdiodev, addr, &ret);
gpiocontrol |= 0x2;
brcmf_sdiod_writel(sdiodev, addr, gpiocontrol, &ret);
......@@ -990,6 +991,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4359),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_CYPRESS_43752),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_CYPRESS_89359),
{ /* end: all zeroes */ }
};
......
......@@ -139,6 +139,8 @@ struct sbconfig {
u32 sbidhigh; /* identification */
};
#define INVALID_RAMBASE ((u32)(~0))
/* bankidx and bankinfo reg defines corerev >= 8 */
#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
#define SOCRAM_BANKINFO_SZMASK 0x0000007f
......@@ -527,7 +529,7 @@ static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
int idx = 1;
list_for_each_entry(core, &ci->cores, list) {
brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n",
idx++, core->pub.id, core->pub.rev, core->pub.base,
core->wrapbase);
......@@ -727,11 +729,13 @@ static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
case BRCM_CC_4364_CHIP_ID:
case CY_CC_4373_CHIP_ID:
return 0x160000;
case CY_CC_43752_CHIP_ID:
return 0x170000;
default:
brcmf_err("unknown chip: %s\n", ci->pub.name);
break;
}
return 0;
return INVALID_RAMBASE;
}
int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
......@@ -746,7 +750,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
mem_core = container_of(mem, struct brcmf_core_priv, pub);
ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
if (!ci->pub.rambase) {
if (ci->pub.rambase == INVALID_RAMBASE) {
brcmf_err("RAM base not provided with ARM CR4 core\n");
return -EINVAL;
}
......@@ -757,7 +761,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
pub);
ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
if (!ci->pub.rambase) {
if (ci->pub.rambase == INVALID_RAMBASE) {
brcmf_err("RAM base not provided with ARM CA7 core\n");
return -EINVAL;
}
......@@ -894,7 +898,8 @@ int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
u32 base, wrap;
int err;
eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
eromaddr = ci->ops->read32(ci->ctx,
CORE_CC_REG(ci->pub.enum_base, eromptr));
while (desc_type != DMP_DESC_EOT) {
val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
......@@ -942,6 +947,11 @@ int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
return 0;
}
u32 brcmf_chip_enum_base(u16 devid)
{
return SI_ENUM_BASE_DEFAULT;
}
static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
{
struct brcmf_core *core;
......@@ -954,7 +964,8 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
* For different chiptypes or old sdio hosts w/o chipcommon,
* other ways of recognition should be added here.
*/
regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
regdata = ci->ops->read32(ci->ctx,
CORE_CC_REG(ci->pub.enum_base, chipid));
ci->pub.chip = regdata & CID_ID_MASK;
ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
......@@ -974,7 +985,7 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
ci->resetcore = brcmf_chip_sb_resetcore;
core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
SI_ENUM_BASE, 0);
SI_ENUM_BASE_DEFAULT, 0);
brcmf_chip_sb_corerev(ci, core);
core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
BCM4329_CORE_BUS_BASE, 0);
......@@ -1088,7 +1099,7 @@ static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
return ret;
}
struct brcmf_chip *brcmf_chip_attach(void *ctx,
struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
const struct brcmf_buscore_ops *ops)
{
struct brcmf_chip_priv *chip;
......@@ -1113,6 +1124,7 @@ struct brcmf_chip *brcmf_chip_attach(void *ctx,
chip->num_cores = 0;
chip->ops = ops;
chip->ctx = ctx;
chip->pub.enum_base = brcmf_chip_enum_base(devid);
err = ops->prepare(ctx);
if (err < 0)
......@@ -1411,6 +1423,7 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
reg = chip->ops->read32(chip->ctx, addr);
return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
case BRCM_CC_4359_CHIP_ID:
case CY_CC_43752_CHIP_ID:
case CY_CC_43012_CHIP_ID:
addr = CORE_CC_REG(pmu->base, retention_ctl);
reg = chip->ops->read32(chip->ctx, addr);
......
......@@ -15,6 +15,7 @@
*
* @chip: chip identifier.
* @chiprev: chip revision.
* @enum_base: base address of core enumeration space.
* @cc_caps: chipcommon core capabilities.
* @cc_caps_ext: chipcommon core extended capabilities.
* @pmucaps: PMU capabilities.
......@@ -27,6 +28,7 @@
struct brcmf_chip {
u32 chip;
u32 chiprev;
u32 enum_base;
u32 cc_caps;
u32 cc_caps_ext;
u32 pmucaps;
......@@ -70,7 +72,7 @@ struct brcmf_buscore_ops {
};
int brcmf_chip_get_raminfo(struct brcmf_chip *pub);
struct brcmf_chip *brcmf_chip_attach(void *ctx,
struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
const struct brcmf_buscore_ops *ops);
void brcmf_chip_detach(struct brcmf_chip *chip);
struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid);
......@@ -85,5 +87,6 @@ void brcmf_chip_set_passive(struct brcmf_chip *ci);
bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec);
bool brcmf_chip_sr_capable(struct brcmf_chip *pub);
char *brcmf_chip_name(u32 chipid, u32 chiprev, char *buf, uint len);
u32 brcmf_chip_enum_base(u16 devid);
#endif /* BRCMF_AXIDMP_H */
......@@ -431,8 +431,6 @@ struct brcmf_fw {
void (*done)(struct device *dev, int err, struct brcmf_fw_request *req);
};
static void brcmf_fw_request_done(const struct firmware *fw, void *ctx);
#ifdef CONFIG_EFI
/* In some cases the EFI-var stored nvram contains "ccode=ALL" or "ccode=XV"
* to specify "worldwide" compatible settings, but these 2 ccode-s do not work
......@@ -594,28 +592,47 @@ static int brcmf_fw_complete_request(const struct firmware *fw,
return (cur->flags & BRCMF_FW_REQF_OPTIONAL) ? 0 : ret;
}
static char *brcm_alt_fw_path(const char *path, const char *board_type)
{
char alt_path[BRCMF_FW_NAME_LEN];
char suffix[5];
strscpy(alt_path, path, BRCMF_FW_NAME_LEN);
/* At least one character + suffix */
if (strlen(alt_path) < 5)
return NULL;
/* strip .txt or .bin at the end */
strscpy(suffix, alt_path + strlen(alt_path) - 4, 5);
alt_path[strlen(alt_path) - 4] = 0;
strlcat(alt_path, ".", BRCMF_FW_NAME_LEN);
strlcat(alt_path, board_type, BRCMF_FW_NAME_LEN);
strlcat(alt_path, suffix, BRCMF_FW_NAME_LEN);
return kstrdup(alt_path, GFP_KERNEL);
}
static int brcmf_fw_request_firmware(const struct firmware **fw,
struct brcmf_fw *fwctx)
{
struct brcmf_fw_item *cur = &fwctx->req->items[fwctx->curpos];
int ret;
/* nvram files are board-specific, first try a board-specific path */
/* Files can be board-specific, first try a board-specific path */
if (cur->type == BRCMF_FW_TYPE_NVRAM && fwctx->req->board_type) {
char alt_path[BRCMF_FW_NAME_LEN];
char *alt_path;
strlcpy(alt_path, cur->path, BRCMF_FW_NAME_LEN);
/* strip .txt at the end */
alt_path[strlen(alt_path) - 4] = 0;
strlcat(alt_path, ".", BRCMF_FW_NAME_LEN);
strlcat(alt_path, fwctx->req->board_type, BRCMF_FW_NAME_LEN);
strlcat(alt_path, ".txt", BRCMF_FW_NAME_LEN);
alt_path = brcm_alt_fw_path(cur->path, fwctx->req->board_type);
if (!alt_path)
goto fallback;
ret = request_firmware(fw, alt_path, fwctx->dev);
kfree(alt_path);
if (ret == 0)
return ret;
}
fallback:
return request_firmware(fw, cur->path, fwctx->dev);
}
......@@ -639,6 +656,22 @@ static void brcmf_fw_request_done(const struct firmware *fw, void *ctx)
kfree(fwctx);
}
static void brcmf_fw_request_done_alt_path(const struct firmware *fw, void *ctx)
{
struct brcmf_fw *fwctx = ctx;
struct brcmf_fw_item *first = &fwctx->req->items[0];
int ret = 0;
/* Fall back to canonical path if board firmware not found */
if (!fw)
ret = request_firmware_nowait(THIS_MODULE, true, first->path,
fwctx->dev, GFP_KERNEL, fwctx,
brcmf_fw_request_done);
if (fw || ret < 0)
brcmf_fw_request_done(fw, ctx);
}
static bool brcmf_fw_request_is_valid(struct brcmf_fw_request *req)
{
struct brcmf_fw_item *item;
......@@ -660,6 +693,7 @@ int brcmf_fw_get_firmwares(struct device *dev, struct brcmf_fw_request *req,
{
struct brcmf_fw_item *first = &req->items[0];
struct brcmf_fw *fwctx;
char *alt_path;
int ret;
brcmf_dbg(TRACE, "enter: dev=%s\n", dev_name(dev));
......@@ -677,9 +711,18 @@ int brcmf_fw_get_firmwares(struct device *dev, struct brcmf_fw_request *req,
fwctx->req = req;
fwctx->done = fw_cb;
/* First try alternative board-specific path if any */
alt_path = brcm_alt_fw_path(first->path, fwctx->req->board_type);
if (alt_path) {
ret = request_firmware_nowait(THIS_MODULE, true, alt_path,
fwctx->dev, GFP_KERNEL, fwctx,
brcmf_fw_request_done_alt_path);
kfree(alt_path);
} else {
ret = request_firmware_nowait(THIS_MODULE, true, first->path,
fwctx->dev, GFP_KERNEL, fwctx,
brcmf_fw_request_done);
}
if (ret < 0)
brcmf_fw_request_done(NULL, fwctx);
......
......@@ -15,6 +15,7 @@
#include "bus.h"
#include "debug.h"
#include "tracepoint.h"
#include "xtlv.h"
#include "fwil.h"
#include "proto.h"
......@@ -150,7 +151,8 @@ brcmf_fil_cmd_data_get(struct brcmf_if *ifp, u32 cmd, void *data, u32 len)
mutex_lock(&ifp->drvr->proto_block);
err = brcmf_fil_cmd_data(ifp, cmd, data, len, false);
brcmf_dbg(FIL, "ifidx=%d, cmd=%d, len=%d\n", ifp->ifidx, cmd, len);
brcmf_dbg(FIL, "ifidx=%d, cmd=%d, len=%d, err=%d\n", ifp->ifidx, cmd,
len, err);
brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
......@@ -260,7 +262,8 @@ brcmf_fil_iovar_data_get(struct brcmf_if *ifp, char *name, void *data,
bphy_err(drvr, "Creating iovar failed\n");
}
brcmf_dbg(FIL, "ifidx=%d, name=%s, len=%d\n", ifp->ifidx, name, len);
brcmf_dbg(FIL, "ifidx=%d, name=%s, len=%d, err=%d\n", ifp->ifidx, name,
len, err);
brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
......@@ -383,14 +386,13 @@ brcmf_fil_bsscfg_data_get(struct brcmf_if *ifp, char *name,
err = -EPERM;
bphy_err(drvr, "Creating bsscfg failed\n");
}
brcmf_dbg(FIL, "ifidx=%d, bsscfgidx=%d, name=%s, len=%d\n", ifp->ifidx,
ifp->bsscfgidx, name, len);
brcmf_dbg(FIL, "ifidx=%d, bsscfgidx=%d, name=%s, len=%d, err=%d\n",
ifp->ifidx, ifp->bsscfgidx, name, len, err);
brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
mutex_unlock(&drvr->proto_block);
return err;
}
s32
......@@ -414,3 +416,117 @@ brcmf_fil_bsscfg_int_get(struct brcmf_if *ifp, char *name, u32 *data)
*data = le32_to_cpu(data_le);
return err;
}
static u32 brcmf_create_xtlv(char *name, u16 id, char *data, u32 len,
char *buf, u32 buflen)
{
u32 iolen;
u32 nmlen;
nmlen = strlen(name) + 1;
iolen = nmlen + brcmf_xtlv_data_size(len, BRCMF_XTLV_OPTION_ALIGN32);
if (iolen > buflen) {
brcmf_err("buffer is too short\n");
return 0;
}
memcpy(buf, name, nmlen);
brcmf_xtlv_pack_header((void *)(buf + nmlen), id, len, data,
BRCMF_XTLV_OPTION_ALIGN32);
return iolen;
}
s32 brcmf_fil_xtlv_data_set(struct brcmf_if *ifp, char *name, u16 id,
void *data, u32 len)
{
struct brcmf_pub *drvr = ifp->drvr;
s32 err;
u32 buflen;
mutex_lock(&drvr->proto_block);
brcmf_dbg(FIL, "ifidx=%d, name=%s, id=%u, len=%u\n", ifp->ifidx, name,
id, len);
brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
buflen = brcmf_create_xtlv(name, id, data, len,
drvr->proto_buf, sizeof(drvr->proto_buf));
if (buflen) {
err = brcmf_fil_cmd_data(ifp, BRCMF_C_SET_VAR, drvr->proto_buf,
buflen, true);
} else {
err = -EPERM;
bphy_err(drvr, "Creating xtlv failed\n");
}
mutex_unlock(&drvr->proto_block);
return err;
}
s32 brcmf_fil_xtlv_data_get(struct brcmf_if *ifp, char *name, u16 id,
void *data, u32 len)
{
struct brcmf_pub *drvr = ifp->drvr;
s32 err;
u32 buflen;
mutex_lock(&drvr->proto_block);
buflen = brcmf_create_xtlv(name, id, data, len,
drvr->proto_buf, sizeof(drvr->proto_buf));
if (buflen) {
err = brcmf_fil_cmd_data(ifp, BRCMF_C_GET_VAR, drvr->proto_buf,
buflen, false);
if (err == 0)
memcpy(data, drvr->proto_buf, len);
} else {
err = -EPERM;
bphy_err(drvr, "Creating bsscfg failed\n");
}
brcmf_dbg(FIL, "ifidx=%d, name=%s, id=%u, len=%u, err=%d\n",
ifp->ifidx, name, id, len, err);
brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
mutex_unlock(&drvr->proto_block);
return err;
}
s32 brcmf_fil_xtlv_int_set(struct brcmf_if *ifp, char *name, u16 id, u32 data)
{
__le32 data_le = cpu_to_le32(data);
return brcmf_fil_xtlv_data_set(ifp, name, id, &data_le,
sizeof(data_le));
}
s32 brcmf_fil_xtlv_int_get(struct brcmf_if *ifp, char *name, u16 id, u32 *data)
{
__le32 data_le = cpu_to_le32(*data);
s32 err;
err = brcmf_fil_xtlv_data_get(ifp, name, id, &data_le, sizeof(data_le));
if (err == 0)
*data = le32_to_cpu(data_le);
return err;
}
s32 brcmf_fil_xtlv_int8_get(struct brcmf_if *ifp, char *name, u16 id, u8 *data)
{
return brcmf_fil_xtlv_data_get(ifp, name, id, data, sizeof(*data));
}
s32 brcmf_fil_xtlv_int16_get(struct brcmf_if *ifp, char *name, u16 id, u16 *data)
{
__le16 data_le = cpu_to_le16(*data);
s32 err;
err = brcmf_fil_xtlv_data_get(ifp, name, id, &data_le, sizeof(data_le));
if (err == 0)
*data = le16_to_cpu(data_le);
return err;
}
......@@ -97,5 +97,13 @@ s32 brcmf_fil_bsscfg_data_get(struct brcmf_if *ifp, char *name, void *data,
u32 len);
s32 brcmf_fil_bsscfg_int_set(struct brcmf_if *ifp, char *name, u32 data);
s32 brcmf_fil_bsscfg_int_get(struct brcmf_if *ifp, char *name, u32 *data);
s32 brcmf_fil_xtlv_data_set(struct brcmf_if *ifp, char *name, u16 id,
void *data, u32 len);
s32 brcmf_fil_xtlv_data_get(struct brcmf_if *ifp, char *name, u16 id,
void *data, u32 len);
s32 brcmf_fil_xtlv_int_set(struct brcmf_if *ifp, char *name, u16 id, u32 data);
s32 brcmf_fil_xtlv_int_get(struct brcmf_if *ifp, char *name, u16 id, u32 *data);
s32 brcmf_fil_xtlv_int8_get(struct brcmf_if *ifp, char *name, u16 id, u8 *data);
s32 brcmf_fil_xtlv_int16_get(struct brcmf_if *ifp, char *name, u16 id, u16 *data);
#endif /* _fwil_h_ */
......@@ -1886,7 +1886,8 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
devinfo->pdev = pdev;
pcie_bus_dev = NULL;
devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
devinfo->ci = brcmf_chip_attach(devinfo, pdev->device,
&brcmf_pcie_buscore_ops);
if (IS_ERR(devinfo->ci)) {
ret = PTR_ERR(devinfo->ci);
devinfo->ci = NULL;
......
......@@ -617,6 +617,7 @@ BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
/* Note the names are not postfixed with a1 for backward compatibility */
BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio");
BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio");
BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio");
BRCMF_FW_DEF(43456, "brcmfmac43456-sdio");
BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio");
......@@ -624,11 +625,15 @@ BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio");
BRCMF_FW_DEF(4359, "brcmfmac4359-sdio");
BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio");
BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio");
BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-sdio");
/* firmware config files */
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt");
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
/* per-board firmware binaries */
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin");
static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
......@@ -643,14 +648,16 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1),
BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1),
BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0),
BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456),
BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455),
BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012)
BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012),
BRCMF_FW_ENTRY(CY_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752)
};
#define TXCTL_CREDITS 2
......@@ -3416,7 +3423,8 @@ static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus)
{
if (bus->ci->chip == CY_CC_43012_CHIP_ID)
if (bus->ci->chip == CY_CC_43012_CHIP_ID ||
bus->ci->chip == CY_CC_43752_CHIP_ID)
return true;
else
return false;
......@@ -3907,7 +3915,7 @@ static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
* It can be identified as 4339 by looking at the chip revision. It
* is corrected here so the chip.c module has the right info.
*/
if (addr == CORE_CC_REG(SI_ENUM_BASE, chipid) &&
if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) &&
(sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 ||
sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) {
rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
......@@ -3943,12 +3951,15 @@ brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
int reg_addr;
u32 reg_val;
u32 drivestrength;
u32 enum_base;
sdiodev = bus->sdiodev;
sdio_claim_host(sdiodev->func1);
pr_debug("F1 signature read @0x18000000=0x%4x\n",
brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL));
enum_base = brcmf_chip_enum_base(sdiodev->func1->device);
pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base,
brcmf_sdiod_readl(sdiodev, enum_base, NULL));
/*
* Force PLL off until brcmf_chip_attach()
......@@ -3967,7 +3978,8 @@ brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
goto fail;
}
bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device,
&brcmf_sdio_buscore_ops);
if (IS_ERR(bus->ci)) {
brcmf_err("brcmf_chip_attach failed!\n");
bus->ci = NULL;
......@@ -4257,6 +4269,7 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err,
switch (sdiod->func1->device) {
case SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373:
case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43752:
brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
CY_4373_F2_WATERMARK);
brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
......@@ -4442,7 +4455,7 @@ struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
bus->tx_seq = SDPCM_SEQ_WRAP - 1;
/* single-threaded workqueue */
wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM | WQ_HIGHPRI,
dev_name(&sdiodev->func1->dev));
if (!wq) {
brcmf_err("insufficient memory to create txworkqueue\n");
......@@ -4616,4 +4629,3 @@ int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
return ret;
}
// SPDX-License-Identifier: ISC
/*
* Copyright (c) 2019 Broadcom
*/
#include <asm/unaligned.h>
#include <linux/string.h>
#include <linux/bug.h>
#include "xtlv.h"
static int brcmf_xtlv_header_size(u16 opts)
{
int len = (int)offsetof(struct brcmf_xtlv, data);
if (opts & BRCMF_XTLV_OPTION_IDU8)
--len;
if (opts & BRCMF_XTLV_OPTION_LENU8)
--len;
return len;
}
int brcmf_xtlv_data_size(int dlen, u16 opts)
{
int hsz;
hsz = brcmf_xtlv_header_size(opts);
if (opts & BRCMF_XTLV_OPTION_ALIGN32)
return roundup(dlen + hsz, 4);
return dlen + hsz;
}
void brcmf_xtlv_pack_header(struct brcmf_xtlv *xtlv, u16 id, u16 len,
const u8 *data, u16 opts)
{
u8 *data_buf;
u16 mask = BRCMF_XTLV_OPTION_IDU8 | BRCMF_XTLV_OPTION_LENU8;
if (!(opts & mask)) {
u8 *idp = (u8 *)xtlv;
u8 *lenp = idp + sizeof(xtlv->id);
put_unaligned_le16(id, idp);
put_unaligned_le16(len, lenp);
data_buf = lenp + sizeof(u16);
} else if ((opts & mask) == mask) { /* u8 id and u8 len */
u8 *idp = (u8 *)xtlv;
u8 *lenp = idp + 1;
*idp = (u8)id;
*lenp = (u8)len;
data_buf = lenp + sizeof(u8);
} else if (opts & BRCMF_XTLV_OPTION_IDU8) { /* u8 id, u16 len */
u8 *idp = (u8 *)xtlv;
u8 *lenp = idp + 1;
*idp = (u8)id;
put_unaligned_le16(len, lenp);
data_buf = lenp + sizeof(u16);
} else if (opts & BRCMF_XTLV_OPTION_LENU8) { /* u16 id, u8 len */
u8 *idp = (u8 *)xtlv;
u8 *lenp = idp + sizeof(u16);
put_unaligned_le16(id, idp);
*lenp = (u8)len;
data_buf = lenp + sizeof(u8);
} else {
WARN(true, "Unexpected xtlv option");
return;
}
if (opts & BRCMF_XTLV_OPTION_LENU8) {
WARN_ON(len > 0x00ff);
len &= 0xff;
}
if (data)
memcpy(data_buf, data, len);
}
// SPDX-License-Identifier: ISC
/*
* Copyright (c) 2019 Broadcom
*/
#ifndef __BRCMF_XTLV_H
#define __BRCMF_XTLV_H
#include <linux/types.h>
#include <linux/bits.h>
/* bcm type(id), length, value with w/16 bit id/len. The structure below
* is nominal, and is used to support variable length id and type. See
* xtlv options below.
*/
struct brcmf_xtlv {
u16 id;
u16 len;
u8 data[0];
};
enum brcmf_xtlv_option {
BRCMF_XTLV_OPTION_ALIGN32 = BIT(0),
BRCMF_XTLV_OPTION_IDU8 = BIT(1),
BRCMF_XTLV_OPTION_LENU8 = BIT(2),
};
int brcmf_xtlv_data_size(int dlen, u16 opts);
void brcmf_xtlv_pack_header(struct brcmf_xtlv *xtlv, u16 id, u16 len,
const u8 *data, u16 opts);
#endif /* __BRCMF_XTLV_H */
......@@ -704,7 +704,7 @@ static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
{
u8 idx;
u16 addr[] = {
static const u16 addr[] = {
M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
M_HOST_FLAGS5
};
......
......@@ -52,6 +52,7 @@
#define BRCM_CC_4371_CHIP_ID 0x4371
#define CY_CC_4373_CHIP_ID 0x4373
#define CY_CC_43012_CHIP_ID 43012
#define CY_CC_43752_CHIP_ID 43752
/* USB Device IDs */
#define BRCM_USB_43143_DEVICE_ID 0xbd1e
......
......@@ -6,7 +6,7 @@
#ifndef _BRCM_SOC_H
#define _BRCM_SOC_H
#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
#define SI_ENUM_BASE_DEFAULT 0x18000000
/* Common core control flags */
#define SICF_BIST_EN 0x8000
......
......@@ -927,7 +927,8 @@ static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
static int libipw_verify_qos_info(struct libipw_qos_information_element
*info_element, int sub_type)
{
if (info_element->elementID != QOS_ELEMENT_ID)
return -1;
if (info_element->qui_subtype != sub_type)
return -1;
if (memcmp(info_element->qui, qos_oui, QOS_OUI_LEN))
......@@ -943,57 +944,34 @@ static int libipw_verify_qos_info(struct libipw_qos_information_element
/*
* Parse a QoS parameter element
*/
static int libipw_read_qos_param_element(struct libipw_qos_parameter_info
*element_param, struct libipw_info_element
*info_element)
static int libipw_read_qos_param_element(
struct libipw_qos_parameter_info *element_param,
struct libipw_info_element *info_element)
{
int ret = 0;
u16 size = sizeof(struct libipw_qos_parameter_info) - 2;
size_t size = sizeof(*element_param);
if ((info_element == NULL) || (element_param == NULL))
if (!element_param || !info_element || info_element->len != size - 2)
return -1;
if (info_element->id == QOS_ELEMENT_ID && info_element->len == size) {
memcpy(element_param->info_element.qui, info_element->data,
info_element->len);
element_param->info_element.elementID = info_element->id;
element_param->info_element.length = info_element->len;
} else
ret = -1;
if (ret == 0)
ret = libipw_verify_qos_info(&element_param->info_element,
memcpy(element_param, info_element, size);
return libipw_verify_qos_info(&element_param->info_element,
QOS_OUI_PARAM_SUB_TYPE);
return ret;
}
/*
* Parse a QoS information element
*/
static int libipw_read_qos_info_element(struct
libipw_qos_information_element
*element_info, struct libipw_info_element
*info_element)
static int libipw_read_qos_info_element(
struct libipw_qos_information_element *element_info,
struct libipw_info_element *info_element)
{
int ret = 0;
u16 size = sizeof(struct libipw_qos_information_element) - 2;
size_t size = sizeof(struct libipw_qos_information_element) - 2;
if (element_info == NULL)
if (!element_info || !info_element || info_element->len != size - 2)
return -1;
if (info_element == NULL)
return -1;
if ((info_element->id == QOS_ELEMENT_ID) && (info_element->len == size)) {
memcpy(element_info->qui, info_element->data,
info_element->len);
element_info->elementID = info_element->id;
element_info->length = info_element->len;
} else
ret = -1;
if (ret == 0)
ret = libipw_verify_qos_info(element_info,
QOS_OUI_INFO_SUB_TYPE);
return ret;
memcpy(element_info, info_element, size);
return libipw_verify_qos_info(element_info, QOS_OUI_INFO_SUB_TYPE);
}
/*
......
......@@ -179,8 +179,8 @@ static struct libipw_txb *libipw_alloc_txb(int nr_frags, int txb_size,
{
struct libipw_txb *txb;
int i;
txb = kmalloc(sizeof(struct libipw_txb) + (sizeof(u8 *) * nr_frags),
gfp_mask);
txb = kmalloc(struct_size(txb, fragments, nr_frags), gfp_mask);
if (!txb)
return NULL;
......
......@@ -16,24 +16,4 @@ source "drivers/net/wireless/intersil/hostap/Kconfig"
source "drivers/net/wireless/intersil/orinoco/Kconfig"
source "drivers/net/wireless/intersil/p54/Kconfig"
config PRISM54
tristate 'Intersil Prism GT/Duette/Indigo PCI/Cardbus (DEPRECATED)'
depends on PCI
select WIRELESS_EXT
select WEXT_SPY
select WEXT_PRIV
select FW_LOADER
help
This enables support for FullMAC PCI/Cardbus prism54 devices. This
driver is now deprecated in favor for the SoftMAC driver, p54pci.
p54pci supports FullMAC PCI/Cardbus devices as well.
For more information refer to the p54 wiki:
http://wireless.wiki.kernel.org/en/users/Drivers/p54
Note: You need a motherboard with DMA support to use any of these cards
When built as module you get the module prism54
endif # WLAN_VENDOR_INTERSIL
......@@ -2,4 +2,3 @@
obj-$(CONFIG_HOSTAP) += hostap/
obj-$(CONFIG_HERMES) += orinoco/
obj-$(CONFIG_P54_COMMON) += p54/
obj-$(CONFIG_PRISM54) += prism54/
# SPDX-License-Identifier: GPL-2.0-only
# $Id: Makefile.k26,v 1.7 2004/01/30 16:24:00 ajfa Exp $
prism54-objs := islpci_eth.o islpci_mgt.o \
isl_38xx.o isl_ioctl.o islpci_dev.o \
islpci_hotplug.o oid_mgt.o
obj-$(CONFIG_PRISM54) += prism54.o
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2002 Intersil Americas Inc.
* Copyright (C) 2003-2004 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>_
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/ktime.h>
#include <linux/uaccess.h>
#include <asm/io.h>
#include "prismcompat.h"
#include "isl_38xx.h"
#include "islpci_dev.h"
#include "islpci_mgt.h"
/******************************************************************************
Device Interface & Control functions
******************************************************************************/
/**
* isl38xx_disable_interrupts - disable all interrupts
* @device: pci memory base address
*
* Instructs the device to disable all interrupt reporting by asserting
* the IRQ line. New events may still show up in the interrupt identification
* register located at offset %ISL38XX_INT_IDENT_REG.
*/
void
isl38xx_disable_interrupts(void __iomem *device)
{
isl38xx_w32_flush(device, 0x00000000, ISL38XX_INT_EN_REG);
udelay(ISL38XX_WRITEIO_DELAY);
}
void
isl38xx_handle_sleep_request(isl38xx_control_block *control_block,
int *powerstate, void __iomem *device_base)
{
/* device requests to go into sleep mode
* check whether the transmit queues for data and management are empty */
if (isl38xx_in_queue(control_block, ISL38XX_CB_TX_DATA_LQ))
/* data tx queue not empty */
return;
if (isl38xx_in_queue(control_block, ISL38XX_CB_TX_MGMTQ))
/* management tx queue not empty */
return;
/* check also whether received frames are pending */
if (isl38xx_in_queue(control_block, ISL38XX_CB_RX_DATA_LQ))
/* data rx queue not empty */
return;
if (isl38xx_in_queue(control_block, ISL38XX_CB_RX_MGMTQ))
/* management rx queue not empty */
return;
#if VERBOSE > SHOW_ERROR_MESSAGES
DEBUG(SHOW_TRACING, "Device going to sleep mode\n");
#endif
/* all queues are empty, allow the device to go into sleep mode */
*powerstate = ISL38XX_PSM_POWERSAVE_STATE;
/* assert the Sleep interrupt in the Device Interrupt Register */
isl38xx_w32_flush(device_base, ISL38XX_DEV_INT_SLEEP,
ISL38XX_DEV_INT_REG);
udelay(ISL38XX_WRITEIO_DELAY);
}
void
isl38xx_handle_wakeup(isl38xx_control_block *control_block,
int *powerstate, void __iomem *device_base)
{
/* device is in active state, update the powerstate flag */
*powerstate = ISL38XX_PSM_ACTIVE_STATE;
/* now check whether there are frames pending for the card */
if (!isl38xx_in_queue(control_block, ISL38XX_CB_TX_DATA_LQ)
&& !isl38xx_in_queue(control_block, ISL38XX_CB_TX_MGMTQ))
return;
#if VERBOSE > SHOW_ERROR_MESSAGES
DEBUG(SHOW_ANYTHING, "Wake up handler trigger the device\n");
#endif
/* either data or management transmit queue has a frame pending
* trigger the device by setting the Update bit in the Device Int reg */
isl38xx_w32_flush(device_base, ISL38XX_DEV_INT_UPDATE,
ISL38XX_DEV_INT_REG);
udelay(ISL38XX_WRITEIO_DELAY);
}
void
isl38xx_trigger_device(int asleep, void __iomem *device_base)
{
u32 reg;
#if VERBOSE > SHOW_ERROR_MESSAGES
u32 counter = 0;
struct timespec64 current_ts64;
DEBUG(SHOW_FUNCTION_CALLS, "isl38xx trigger device\n");
#endif
/* check whether the device is in power save mode */
if (asleep) {
/* device is in powersave, trigger the device for wakeup */
#if VERBOSE > SHOW_ERROR_MESSAGES
ktime_get_real_ts64(&current_ts64);
DEBUG(SHOW_TRACING, "%lld.%09ld Device wakeup triggered\n",
(s64)current_ts64.tv_sec, current_ts64.tv_nsec);
DEBUG(SHOW_TRACING, "%lld.%09ld Device register read %08x\n",
(s64)current_ts64.tv_sec, current_ts64.tv_nsec,
readl(device_base + ISL38XX_CTRL_STAT_REG));
#endif
reg = readl(device_base + ISL38XX_INT_IDENT_REG);
if (reg == 0xabadface) {
#if VERBOSE > SHOW_ERROR_MESSAGES
ktime_get_real_ts64(&current_ts64);
DEBUG(SHOW_TRACING,
"%lld.%09ld Device register abadface\n",
(s64)current_ts64.tv_sec, current_ts64.tv_nsec);
#endif
/* read the Device Status Register until Sleepmode bit is set */
while (reg = readl(device_base + ISL38XX_CTRL_STAT_REG),
(reg & ISL38XX_CTRL_STAT_SLEEPMODE) == 0) {
udelay(ISL38XX_WRITEIO_DELAY);
#if VERBOSE > SHOW_ERROR_MESSAGES
counter++;
#endif
}
#if VERBOSE > SHOW_ERROR_MESSAGES
DEBUG(SHOW_TRACING,
"%lld.%09ld Device register read %08x\n",
(s64)current_ts64.tv_sec, current_ts64.tv_nsec,
readl(device_base + ISL38XX_CTRL_STAT_REG));
ktime_get_real_ts64(&current_ts64);
DEBUG(SHOW_TRACING,
"%lld.%09ld Device asleep counter %i\n",
(s64)current_ts64.tv_sec, current_ts64.tv_nsec,
counter);
#endif
}
/* assert the Wakeup interrupt in the Device Interrupt Register */
isl38xx_w32_flush(device_base, ISL38XX_DEV_INT_WAKEUP,
ISL38XX_DEV_INT_REG);
#if VERBOSE > SHOW_ERROR_MESSAGES
udelay(ISL38XX_WRITEIO_DELAY);
/* perform another read on the Device Status Register */
reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
ktime_get_real_ts64(&current_ts64);
DEBUG(SHOW_TRACING, "%lld.%00ld Device register read %08x\n",
(s64)current_ts64.tv_sec, current_ts64.tv_nsec, reg);
#endif
} else {
/* device is (still) awake */
#if VERBOSE > SHOW_ERROR_MESSAGES
DEBUG(SHOW_TRACING, "Device is in active state\n");
#endif
/* trigger the device by setting the Update bit in the Device Int reg */
isl38xx_w32_flush(device_base, ISL38XX_DEV_INT_UPDATE,
ISL38XX_DEV_INT_REG);
}
}
void
isl38xx_interface_reset(void __iomem *device_base, dma_addr_t host_address)
{
#if VERBOSE > SHOW_ERROR_MESSAGES
DEBUG(SHOW_FUNCTION_CALLS, "isl38xx_interface_reset\n");
#endif
/* load the address of the control block in the device */
isl38xx_w32_flush(device_base, host_address, ISL38XX_CTRL_BLK_BASE_REG);
udelay(ISL38XX_WRITEIO_DELAY);
/* set the reset bit in the Device Interrupt Register */
isl38xx_w32_flush(device_base, ISL38XX_DEV_INT_RESET, ISL38XX_DEV_INT_REG);
udelay(ISL38XX_WRITEIO_DELAY);
/* enable the interrupt for detecting initialization */
/* Note: Do not enable other interrupts here. We want the
* device to have come up first 100% before allowing any other
* interrupts. */
isl38xx_w32_flush(device_base, ISL38XX_INT_IDENT_INIT, ISL38XX_INT_EN_REG);
udelay(ISL38XX_WRITEIO_DELAY); /* allow complete full reset */
}
void
isl38xx_enable_common_interrupts(void __iomem *device_base)
{
u32 reg;
reg = ISL38XX_INT_IDENT_UPDATE | ISL38XX_INT_IDENT_SLEEP |
ISL38XX_INT_IDENT_WAKEUP;
isl38xx_w32_flush(device_base, reg, ISL38XX_INT_EN_REG);
udelay(ISL38XX_WRITEIO_DELAY);
}
int
isl38xx_in_queue(isl38xx_control_block *cb, int queue)
{
const s32 delta = (le32_to_cpu(cb->driver_curr_frag[queue]) -
le32_to_cpu(cb->device_curr_frag[queue]));
/* determine the amount of fragments in the queue depending on the type
* of the queue, either transmit or receive */
BUG_ON(delta < 0); /* driver ptr must be ahead of device ptr */
switch (queue) {
/* send queues */
case ISL38XX_CB_TX_MGMTQ:
BUG_ON(delta > ISL38XX_CB_MGMT_QSIZE);
fallthrough;
case ISL38XX_CB_TX_DATA_LQ:
case ISL38XX_CB_TX_DATA_HQ:
BUG_ON(delta > ISL38XX_CB_TX_QSIZE);
return delta;
/* receive queues */
case ISL38XX_CB_RX_MGMTQ:
BUG_ON(delta > ISL38XX_CB_MGMT_QSIZE);
return ISL38XX_CB_MGMT_QSIZE - delta;
case ISL38XX_CB_RX_DATA_LQ:
case ISL38XX_CB_RX_DATA_HQ:
BUG_ON(delta > ISL38XX_CB_RX_QSIZE);
return ISL38XX_CB_RX_QSIZE - delta;
}
BUG();
return 0;
}
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2002 Intersil Americas Inc.
*/
#ifndef _ISL_38XX_H
#define _ISL_38XX_H
#include <asm/io.h>
#include <asm/byteorder.h>
#define ISL38XX_CB_RX_QSIZE 8
#define ISL38XX_CB_TX_QSIZE 32
/* ISL38XX Access Point Specific definitions */
#define ISL38XX_MAX_WDS_LINKS 8
/* ISL38xx Client Specific definitions */
#define ISL38XX_PSM_ACTIVE_STATE 0
#define ISL38XX_PSM_POWERSAVE_STATE 1
/* ISL38XX Host Interface Definitions */
#define ISL38XX_PCI_MEM_SIZE 0x02000
#define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
#define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
#define ISL38XX_WRITEIO_DELAY 10 /* in us */
#define ISL38XX_RESET_DELAY 50 /* in ms */
#define ISL38XX_WAIT_CYCLE 10 /* in 10ms */
#define ISL38XX_MAX_WAIT_CYCLES 10
/* PCI Memory Area */
#define ISL38XX_HARDWARE_REG 0x0000
#define ISL38XX_CARDBUS_CIS 0x0800
#define ISL38XX_DIRECT_MEM_WIN 0x1000
/* Hardware registers */
#define ISL38XX_DEV_INT_REG 0x0000
#define ISL38XX_INT_IDENT_REG 0x0010
#define ISL38XX_INT_ACK_REG 0x0014
#define ISL38XX_INT_EN_REG 0x0018
#define ISL38XX_GEN_PURP_COM_REG_1 0x0020
#define ISL38XX_GEN_PURP_COM_REG_2 0x0024
#define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1
#define ISL38XX_DIR_MEM_BASE_REG 0x0030
#define ISL38XX_CTRL_STAT_REG 0x0078
/* High end mobos queue up pci writes, the following
* is used to "read" from after a write to force flush */
#define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG
/**
* isl38xx_w32_flush - PCI iomem write helper
* @base: (host) memory base address of the device
* @val: 32bit value (host order) to write
* @offset: byte offset into @base to write value to
*
* This helper takes care of writing a 32bit datum to the
* specified offset into the device's pci memory space, and making sure
* the pci memory buffers get flushed by performing one harmless read
* from the %ISL38XX_PCI_POSTING_FLUSH offset.
*/
static inline void
isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset)
{
writel(val, base + offset);
(void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
}
/* Device Interrupt register bits */
#define ISL38XX_DEV_INT_RESET 0x0001
#define ISL38XX_DEV_INT_UPDATE 0x0002
#define ISL38XX_DEV_INT_WAKEUP 0x0008
#define ISL38XX_DEV_INT_SLEEP 0x0010
/* Interrupt Identification/Acknowledge/Enable register bits */
#define ISL38XX_INT_IDENT_UPDATE 0x0002
#define ISL38XX_INT_IDENT_INIT 0x0004
#define ISL38XX_INT_IDENT_WAKEUP 0x0008
#define ISL38XX_INT_IDENT_SLEEP 0x0010
#define ISL38XX_INT_SOURCES 0x001E
/* Control/Status register bits */
/* Looks like there are other meaningful bits
0x20004400 seen in normal operation,
0x200044db at 'timeout waiting for mgmt response'
*/
#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
#define ISL38XX_CTRL_STAT_RESET 0x10000000
#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
/* Control Block definitions */
#define ISL38XX_CB_RX_DATA_LQ 0
#define ISL38XX_CB_TX_DATA_LQ 1
#define ISL38XX_CB_RX_DATA_HQ 2
#define ISL38XX_CB_TX_DATA_HQ 3
#define ISL38XX_CB_RX_MGMTQ 4
#define ISL38XX_CB_TX_MGMTQ 5
#define ISL38XX_CB_QCOUNT 6
#define ISL38XX_CB_MGMT_QSIZE 4
#define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */
/* Memory Manager definitions */
#define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */
#define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */
#define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */
#define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
#define CONTROL_BLOCK_SIZE 1024 /* should be enough */
#define PSM_FRAME_SIZE 1536
#define PSM_MINIMAL_STATION_COUNT 64
#define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT
#define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT
#define MAX_TRAP_RX_QUEUE 4
#define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
/* Fragment package definitions */
#define FRAGMENT_FLAG_MF 0x0001
#define MAX_FRAGMENT_SIZE 1536
/* In monitor mode frames have a header. I don't know exactly how big those
* frame can be but I've never seen any frame bigger than 1584... :
*/
#define MAX_FRAGMENT_SIZE_RX 1600
typedef struct {
__le32 address; /* physical address on host */
__le16 size; /* packet size */
__le16 flags; /* set of bit-wise flags */
} isl38xx_fragment;
struct isl38xx_cb {
__le32 driver_curr_frag[ISL38XX_CB_QCOUNT];
__le32 device_curr_frag[ISL38XX_CB_QCOUNT];
isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
};
typedef struct isl38xx_cb isl38xx_control_block;
/* determine number of entries currently in queue */
int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
void isl38xx_disable_interrupts(void __iomem *);
void isl38xx_enable_common_interrupts(void __iomem *);
void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
void __iomem *);
void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *);
void isl38xx_trigger_device(int, void __iomem *);
void isl38xx_interface_reset(void __iomem *, dma_addr_t);
#endif /* _ISL_38XX_H */
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2002 Intersil Americas Inc.
* (C) 2003 Aurelien Alleaume <slts@free.fr>
* (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
*/
#ifndef _ISL_IOCTL_H
#define _ISL_IOCTL_H
#include "islpci_mgt.h"
#include "islpci_dev.h"
#include <net/iw_handler.h> /* New driver API */
#define SUPPORTED_WIRELESS_EXT 19
void prism54_mib_init(islpci_private *);
struct iw_statistics *prism54_get_wireless_stats(struct net_device *);
void prism54_update_stats(struct work_struct *);
void prism54_acl_init(struct islpci_acl *);
void prism54_acl_clean(struct islpci_acl *);
void prism54_process_trap(struct work_struct *);
void prism54_wpa_bss_ie_init(islpci_private *priv);
void prism54_wpa_bss_ie_clean(islpci_private *priv);
int prism54_set_mac_address(struct net_device *, void *);
extern const struct iw_handler_def prism54_handler_def;
#endif /* _ISL_IOCTL_H */
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2002 Intersil Americas Inc.
* Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
* Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
* Copyright (C) 2003 Aurelien Alleaume <slts@free.fr>
*/
#ifndef _ISLPCI_DEV_H
#define _ISLPCI_DEV_H
#include <linux/irqreturn.h>
#include <linux/netdevice.h>
#include <linux/wireless.h>
#include <net/iw_handler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include "isl_38xx.h"
#include "isl_oid.h"
#include "islpci_mgt.h"
/* some states might not be superflous and may be removed when
design is finalized (hvr) */
typedef enum {
PRV_STATE_OFF = 0, /* this means hw_unavailable is != 0 */
PRV_STATE_PREBOOT, /* we are in a pre-boot state (empty RAM) */
PRV_STATE_BOOT, /* boot state (fw upload, run fw) */
PRV_STATE_POSTBOOT, /* after boot state, need reset now */
PRV_STATE_PREINIT, /* pre-init state */
PRV_STATE_INIT, /* init state (restore MIB backup to device) */
PRV_STATE_READY, /* driver&device are in operational state */
PRV_STATE_SLEEP /* device in sleep mode */
} islpci_state_t;
/* ACL using MAC address */
struct mac_entry {
struct list_head _list;
char addr[ETH_ALEN];
};
struct islpci_acl {
enum { MAC_POLICY_OPEN=0, MAC_POLICY_ACCEPT=1, MAC_POLICY_REJECT=2 } policy;
struct list_head mac_list; /* a list of mac_entry */
int size; /* size of queue */
struct mutex lock; /* accessed in ioctls and trap_work */
};
struct islpci_membuf {
int size; /* size of memory */
void *mem; /* address of memory as seen by CPU */
dma_addr_t pci_addr; /* address of memory as seen by device */
};
#define MAX_BSS_WPA_IE_COUNT 64
#define MAX_WPA_IE_LEN 64
struct islpci_bss_wpa_ie {
struct list_head list;
unsigned long last_update;
u8 bssid[ETH_ALEN];
u8 wpa_ie[MAX_WPA_IE_LEN];
size_t wpa_ie_len;
};
typedef struct {
spinlock_t slock; /* generic spinlock; */
u32 priv_oid;
/* our mib cache */
u32 iw_mode;
struct rw_semaphore mib_sem;
void **mib;
char nickname[IW_ESSID_MAX_SIZE+1];
/* Take care of the wireless stats */
struct work_struct stats_work;
struct mutex stats_lock;
/* remember when we last updated the stats */
unsigned long stats_timestamp;
/* The first is accessed under semaphore locking.
* The second is the clean one we return to iwconfig.
*/
struct iw_statistics local_iwstatistics;
struct iw_statistics iwstatistics;
struct iw_spy_data spy_data; /* iwspy support */
struct iw_public_data wireless_data;
int monitor_type; /* ARPHRD_IEEE80211 or ARPHRD_IEEE80211_PRISM */
struct islpci_acl acl;
/* PCI bus allocation & configuration members */
struct pci_dev *pdev; /* PCI structure information */
char firmware[33];
void __iomem *device_base; /* ioremapped device base address */
/* consistent DMA region */
void *driver_mem_address; /* base DMA address */
dma_addr_t device_host_address; /* base DMA address (bus address) */
dma_addr_t device_psm_buffer; /* host memory for PSM buffering (bus address) */
/* our network_device structure */
struct net_device *ndev;
/* device queue interface members */
struct isl38xx_cb *control_block; /* device control block
(== driver_mem_address!) */
/* Each queue has three indexes:
* free/index_mgmt/data_rx/tx (called index, see below),
* driver_curr_frag, and device_curr_frag (in the control block)
* All indexes are ever-increasing, but interpreted modulo the
* device queue size when used.
* index <= device_curr_frag <= driver_curr_frag at all times
* For rx queues, [index, device_curr_frag) contains fragments
* that the interrupt processing needs to handle (owned by driver).
* [device_curr_frag, driver_curr_frag) is the free space in the
* rx queue, waiting for data (owned by device). The driver
* increments driver_curr_frag to indicate to the device that more
* buffers are available.
* If device_curr_frag == driver_curr_frag, no more rx buffers are
* available, and the rx DMA engine of the device is halted.
* For tx queues, [index, device_curr_frag) contains fragments
* where tx is done; they need to be freed (owned by driver).
* [device_curr_frag, driver_curr_frag) contains the frames
* that are being transferred (owned by device). The driver
* increments driver_curr_frag to indicate that more tx work
* needs to be done.
*/
u32 index_mgmt_rx; /* real index mgmt rx queue */
u32 index_mgmt_tx; /* read index mgmt tx queue */
u32 free_data_rx; /* free pointer data rx queue */
u32 free_data_tx; /* free pointer data tx queue */
u32 data_low_tx_full; /* full detected flag */
/* frame memory buffers for the device queues */
struct islpci_membuf mgmt_tx[ISL38XX_CB_MGMT_QSIZE];
struct islpci_membuf mgmt_rx[ISL38XX_CB_MGMT_QSIZE];
struct sk_buff *data_low_tx[ISL38XX_CB_TX_QSIZE];
struct sk_buff *data_low_rx[ISL38XX_CB_RX_QSIZE];
dma_addr_t pci_map_tx_address[ISL38XX_CB_TX_QSIZE];
dma_addr_t pci_map_rx_address[ISL38XX_CB_RX_QSIZE];
/* wait for a reset interrupt */
wait_queue_head_t reset_done;
/* used by islpci_mgt_transaction */
struct mutex mgmt_lock; /* serialize access to mailbox and wqueue */
struct islpci_mgmtframe *mgmt_received; /* mbox for incoming frame */
wait_queue_head_t mgmt_wqueue; /* waitqueue for mbox */
/* state machine */
islpci_state_t state;
int state_off; /* enumeration of off-state, if 0 then
* we're not in any off-state */
/* WPA stuff */
int wpa; /* WPA mode enabled */
struct list_head bss_wpa_list;
int num_bss_wpa;
struct mutex wpa_lock;
u8 wpa_ie[MAX_WPA_IE_LEN];
size_t wpa_ie_len;
struct work_struct reset_task;
int reset_task_pending;
} islpci_private;
static inline islpci_state_t
islpci_get_state(islpci_private *priv)
{
/* lock */
return priv->state;
/* unlock */
}
islpci_state_t islpci_set_state(islpci_private *priv, islpci_state_t new_state);
#define ISLPCI_TX_TIMEOUT (2*HZ)
irqreturn_t islpci_interrupt(int, void *);
int prism54_post_setup(islpci_private *, int);
int islpci_reset(islpci_private *, int);
static inline void
islpci_trigger(islpci_private *priv)
{
isl38xx_trigger_device(islpci_get_state(priv) == PRV_STATE_SLEEP,
priv->device_base);
}
int islpci_free_memory(islpci_private *);
struct net_device *islpci_setup(struct pci_dev *);
#define DRV_NAME "prism54"
#define DRV_VERSION "1.2"
#endif /* _ISLPCI_DEV_H */
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2003 Aurelien Alleaume <slts@free.fr>
*/
#if !defined(_OID_MGT_H)
#define _OID_MGT_H
#include "isl_oid.h"
#include "islpci_dev.h"
extern struct oid_t isl_oid[];
int mgt_init(islpci_private *);
void mgt_clean(islpci_private *);
/* I don't know where to put these 2 */
extern const int frequency_list_a[];
int channel_of_freq(int);
void mgt_le_to_cpu(int, void *);
int mgt_set_request(islpci_private *, enum oid_num_t, int, void *);
int mgt_set_varlen(islpci_private *, enum oid_num_t, void *, int);
int mgt_get_request(islpci_private *, enum oid_num_t, int, void *,
union oid_res_t *);
int mgt_commit_list(islpci_private *, enum oid_num_t *, int);
void mgt_set(islpci_private *, enum oid_num_t, void *);
void mgt_get(islpci_private *, enum oid_num_t, void *);
int mgt_commit(islpci_private *);
int mgt_mlme_answer(islpci_private *);
enum oid_num_t mgt_oidtonum(u32 oid);
int mgt_response_to_str(enum oid_num_t, union oid_res_t *, char *);
#endif /* !defined(_OID_MGT_H) */
/* EOF */
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