Commit e707eb76 authored by Thomas Gleixner's avatar Thomas Gleixner

Merge branch 'clockevents/4.13' of...

Merge branch 'clockevents/4.13' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clockevent changes from Daniel Lezcano:

 - Factored out moxart, aspeed, cortina drivers into a generic timer fttrm010.
   Take the opportunity to add the delay timer (Linus Walleij)

 - Saved / restored tcb atmel context at suspend/resume (Alexandre Belloni)

 - Added ast2500 compatible string and fixed aspeed2500 initialization (Daniel
   Lezcano)

 - Added clock names property for aspeed (Andrew Jeffery)

 - Renamed clocksource_of to timer_of (Daniel Lezcano)

 - Added a common timer init routine (Daniel Lezcano)
parents 938e7cf2 c4779902
...@@ -7,7 +7,11 @@ Required properties: ...@@ -7,7 +7,11 @@ Required properties:
- compatible : Must be one of - compatible : Must be one of
"faraday,fttmr010" "faraday,fttmr010"
"cortina,gemini-timer" "cortina,gemini-timer", "faraday,fttmr010"
"moxa,moxart-timer", "faraday,fttmr010"
"aspeed,ast2400-timer"
"aspeed,ast2500-timer"
- reg : Should contain registers location and length - reg : Should contain registers location and length
- interrupts : Should contain the three timer interrupts usually with - interrupts : Should contain the three timer interrupts usually with
flags for falling edge flags for falling edge
......
MOXA ART timer
Required properties:
- compatible : Must be one of:
- "moxa,moxart-timer"
- "aspeed,ast2400-timer"
- reg : Should contain registers location and length
- interrupts : Should contain the timer interrupt number
- clocks : Should contain phandle for the clock that drives the counter
Example:
timer: timer@98400000 {
compatible = "moxa,moxart-timer";
reg = <0x98400000 0x42>;
interrupts = <19 1>;
clocks = <&coreclk>;
};
...@@ -470,7 +470,7 @@ void __init setup_arch(char **cmdline_p) ...@@ -470,7 +470,7 @@ void __init setup_arch(char **cmdline_p)
void __init time_init(void) void __init time_init(void)
{ {
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
} }
static int __init customize_machine(void) static int __init customize_machine(void)
......
...@@ -337,7 +337,7 @@ config ARCH_MULTIPLATFORM ...@@ -337,7 +337,7 @@ config ARCH_MULTIPLATFORM
select ARM_HAS_SG_CHAIN select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR select AUTO_ZRELADDR
select CLKSRC_OF select TIMER_OF
select COMMON_CLK select COMMON_CLK
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI select MIGHT_HAVE_PCI
...@@ -351,7 +351,7 @@ config ARM_SINGLE_ARMV7M ...@@ -351,7 +351,7 @@ config ARM_SINGLE_ARMV7M
depends on !MMU depends on !MMU
select ARM_NVIC select ARM_NVIC
select AUTO_ZRELADDR select AUTO_ZRELADDR
select CLKSRC_OF select TIMER_OF
select COMMON_CLK select COMMON_CLK
select CPU_V7M select CPU_V7M
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
...@@ -532,7 +532,7 @@ config ARCH_PXA ...@@ -532,7 +532,7 @@ config ARCH_PXA
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
select CLKSRC_PXA select CLKSRC_PXA
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF select TIMER_OF
select CPU_XSCALE if !CPU_XSC3 select CPU_XSCALE if !CPU_XSC3
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GPIO_PXA select GPIO_PXA
...@@ -571,7 +571,7 @@ config ARCH_SA1100 ...@@ -571,7 +571,7 @@ config ARCH_SA1100
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_PXA select CLKSRC_PXA
select CLKSRC_OF if OF select TIMER_OF if OF
select CPU_FREQ select CPU_FREQ
select CPU_SA1100 select CPU_SA1100
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
...@@ -1357,7 +1357,7 @@ config HAVE_ARM_ARCH_TIMER ...@@ -1357,7 +1357,7 @@ config HAVE_ARM_ARCH_TIMER
config HAVE_ARM_TWD config HAVE_ARM_TWD
bool bool
select CLKSRC_OF if OF select TIMER_OF if OF
help help
This options enables support for the ARM timer and watchdog unit This options enables support for the ARM timer and watchdog unit
......
...@@ -893,6 +893,7 @@ timer: timer@1e782000 { ...@@ -893,6 +893,7 @@ timer: timer@1e782000 {
//interrupts = <16 17 18 35 36 37 38 39>; //interrupts = <16 17 18 35 36 37 38 39>;
interrupts = <16>; interrupts = <16>;
clocks = <&clk_apb>; clocks = <&clk_apb>;
clock-names = "PCLK";
}; };
wdt1: wdt@1e785000 { wdt1: wdt@1e785000 {
......
...@@ -1000,6 +1000,7 @@ timer: timer@1e782000 { ...@@ -1000,6 +1000,7 @@ timer: timer@1e782000 {
//interrupts = <16 17 18 35 36 37 38 39>; //interrupts = <16 17 18 35 36 37 38 39>;
interrupts = <16>; interrupts = <16>;
clocks = <&clk_apb>; clocks = <&clk_apb>;
clock-names = "PCLK";
}; };
......
...@@ -403,7 +403,7 @@ static int __init twd_local_timer_of_register(struct device_node *np) ...@@ -403,7 +403,7 @@ static int __init twd_local_timer_of_register(struct device_node *np)
WARN(err, "twd_local_timer_of_register failed (%d)\n", err); WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
return err; return err;
} }
CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); TIMER_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); TIMER_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
#endif #endif
...@@ -120,6 +120,6 @@ void __init time_init(void) ...@@ -120,6 +120,6 @@ void __init time_init(void)
#ifdef CONFIG_COMMON_CLK #ifdef CONFIG_COMMON_CLK
of_clk_init(NULL); of_clk_init(NULL);
#endif #endif
clocksource_probe(); timer_probe();
} }
} }
...@@ -4,7 +4,7 @@ menuconfig ARCH_ASPEED ...@@ -4,7 +4,7 @@ menuconfig ARCH_ASPEED
select SRAM select SRAM
select WATCHDOG select WATCHDOG
select ASPEED_WATCHDOG select ASPEED_WATCHDOG
select MOXART_TIMER select FTTMR010_TIMER
select MFD_SYSCON select MFD_SYSCON
select PINCTRL select PINCTRL
help help
......
...@@ -150,7 +150,7 @@ config ARCH_BCM2835 ...@@ -150,7 +150,7 @@ config ARCH_BCM2835
select ARM_ERRATA_411920 if ARCH_MULTI_V6 select ARM_ERRATA_411920 if ARCH_MULTI_V6
select ARM_TIMER_SP804 select ARM_TIMER_SP804
select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
select CLKSRC_OF select TIMER_OF
select BCM2835_TIMER select BCM2835_TIMER
select PINCTRL select PINCTRL
select PINCTRL_BCM2835 select PINCTRL_BCM2835
......
...@@ -2,7 +2,7 @@ menuconfig ARCH_CLPS711X ...@@ -2,7 +2,7 @@ menuconfig ARCH_CLPS711X
bool "Cirrus Logic EP721x/EP731x-based" bool "Cirrus Logic EP721x/EP731x-based"
depends on ARCH_MULTI_V4T depends on ARCH_MULTI_V4T
select AUTO_ZRELADDR select AUTO_ZRELADDR
select CLKSRC_OF select TIMER_OF
select CLPS711X_TIMER select CLPS711X_TIMER
select COMMON_CLK select COMMON_CLK
select CPU_ARM720T select CPU_ARM720T
......
...@@ -41,7 +41,7 @@ static void __init mediatek_timer_init(void) ...@@ -41,7 +41,7 @@ static void __init mediatek_timer_init(void)
} }
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
}; };
static const char * const mediatek_board_dt_compat[] = { static const char * const mediatek_board_dt_compat[] = {
......
...@@ -4,7 +4,7 @@ menuconfig ARCH_MOXART ...@@ -4,7 +4,7 @@ menuconfig ARCH_MOXART
select CPU_FA526 select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE select ARM_DMA_MEM_BUFFERABLE
select FARADAY_FTINTC010 select FARADAY_FTINTC010
select MOXART_TIMER select FTTMR010_TIMER
select GPIOLIB select GPIOLIB
select PHYLIB if NETDEVICES select PHYLIB if NETDEVICES
help help
......
...@@ -497,7 +497,7 @@ void __init omap_init_time(void) ...@@ -497,7 +497,7 @@ void __init omap_init_time(void)
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL, false); 2, "timer_sys_ck", NULL, false);
clocksource_probe(); timer_probe();
} }
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
...@@ -506,7 +506,7 @@ void __init omap3_secure_sync32k_timer_init(void) ...@@ -506,7 +506,7 @@ void __init omap3_secure_sync32k_timer_init(void)
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL, false); 2, "timer_sys_ck", NULL, false);
clocksource_probe(); timer_probe();
} }
#endif /* CONFIG_ARCH_OMAP3 */ #endif /* CONFIG_ARCH_OMAP3 */
...@@ -517,7 +517,7 @@ void __init omap3_gptimer_timer_init(void) ...@@ -517,7 +517,7 @@ void __init omap3_gptimer_timer_init(void)
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL, __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon", true); 1, "timer_sys_ck", "ti,timer-alwon", true);
if (of_have_populated_dt()) if (of_have_populated_dt())
clocksource_probe(); timer_probe();
} }
#endif #endif
...@@ -532,7 +532,7 @@ static void __init omap4_sync32k_timer_init(void) ...@@ -532,7 +532,7 @@ static void __init omap4_sync32k_timer_init(void)
void __init omap4_local_timer_init(void) void __init omap4_local_timer_init(void)
{ {
omap4_sync32k_timer_init(); omap4_sync32k_timer_init();
clocksource_probe(); timer_probe();
} }
#endif #endif
...@@ -656,7 +656,7 @@ void __init omap5_realtime_timer_init(void) ...@@ -656,7 +656,7 @@ void __init omap5_realtime_timer_init(void)
omap4_sync32k_timer_init(); omap4_sync32k_timer_init();
realtime_counter_init(); realtime_counter_init();
clocksource_probe(); timer_probe();
} }
#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
......
...@@ -55,7 +55,7 @@ static void __init rockchip_timer_init(void) ...@@ -55,7 +55,7 @@ static void __init rockchip_timer_init(void)
} }
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
} }
static void __init rockchip_dt_init(void) static void __init rockchip_dt_init(void)
......
...@@ -394,7 +394,7 @@ config MACH_SMDK2416 ...@@ -394,7 +394,7 @@ config MACH_SMDK2416
config MACH_S3C2416_DT config MACH_S3C2416_DT
bool "Samsung S3C2416 machine using devicetree" bool "Samsung S3C2416 machine using devicetree"
select CLKSRC_OF select TIMER_OF
select USE_OF select USE_OF
select PINCTRL select PINCTRL
select PINCTRL_S3C24XX select PINCTRL_S3C24XX
......
...@@ -336,7 +336,7 @@ config MACH_WLF_CRAGG_6410 ...@@ -336,7 +336,7 @@ config MACH_WLF_CRAGG_6410
config MACH_S3C64XX_DT config MACH_S3C64XX_DT
bool "Samsung S3C6400/S3C6410 machine using Device Tree" bool "Samsung S3C6400/S3C6410 machine using Device Tree"
select CLKSRC_OF select TIMER_OF
select CPU_S3C6400 select CPU_S3C6400
select CPU_S3C6410 select CPU_S3C6410
select PINCTRL select PINCTRL
......
...@@ -113,7 +113,7 @@ void __init rcar_gen2_timer_init(void) ...@@ -113,7 +113,7 @@ void __init rcar_gen2_timer_init(void)
#endif /* CONFIG_ARM_ARCH_TIMER */ #endif /* CONFIG_ARM_ARCH_TIMER */
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
} }
struct memory_reserve_config { struct memory_reserve_config {
......
...@@ -124,5 +124,5 @@ void __init spear13xx_timer_init(void) ...@@ -124,5 +124,5 @@ void __init spear13xx_timer_init(void)
clk_put(pclk); clk_put(pclk);
spear_setup_of_timer(); spear_setup_of_timer();
clocksource_probe(); timer_probe();
} }
...@@ -42,7 +42,7 @@ static void __init sun6i_timer_init(void) ...@@ -42,7 +42,7 @@ static void __init sun6i_timer_init(void)
of_clk_init(NULL); of_clk_init(NULL);
if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
sun6i_reset_init(); sun6i_reset_init();
clocksource_probe(); timer_probe();
} }
DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
......
...@@ -407,7 +407,7 @@ static const char * u300_board_compat[] = { ...@@ -407,7 +407,7 @@ static const char * u300_board_compat[] = {
DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)") DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
.map_io = u300_map_io, .map_io = u300_map_io,
.init_irq = u300_init_irq_dt, .init_irq = u300_init_irq_dt,
.init_time = clocksource_probe, .init_time = timer_probe,
.init_machine = u300_init_machine_dt, .init_machine = u300_init_machine_dt,
.restart = u300_restart, .restart = u300_restart,
.dt_compat = u300_board_compat, .dt_compat = u300_board_compat,
......
...@@ -150,7 +150,7 @@ static void __init zynq_timer_init(void) ...@@ -150,7 +150,7 @@ static void __init zynq_timer_init(void)
{ {
zynq_clock_init(); zynq_clock_init();
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
} }
static struct map_desc zynq_cortex_a9_scu_map __initdata = { static struct map_desc zynq_cortex_a9_scu_map __initdata = {
......
...@@ -18,7 +18,7 @@ config ARCH_ALPINE ...@@ -18,7 +18,7 @@ config ARCH_ALPINE
config ARCH_BCM2835 config ARCH_BCM2835
bool "Broadcom BCM2835 family" bool "Broadcom BCM2835 family"
select CLKSRC_OF select TIMER_OF
select GPIOLIB select GPIOLIB
select PINCTRL select PINCTRL
select PINCTRL_BCM2835 select PINCTRL_BCM2835
...@@ -178,7 +178,7 @@ config ARCH_TEGRA ...@@ -178,7 +178,7 @@ config ARCH_TEGRA
select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_RESET_CONTROLLER
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF select TIMER_OF
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GPIOLIB select GPIOLIB
select PINCTRL select PINCTRL
......
...@@ -70,7 +70,7 @@ void __init time_init(void) ...@@ -70,7 +70,7 @@ void __init time_init(void)
u32 arch_timer_rate; u32 arch_timer_rate;
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
tick_setup_hrtimer_broadcast(); tick_setup_hrtimer_broadcast();
......
...@@ -15,7 +15,7 @@ config H8300 ...@@ -15,7 +15,7 @@ config H8300
select OF_IRQ select OF_IRQ
select OF_EARLY_FLATTREE select OF_EARLY_FLATTREE
select HAVE_MEMBLOCK select HAVE_MEMBLOCK
select CLKSRC_OF select TIMER_OF
select H8300_TMR8 select H8300_TMR8
select HAVE_KERNEL_GZIP select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO select HAVE_KERNEL_LZO
......
...@@ -246,5 +246,5 @@ void __init calibrate_delay(void) ...@@ -246,5 +246,5 @@ void __init calibrate_delay(void)
void __init time_init(void) void __init time_init(void)
{ {
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
} }
...@@ -4,7 +4,7 @@ config MICROBLAZE ...@@ -4,7 +4,7 @@ config MICROBLAZE
select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_WANT_IPC_PARSE_VERSION select ARCH_WANT_IPC_PARSE_VERSION
select BUILDTIME_EXTABLE_SORT select BUILDTIME_EXTABLE_SORT
select CLKSRC_OF select TIMER_OF
select CLONE_BACKWARDS3 select CLONE_BACKWARDS3
select COMMON_CLK select COMMON_CLK
select GENERIC_ATOMIC64 select GENERIC_ATOMIC64
......
...@@ -192,7 +192,7 @@ void __init time_init(void) ...@@ -192,7 +192,7 @@ void __init time_init(void)
{ {
of_clk_init(NULL); of_clk_init(NULL);
setup_cpuinfo_clk(); setup_cpuinfo_clk();
clocksource_probe(); timer_probe();
} }
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
......
...@@ -333,5 +333,5 @@ static int __init xilinx_timer_init(struct device_node *timer) ...@@ -333,5 +333,5 @@ static int __init xilinx_timer_init(struct device_node *timer)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", TIMER_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
xilinx_timer_init); xilinx_timer_init);
...@@ -161,7 +161,7 @@ void __init plat_time_init(void) ...@@ -161,7 +161,7 @@ void __init plat_time_init(void)
} }
} }
clocksource_probe(); timer_probe();
} }
void __init arch_init_irq(void) void __init arch_init_irq(void)
......
...@@ -265,7 +265,7 @@ void __init plat_time_init(void) ...@@ -265,7 +265,7 @@ void __init plat_time_init(void)
(freq%1000000)*100/1000000); (freq%1000000)*100/1000000);
#ifdef CONFIG_CLKSRC_MIPS_GIC #ifdef CONFIG_CLKSRC_MIPS_GIC
update_gic_frequency_dt(); update_gic_frequency_dt();
clocksource_probe(); timer_probe();
#endif #endif
} }
#endif #endif
......
...@@ -64,5 +64,5 @@ void __init plat_time_init(void) ...@@ -64,5 +64,5 @@ void __init plat_time_init(void)
pr_info("CPU Clock: %ldMHz\n", rate / 1000000); pr_info("CPU Clock: %ldMHz\n", rate / 1000000);
mips_hpt_frequency = rate / 2; mips_hpt_frequency = rate / 2;
clocksource_probe(); timer_probe();
} }
...@@ -39,7 +39,7 @@ void __init plat_time_init(void) ...@@ -39,7 +39,7 @@ void __init plat_time_init(void)
struct clk *clk; struct clk *clk;
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
np = of_get_cpu_node(0, NULL); np = of_get_cpu_node(0, NULL);
if (!np) { if (!np) {
......
...@@ -4,7 +4,7 @@ config CLKEVT_RT3352 ...@@ -4,7 +4,7 @@ config CLKEVT_RT3352
bool bool
depends on SOC_RT305X || SOC_MT7620 depends on SOC_RT305X || SOC_MT7620
default y default y
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
config RALINK_ILL_ACC config RALINK_ILL_ACC
......
...@@ -152,4 +152,4 @@ static int __init ralink_systick_init(struct device_node *np) ...@@ -152,4 +152,4 @@ static int __init ralink_systick_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init); TIMER_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
...@@ -82,5 +82,5 @@ void __init plat_time_init(void) ...@@ -82,5 +82,5 @@ void __init plat_time_init(void)
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
mips_hpt_frequency = clk_get_rate(clk) / 2; mips_hpt_frequency = clk_get_rate(clk) / 2;
clk_put(clk); clk_put(clk);
clocksource_probe(); timer_probe();
} }
...@@ -20,5 +20,5 @@ void __init plat_time_init(void) ...@@ -20,5 +20,5 @@ void __init plat_time_init(void)
ralink_of_remap(); ralink_of_remap();
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
} }
...@@ -22,7 +22,7 @@ void __init plat_time_init(void) ...@@ -22,7 +22,7 @@ void __init plat_time_init(void)
struct clk *clk; struct clk *clk;
of_clk_init(NULL); of_clk_init(NULL);
clocksource_probe(); timer_probe();
np = of_get_cpu_node(0, NULL); np = of_get_cpu_node(0, NULL);
if (!np) { if (!np) {
......
config NIOS2 config NIOS2
def_bool y def_bool y
select CLKSRC_OF select TIMER_OF
select GENERIC_ATOMIC64 select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GENERIC_CPU_DEVICES select GENERIC_CPU_DEVICES
......
...@@ -350,7 +350,7 @@ void __init time_init(void) ...@@ -350,7 +350,7 @@ void __init time_init(void)
if (count < 2) if (count < 2)
panic("%d timer is found, it needs 2 timers in system\n", count); panic("%d timer is found, it needs 2 timers in system\n", count);
clocksource_probe(); timer_probe();
} }
CLOCKSOURCE_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init); TIMER_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init);
...@@ -10,7 +10,7 @@ config SH_DEVICE_TREE ...@@ -10,7 +10,7 @@ config SH_DEVICE_TREE
bool "Board Described by Device Tree" bool "Board Described by Device Tree"
select OF select OF
select OF_EARLY_FLATTREE select OF_EARLY_FLATTREE
select CLKSRC_OF select TIMER_OF
select COMMON_CLK select COMMON_CLK
select GENERIC_CALIBRATE_DELAY select GENERIC_CALIBRATE_DELAY
help help
......
...@@ -119,7 +119,7 @@ static void __init sh_of_mem_reserve(void) ...@@ -119,7 +119,7 @@ static void __init sh_of_mem_reserve(void)
static void __init sh_of_time_init(void) static void __init sh_of_time_init(void)
{ {
pr_info("SH generic board support: scanning for clocksource devices\n"); pr_info("SH generic board support: scanning for clocksource devices\n");
clocksource_probe(); timer_probe();
} }
static void __init sh_of_setup(char **cmdline_p) static void __init sh_of_setup(char **cmdline_p)
......
...@@ -187,7 +187,7 @@ void __init time_init(void) ...@@ -187,7 +187,7 @@ void __init time_init(void)
local_timer_setup(0); local_timer_setup(0);
setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction); setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction);
sched_clock_register(ccount_sched_clock_read, 32, ccount_freq); sched_clock_register(ccount_sched_clock_read, 32, ccount_freq);
clocksource_probe(); timer_probe();
} }
/* /*
......
menu "Clock Source drivers" menu "Clock Source drivers"
depends on !ARCH_USES_GETTIMEOFFSET depends on !ARCH_USES_GETTIMEOFFSET
config CLKSRC_OF config TIMER_OF
bool bool
select CLKSRC_PROBE depends on GENERIC_CLOCKEVENTS
select TIMER_PROBE
config CLKEVT_OF
bool
select CLKEVT_PROBE
config CLKSRC_ACPI
bool
select CLKSRC_PROBE
config CLKSRC_PROBE config TIMER_ACPI
bool bool
select TIMER_PROBE
config CLKEVT_PROBE config TIMER_PROBE
bool bool
config CLKSRC_I8253 config CLKSRC_I8253
...@@ -65,14 +59,14 @@ config DW_APB_TIMER ...@@ -65,14 +59,14 @@ config DW_APB_TIMER
config DW_APB_TIMER_OF config DW_APB_TIMER_OF
bool bool
select DW_APB_TIMER select DW_APB_TIMER
select CLKSRC_OF select TIMER_OF
config FTTMR010_TIMER config FTTMR010_TIMER
bool "Faraday Technology timer driver" if COMPILE_TEST bool "Faraday Technology timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
depends on HAS_IOMEM depends on HAS_IOMEM
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF select TIMER_OF
select MFD_SYSCON select MFD_SYSCON
help help
Enables support for the Faraday Technology timer block Enables support for the Faraday Technology timer block
...@@ -81,7 +75,7 @@ config FTTMR010_TIMER ...@@ -81,7 +75,7 @@ config FTTMR010_TIMER
config ROCKCHIP_TIMER config ROCKCHIP_TIMER
bool "Rockchip timer driver" if COMPILE_TEST bool "Rockchip timer driver" if COMPILE_TEST
depends on ARM || ARM64 depends on ARM || ARM64
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
Enables the support for the rockchip timer driver. Enables the support for the rockchip timer driver.
...@@ -89,7 +83,7 @@ config ROCKCHIP_TIMER ...@@ -89,7 +83,7 @@ config ROCKCHIP_TIMER
config ARMADA_370_XP_TIMER config ARMADA_370_XP_TIMER
bool "Armada 370 and XP timer driver" if COMPILE_TEST bool "Armada 370 and XP timer driver" if COMPILE_TEST
depends on ARM depends on ARM
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
Enables the support for the Armada 370 and XP timer driver. Enables the support for the Armada 370 and XP timer driver.
...@@ -104,7 +98,7 @@ config MESON6_TIMER ...@@ -104,7 +98,7 @@ config MESON6_TIMER
config ORION_TIMER config ORION_TIMER
bool "Orion timer driver" if COMPILE_TEST bool "Orion timer driver" if COMPILE_TEST
depends on ARM depends on ARM
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
Enables the support for the Orion timer driver Enables the support for the Orion timer driver
...@@ -148,7 +142,7 @@ config ASM9260_TIMER ...@@ -148,7 +142,7 @@ config ASM9260_TIMER
bool "ASM9260 timer driver" if COMPILE_TEST bool "ASM9260 timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF select TIMER_OF
help help
Enables support for the ASM9260 timer. Enables support for the ASM9260 timer.
...@@ -188,13 +182,6 @@ config ATLAS7_TIMER ...@@ -188,13 +182,6 @@ config ATLAS7_TIMER
help help
Enables support for the Atlas7 timer. Enables support for the Atlas7 timer.
config MOXART_TIMER
bool "Moxart timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
select CLKSRC_MMIO
help
Enables support for the Moxart timer.
config MXS_TIMER config MXS_TIMER
bool "Mxs timer driver" if COMPILE_TEST bool "Mxs timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
...@@ -261,21 +248,21 @@ config CLKSRC_LPC32XX ...@@ -261,21 +248,21 @@ config CLKSRC_LPC32XX
depends on GENERIC_CLOCKEVENTS && HAS_IOMEM depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
depends on ARM depends on ARM
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF select TIMER_OF
help help
Support for the LPC32XX clocksource. Support for the LPC32XX clocksource.
config CLKSRC_PISTACHIO config CLKSRC_PISTACHIO
bool "Clocksource for Pistachio SoC" if COMPILE_TEST bool "Clocksource for Pistachio SoC" if COMPILE_TEST
depends on HAS_IOMEM depends on HAS_IOMEM
select CLKSRC_OF select TIMER_OF
help help
Enables the clocksource for the Pistachio SoC. Enables the clocksource for the Pistachio SoC.
config CLKSRC_TI_32K config CLKSRC_TI_32K
bool "Texas Instruments 32.768 Hz Clocksource" if COMPILE_TEST bool "Texas Instruments 32.768 Hz Clocksource" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK depends on GENERIC_SCHED_CLOCK
select CLKSRC_OF if OF select TIMER_OF if OF
help help
This option enables support for Texas Instruments 32.768 Hz clocksource This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms. available on many OMAP-like platforms.
...@@ -284,7 +271,7 @@ config CLKSRC_NPS ...@@ -284,7 +271,7 @@ config CLKSRC_NPS
bool "NPS400 clocksource driver" if COMPILE_TEST bool "NPS400 clocksource driver" if COMPILE_TEST
depends on !PHYS_ADDR_T_64BIT depends on !PHYS_ADDR_T_64BIT
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF if OF select TIMER_OF if OF
help help
NPS400 clocksource support. NPS400 clocksource support.
Got 64 bit counter with update rate up to 1000MHz. Got 64 bit counter with update rate up to 1000MHz.
...@@ -299,12 +286,12 @@ config CLKSRC_MPS2 ...@@ -299,12 +286,12 @@ config CLKSRC_MPS2
bool "Clocksource for MPS2 SoCs" if COMPILE_TEST bool "Clocksource for MPS2 SoCs" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK depends on GENERIC_SCHED_CLOCK
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF select TIMER_OF
config ARC_TIMERS config ARC_TIMERS
bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
select CLKSRC_OF select TIMER_OF
help help
These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
(ARC700 as well as ARC HS38). (ARC700 as well as ARC HS38).
...@@ -314,7 +301,7 @@ config ARC_TIMERS_64BIT ...@@ -314,7 +301,7 @@ config ARC_TIMERS_64BIT
bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
depends on ARC_TIMERS depends on ARC_TIMERS
select CLKSRC_OF select TIMER_OF
help help
This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP) This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP)
RTC is implemented inside the core, while GFRC sits outside the core in RTC is implemented inside the core, while GFRC sits outside the core in
...@@ -323,8 +310,8 @@ config ARC_TIMERS_64BIT ...@@ -323,8 +310,8 @@ config ARC_TIMERS_64BIT
config ARM_ARCH_TIMER config ARM_ARCH_TIMER
bool bool
select CLKSRC_OF if OF select TIMER_OF if OF
select CLKSRC_ACPI if ACPI select TIMER_ACPI if ACPI
config ARM_ARCH_TIMER_EVTSTREAM config ARM_ARCH_TIMER_EVTSTREAM
bool "Enable ARM architected timer event stream generation by default" bool "Enable ARM architected timer event stream generation by default"
...@@ -381,7 +368,7 @@ config ARM64_ERRATUM_858921 ...@@ -381,7 +368,7 @@ config ARM64_ERRATUM_858921
config ARM_GLOBAL_TIMER config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF select TIMER_OF if OF
depends on ARM depends on ARM
help help
This options enables support for the ARM global timer unit This options enables support for the ARM global timer unit
...@@ -390,7 +377,7 @@ config ARM_TIMER_SP804 ...@@ -390,7 +377,7 @@ config ARM_TIMER_SP804
bool "Support for Dual Timer SP804 module" bool "Support for Dual Timer SP804 module"
depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
select CLKSRC_MMIO select CLKSRC_MMIO
select CLKSRC_OF if OF select TIMER_OF if OF
config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
bool bool
...@@ -401,19 +388,19 @@ config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK ...@@ -401,19 +388,19 @@ config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
config ARMV7M_SYSTICK config ARMV7M_SYSTICK
bool "Support for the ARMv7M system time" if COMPILE_TEST bool "Support for the ARMv7M system time" if COMPILE_TEST
select CLKSRC_OF if OF select TIMER_OF if OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
This options enables support for the ARMv7M system timer unit This options enables support for the ARMv7M system timer unit
config ATMEL_PIT config ATMEL_PIT
select CLKSRC_OF if OF select TIMER_OF if OF
def_bool SOC_AT91SAM9 || SOC_SAMA5 def_bool SOC_AT91SAM9 || SOC_SAMA5
config ATMEL_ST config ATMEL_ST
bool "Atmel ST timer support" if COMPILE_TEST bool "Atmel ST timer support" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
select CLKSRC_OF select TIMER_OF
select MFD_SYSCON select MFD_SYSCON
help help
Support for the Atmel ST timer. Support for the Atmel ST timer.
...@@ -456,7 +443,7 @@ config VF_PIT_TIMER ...@@ -456,7 +443,7 @@ config VF_PIT_TIMER
config OXNAS_RPS_TIMER config OXNAS_RPS_TIMER
bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
This enables support for the Oxford Semiconductor OXNAS RPS timers. This enables support for the Oxford Semiconductor OXNAS RPS timers.
...@@ -467,7 +454,7 @@ config SYS_SUPPORTS_SH_CMT ...@@ -467,7 +454,7 @@ config SYS_SUPPORTS_SH_CMT
config MTK_TIMER config MTK_TIMER
bool "Mediatek timer driver" if COMPILE_TEST bool "Mediatek timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS && HAS_IOMEM depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
Support for Mediatek timer driver. Support for Mediatek timer driver.
...@@ -540,7 +527,7 @@ config EM_TIMER_STI ...@@ -540,7 +527,7 @@ config EM_TIMER_STI
config CLKSRC_QCOM config CLKSRC_QCOM
bool "Qualcomm MSM timer" if COMPILE_TEST bool "Qualcomm MSM timer" if COMPILE_TEST
depends on ARM depends on ARM
select CLKSRC_OF select TIMER_OF
help help
This enables the clocksource and the per CPU clockevent driver for the This enables the clocksource and the per CPU clockevent driver for the
Qualcomm SoCs. Qualcomm SoCs.
...@@ -548,7 +535,7 @@ config CLKSRC_QCOM ...@@ -548,7 +535,7 @@ config CLKSRC_QCOM
config CLKSRC_VERSATILE config CLKSRC_VERSATILE
bool "ARM Versatile (Express) reference platforms clock source" if COMPILE_TEST bool "ARM Versatile (Express) reference platforms clock source" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && !ARCH_USES_GETTIMEOFFSET depends on GENERIC_SCHED_CLOCK && !ARCH_USES_GETTIMEOFFSET
select CLKSRC_OF select TIMER_OF
default y if MFD_VEXPRESS_SYSREG default y if MFD_VEXPRESS_SYSREG
help help
This option enables clock source based on free running This option enables clock source based on free running
...@@ -559,12 +546,12 @@ config CLKSRC_VERSATILE ...@@ -559,12 +546,12 @@ config CLKSRC_VERSATILE
config CLKSRC_MIPS_GIC config CLKSRC_MIPS_GIC
bool bool
depends on MIPS_GIC depends on MIPS_GIC
select CLKSRC_OF select TIMER_OF
config CLKSRC_TANGO_XTAL config CLKSRC_TANGO_XTAL
bool "Clocksource for Tango SoC" if COMPILE_TEST bool "Clocksource for Tango SoC" if COMPILE_TEST
depends on ARM depends on ARM
select CLKSRC_OF select TIMER_OF
select CLKSRC_MMIO select CLKSRC_MMIO
help help
This enables the clocksource for Tango SoC This enables the clocksource for Tango SoC
...@@ -605,7 +592,7 @@ config CLKSRC_IMX_GPT ...@@ -605,7 +592,7 @@ config CLKSRC_IMX_GPT
config CLKSRC_ST_LPC config CLKSRC_ST_LPC
bool "Low power clocksource found in the LPC" if COMPILE_TEST bool "Low power clocksource found in the LPC" if COMPILE_TEST
select CLKSRC_OF if OF select TIMER_OF if OF
depends on HAS_IOMEM depends on HAS_IOMEM
select CLKSRC_MMIO select CLKSRC_MMIO
help help
......
obj-$(CONFIG_CLKSRC_PROBE) += clksrc-probe.o obj-$(CONFIG_TIMER_OF) += timer-of.o
obj-$(CONFIG_CLKEVT_PROBE) += clkevt-probe.o obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
...@@ -26,7 +26,6 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o ...@@ -26,7 +26,6 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o
obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o
obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o
obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o
obj-$(CONFIG_MOXART_TIMER) += moxart_timer.o
obj-$(CONFIG_MXS_TIMER) += mxs_timer.o obj-$(CONFIG_MXS_TIMER) += mxs_timer.o
obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o
obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o
......
...@@ -99,7 +99,7 @@ static int __init arc_cs_setup_gfrc(struct device_node *node) ...@@ -99,7 +99,7 @@ static int __init arc_cs_setup_gfrc(struct device_node *node)
return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
} }
CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
#define AUX_RTC_CTRL 0x103 #define AUX_RTC_CTRL 0x103
#define AUX_RTC_LOW 0x104 #define AUX_RTC_LOW 0x104
...@@ -158,7 +158,7 @@ static int __init arc_cs_setup_rtc(struct device_node *node) ...@@ -158,7 +158,7 @@ static int __init arc_cs_setup_rtc(struct device_node *node)
return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
} }
CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
#endif #endif
...@@ -333,4 +333,4 @@ static int __init arc_of_timer_init(struct device_node *np) ...@@ -333,4 +333,4 @@ static int __init arc_of_timer_init(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
...@@ -1194,8 +1194,8 @@ static int __init arch_timer_of_init(struct device_node *np) ...@@ -1194,8 +1194,8 @@ static int __init arch_timer_of_init(struct device_node *np)
return arch_timer_common_init(); return arch_timer_common_init();
} }
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
static u32 __init static u32 __init
arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame) arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
...@@ -1382,7 +1382,7 @@ static int __init arch_timer_mem_of_init(struct device_node *np) ...@@ -1382,7 +1382,7 @@ static int __init arch_timer_mem_of_init(struct device_node *np)
kfree(timer_mem); kfree(timer_mem);
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
arch_timer_mem_of_init); arch_timer_mem_of_init);
#ifdef CONFIG_ACPI_GTDT #ifdef CONFIG_ACPI_GTDT
...@@ -1516,5 +1516,5 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) ...@@ -1516,5 +1516,5 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
return arch_timer_common_init(); return arch_timer_common_init();
} }
CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
#endif #endif
...@@ -339,5 +339,5 @@ static int __init global_timer_of_register(struct device_node *np) ...@@ -339,5 +339,5 @@ static int __init global_timer_of_register(struct device_node *np)
} }
/* Only tested on r2p2 and r3p0 */ /* Only tested on r2p2 and r3p0 */
CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer", TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
global_timer_of_register); global_timer_of_register);
...@@ -82,5 +82,5 @@ static int __init system_timer_of_register(struct device_node *np) ...@@ -82,5 +82,5 @@ static int __init system_timer_of_register(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(arm_systick, "arm,armv7m-systick", TIMER_OF_DECLARE(arm_systick, "arm,armv7m-systick",
system_timer_of_register); system_timer_of_register);
...@@ -238,5 +238,5 @@ static int __init asm9260_timer_init(struct device_node *np) ...@@ -238,5 +238,5 @@ static int __init asm9260_timer_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer", TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
asm9260_timer_init); asm9260_timer_init);
...@@ -148,5 +148,5 @@ static int __init bcm2835_timer_init(struct device_node *node) ...@@ -148,5 +148,5 @@ static int __init bcm2835_timer_init(struct device_node *node)
iounmap(base); iounmap(base);
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(bcm2835, "brcm,bcm2835-system-timer", TIMER_OF_DECLARE(bcm2835, "brcm,bcm2835-system-timer",
bcm2835_timer_init); bcm2835_timer_init);
...@@ -198,9 +198,9 @@ static int __init kona_timer_init(struct device_node *node) ...@@ -198,9 +198,9 @@ static int __init kona_timer_init(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(brcm_kona, "brcm,kona-timer", kona_timer_init); TIMER_OF_DECLARE(brcm_kona, "brcm,kona-timer", kona_timer_init);
/* /*
* bcm,kona-timer is deprecated by brcm,kona-timer * bcm,kona-timer is deprecated by brcm,kona-timer
* being kept here for driver compatibility * being kept here for driver compatibility
*/ */
CLOCKSOURCE_OF_DECLARE(bcm_kona, "bcm,kona-timer", kona_timer_init); TIMER_OF_DECLARE(bcm_kona, "bcm,kona-timer", kona_timer_init);
...@@ -539,4 +539,4 @@ static int __init ttc_timer_init(struct device_node *timer) ...@@ -539,4 +539,4 @@ static int __init ttc_timer_init(struct device_node *timer)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
/*
* Copyright (c) 2016, Linaro Ltd. All rights reserved.
* Daniel Lezcano <daniel.lezcano@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/clockchips.h>
extern struct of_device_id __clkevt_of_table[];
static const struct of_device_id __clkevt_of_table_sentinel
__used __section(__clkevt_of_table_end);
int __init clockevent_probe(void)
{
struct device_node *np;
const struct of_device_id *match;
of_init_fn_1_ret init_func;
int ret, clockevents = 0;
for_each_matching_node_and_match(np, __clkevt_of_table, &match) {
if (!of_device_is_available(np))
continue;
init_func = match->data;
ret = init_func(np);
if (ret) {
pr_warn("Failed to initialize '%s' (%d)\n",
np->name, ret);
continue;
}
clockevents++;
}
if (!clockevents) {
pr_crit("%s: no matching clockevent found\n", __func__);
return -ENODEV;
}
return 0;
}
...@@ -86,5 +86,5 @@ static int __init clksrc_dbx500_prcmu_init(struct device_node *node) ...@@ -86,5 +86,5 @@ static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
#endif #endif
return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
} }
CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
clksrc_dbx500_prcmu_init); clksrc_dbx500_prcmu_init);
...@@ -132,4 +132,4 @@ static int __init st_clksrc_of_register(struct device_node *np) ...@@ -132,4 +132,4 @@ static int __init st_clksrc_of_register(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register); TIMER_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);
...@@ -103,7 +103,7 @@ void __init clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base, ...@@ -103,7 +103,7 @@ void __init clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
BUG_ON(_clps711x_clkevt_init(tc2, tc2_base, irq)); BUG_ON(_clps711x_clkevt_init(tc2, tc2_base, irq));
} }
#ifdef CONFIG_CLKSRC_OF #ifdef CONFIG_TIMER_OF
static int __init clps711x_timer_init(struct device_node *np) static int __init clps711x_timer_init(struct device_node *np)
{ {
unsigned int irq = irq_of_parse_and_map(np, 0); unsigned int irq = irq_of_parse_and_map(np, 0);
...@@ -119,5 +119,5 @@ static int __init clps711x_timer_init(struct device_node *np) ...@@ -119,5 +119,5 @@ static int __init clps711x_timer_init(struct device_node *np)
return -EINVAL; return -EINVAL;
} }
} }
CLOCKSOURCE_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init); TIMER_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init);
#endif #endif
...@@ -167,7 +167,7 @@ static int __init dw_apb_timer_init(struct device_node *timer) ...@@ -167,7 +167,7 @@ static int __init dw_apb_timer_init(struct device_node *timer)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init); TIMER_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
CLOCKSOURCE_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init); TIMER_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
CLOCKSOURCE_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init); TIMER_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init); TIMER_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);
...@@ -610,5 +610,5 @@ static int __init mct_init_ppi(struct device_node *np) ...@@ -610,5 +610,5 @@ static int __init mct_init_ppi(struct device_node *np)
{ {
return mct_init_dt(np, MCT_INT_PPI); return mct_init_dt(np, MCT_INT_PPI);
} }
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
...@@ -369,4 +369,4 @@ static int __init ftm_timer_init(struct device_node *np) ...@@ -369,4 +369,4 @@ static int __init ftm_timer_init(struct device_node *np)
kfree(priv); kfree(priv);
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(flextimer, "fsl,ftm-timer", ftm_timer_init); TIMER_OF_DECLARE(flextimer, "fsl,ftm-timer", ftm_timer_init);
...@@ -187,5 +187,5 @@ static int __init h8300_16timer_init(struct device_node *node) ...@@ -187,5 +187,5 @@ static int __init h8300_16timer_init(struct device_node *node)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(h8300_16bit, "renesas,16bit-timer", TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
h8300_16timer_init); h8300_16timer_init);
...@@ -207,4 +207,4 @@ static int __init h8300_8timer_init(struct device_node *node) ...@@ -207,4 +207,4 @@ static int __init h8300_8timer_init(struct device_node *node)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init); TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
...@@ -154,4 +154,4 @@ static int __init h8300_tpu_init(struct device_node *node) ...@@ -154,4 +154,4 @@ static int __init h8300_tpu_init(struct device_node *node)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init); TIMER_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);
...@@ -246,4 +246,4 @@ static int __init jcore_pit_init(struct device_node *node) ...@@ -246,4 +246,4 @@ static int __init jcore_pit_init(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init); TIMER_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
...@@ -174,5 +174,5 @@ static int __init meson6_timer_init(struct device_node *node) ...@@ -174,5 +174,5 @@ static int __init meson6_timer_init(struct device_node *node)
1, 0xfffe); 1, 0xfffe);
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(meson6, "amlogic,meson6-timer", TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
meson6_timer_init); meson6_timer_init);
...@@ -200,5 +200,5 @@ static int __init gic_clocksource_of_init(struct device_node *node) ...@@ -200,5 +200,5 @@ static int __init gic_clocksource_of_init(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer", TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
gic_clocksource_of_init); gic_clocksource_of_init);
/*
* MOXA ART SoCs timer handling.
*
* Copyright (C) 2013 Jonas Jensen
*
* Jonas Jensen <jonas.jensen@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/bitops.h>
#include <linux/slab.h>
#define TIMER1_BASE 0x00
#define TIMER2_BASE 0x10
#define TIMER3_BASE 0x20
#define REG_COUNT 0x0 /* writable */
#define REG_LOAD 0x4
#define REG_MATCH1 0x8
#define REG_MATCH2 0xC
#define TIMER_CR 0x30
#define TIMER_INTR_STATE 0x34
#define TIMER_INTR_MASK 0x38
/*
* Moxart TIMER_CR flags:
*
* MOXART_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
* MOXART_CR_*_INT overflow interrupt enable bit
*/
#define MOXART_CR_1_ENABLE BIT(0)
#define MOXART_CR_1_CLOCK BIT(1)
#define MOXART_CR_1_INT BIT(2)
#define MOXART_CR_2_ENABLE BIT(3)
#define MOXART_CR_2_CLOCK BIT(4)
#define MOXART_CR_2_INT BIT(5)
#define MOXART_CR_3_ENABLE BIT(6)
#define MOXART_CR_3_CLOCK BIT(7)
#define MOXART_CR_3_INT BIT(8)
#define MOXART_CR_COUNT_UP BIT(9)
#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE)
#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE)
/*
* The ASpeed variant of the IP block has a different layout
* for the control register
*/
#define ASPEED_CR_1_ENABLE BIT(0)
#define ASPEED_CR_1_CLOCK BIT(1)
#define ASPEED_CR_1_INT BIT(2)
#define ASPEED_CR_2_ENABLE BIT(4)
#define ASPEED_CR_2_CLOCK BIT(5)
#define ASPEED_CR_2_INT BIT(6)
#define ASPEED_CR_3_ENABLE BIT(8)
#define ASPEED_CR_3_CLOCK BIT(9)
#define ASPEED_CR_3_INT BIT(10)
#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE)
#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE)
struct moxart_timer {
void __iomem *base;
unsigned int t1_disable_val;
unsigned int t1_enable_val;
unsigned int count_per_tick;
struct clock_event_device clkevt;
};
static inline struct moxart_timer *to_moxart(struct clock_event_device *evt)
{
return container_of(evt, struct moxart_timer, clkevt);
}
static inline void moxart_disable(struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
writel(timer->t1_disable_val, timer->base + TIMER_CR);
}
static inline void moxart_enable(struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
writel(timer->t1_enable_val, timer->base + TIMER_CR);
}
static int moxart_shutdown(struct clock_event_device *evt)
{
moxart_disable(evt);
return 0;
}
static int moxart_set_oneshot(struct clock_event_device *evt)
{
moxart_disable(evt);
writel(~0, to_moxart(evt)->base + TIMER1_BASE + REG_LOAD);
return 0;
}
static int moxart_set_periodic(struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
moxart_disable(evt);
writel(timer->count_per_tick, timer->base + TIMER1_BASE + REG_LOAD);
writel(0, timer->base + TIMER1_BASE + REG_MATCH1);
moxart_enable(evt);
return 0;
}
static int moxart_clkevt_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
u32 u;
moxart_disable(evt);
u = readl(timer->base + TIMER1_BASE + REG_COUNT) - cycles;
writel(u, timer->base + TIMER1_BASE + REG_MATCH1);
moxart_enable(evt);
return 0;
}
static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static int __init moxart_timer_init(struct device_node *node)
{
int ret, irq;
unsigned long pclk;
struct clk *clk;
struct moxart_timer *timer;
timer = kzalloc(sizeof(*timer), GFP_KERNEL);
if (!timer)
return -ENOMEM;
timer->base = of_iomap(node, 0);
if (!timer->base) {
pr_err("%s: of_iomap failed\n", node->full_name);
ret = -ENXIO;
goto out_free;
}
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0) {
pr_err("%s: irq_of_parse_and_map failed\n", node->full_name);
ret = -EINVAL;
goto out_unmap;
}
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_err("%s: of_clk_get failed\n", node->full_name);
ret = PTR_ERR(clk);
goto out_unmap;
}
pclk = clk_get_rate(clk);
if (of_device_is_compatible(node, "moxa,moxart-timer")) {
timer->t1_enable_val = MOXART_TIMER1_ENABLE;
timer->t1_disable_val = MOXART_TIMER1_DISABLE;
} else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) {
timer->t1_enable_val = ASPEED_TIMER1_ENABLE;
timer->t1_disable_val = ASPEED_TIMER1_DISABLE;
} else {
pr_err("%s: unknown platform\n", node->full_name);
ret = -EINVAL;
goto out_unmap;
}
timer->count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
timer->clkevt.name = node->name;
timer->clkevt.rating = 200;
timer->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;
timer->clkevt.set_state_shutdown = moxart_shutdown;
timer->clkevt.set_state_periodic = moxart_set_periodic;
timer->clkevt.set_state_oneshot = moxart_set_oneshot;
timer->clkevt.tick_resume = moxart_set_oneshot;
timer->clkevt.set_next_event = moxart_clkevt_next_event;
timer->clkevt.cpumask = cpumask_of(0);
timer->clkevt.irq = irq;
ret = clocksource_mmio_init(timer->base + TIMER2_BASE + REG_COUNT,
"moxart_timer", pclk, 200, 32,
clocksource_mmio_readl_down);
if (ret) {
pr_err("%s: clocksource_mmio_init failed\n", node->full_name);
goto out_unmap;
}
ret = request_irq(irq, moxart_timer_interrupt, IRQF_TIMER,
node->name, &timer->clkevt);
if (ret) {
pr_err("%s: setup_irq failed\n", node->full_name);
goto out_unmap;
}
/* Clear match registers */
writel(0, timer->base + TIMER1_BASE + REG_MATCH1);
writel(0, timer->base + TIMER1_BASE + REG_MATCH2);
writel(0, timer->base + TIMER2_BASE + REG_MATCH1);
writel(0, timer->base + TIMER2_BASE + REG_MATCH2);
/*
* Start timer 2 rolling as our main wall clock source, keep timer 1
* disabled
*/
writel(0, timer->base + TIMER_CR);
writel(~0, timer->base + TIMER2_BASE + REG_LOAD);
writel(timer->t1_disable_val, timer->base + TIMER_CR);
/*
* documentation is not publicly available:
* min_delta / max_delta obtained by trial-and-error,
* max_delta 0xfffffffe should be ok because count
* register size is u32
*/
clockevents_config_and_register(&timer->clkevt, pclk, 0x4, 0xfffffffe);
return 0;
out_unmap:
iounmap(timer->base);
out_free:
kfree(timer);
return ret;
}
CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);
CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init);
...@@ -274,4 +274,4 @@ static int __init mps2_timer_init(struct device_node *np) ...@@ -274,4 +274,4 @@ static int __init mps2_timer_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init); TIMER_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);
...@@ -265,4 +265,4 @@ static int __init mtk_timer_init(struct device_node *node) ...@@ -265,4 +265,4 @@ static int __init mtk_timer_init(struct device_node *node)
return -EINVAL; return -EINVAL;
} }
CLOCKSOURCE_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init); TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
...@@ -293,4 +293,4 @@ static int __init mxs_timer_init(struct device_node *np) ...@@ -293,4 +293,4 @@ static int __init mxs_timer_init(struct device_node *np)
return setup_irq(irq, &mxs_timer_irq); return setup_irq(irq, &mxs_timer_irq);
} }
CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init); TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
...@@ -284,5 +284,5 @@ static int __init nmdk_timer_of_init(struct device_node *node) ...@@ -284,5 +284,5 @@ static int __init nmdk_timer_of_init(struct device_node *node)
return nmdk_timer_init(base, irq, pclk, clk); return nmdk_timer_init(base, irq, pclk, clk);
} }
CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu", TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
nmdk_timer_of_init); nmdk_timer_of_init);
...@@ -216,7 +216,7 @@ static int __init pxa_timer_dt_init(struct device_node *np) ...@@ -216,7 +216,7 @@ static int __init pxa_timer_dt_init(struct device_node *np)
return pxa_timer_common_init(irq, clk_get_rate(clk)); return pxa_timer_common_init(irq, clk_get_rate(clk));
} }
CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init); TIMER_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
/* /*
* Legacy timer init for non device-tree boards. * Legacy timer init for non device-tree boards.
......
...@@ -254,5 +254,5 @@ static int __init msm_dt_timer_init(struct device_node *np) ...@@ -254,5 +254,5 @@ static int __init msm_dt_timer_init(struct device_node *np)
return msm_timer_init(freq, 32, irq, !!percpu_offset); return msm_timer_init(freq, 32, irq, !!percpu_offset);
} }
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
...@@ -262,4 +262,4 @@ static int __init ostm_init(struct device_node *np) ...@@ -262,4 +262,4 @@ static int __init ostm_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(ostm, "renesas,ostm", ostm_init); TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
...@@ -303,5 +303,5 @@ static int __init rk_timer_init(struct device_node *np) ...@@ -303,5 +303,5 @@ static int __init rk_timer_init(struct device_node *np)
return -EINVAL; return -EINVAL;
} }
CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init); TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init); TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
...@@ -418,7 +418,7 @@ void __init samsung_pwm_clocksource_init(void __iomem *base, ...@@ -418,7 +418,7 @@ void __init samsung_pwm_clocksource_init(void __iomem *base,
_samsung_pwm_clocksource_init(); _samsung_pwm_clocksource_init();
} }
#ifdef CONFIG_CLKSRC_OF #ifdef CONFIG_TIMER_OF
static int __init samsung_pwm_alloc(struct device_node *np, static int __init samsung_pwm_alloc(struct device_node *np,
const struct samsung_pwm_variant *variant) const struct samsung_pwm_variant *variant)
{ {
...@@ -466,7 +466,7 @@ static int __init s3c2410_pwm_clocksource_init(struct device_node *np) ...@@ -466,7 +466,7 @@ static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
{ {
return samsung_pwm_alloc(np, &s3c24xx_variant); return samsung_pwm_alloc(np, &s3c24xx_variant);
} }
CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init); TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
static const struct samsung_pwm_variant s3c64xx_variant = { static const struct samsung_pwm_variant s3c64xx_variant = {
.bits = 32, .bits = 32,
...@@ -479,7 +479,7 @@ static int __init s3c64xx_pwm_clocksource_init(struct device_node *np) ...@@ -479,7 +479,7 @@ static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{ {
return samsung_pwm_alloc(np, &s3c64xx_variant); return samsung_pwm_alloc(np, &s3c64xx_variant);
} }
CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init); TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
static const struct samsung_pwm_variant s5p64x0_variant = { static const struct samsung_pwm_variant s5p64x0_variant = {
.bits = 32, .bits = 32,
...@@ -492,7 +492,7 @@ static int __init s5p64x0_pwm_clocksource_init(struct device_node *np) ...@@ -492,7 +492,7 @@ static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{ {
return samsung_pwm_alloc(np, &s5p64x0_variant); return samsung_pwm_alloc(np, &s5p64x0_variant);
} }
CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init); TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
static const struct samsung_pwm_variant s5p_variant = { static const struct samsung_pwm_variant s5p_variant = {
.bits = 32, .bits = 32,
...@@ -505,5 +505,5 @@ static int __init s5p_pwm_clocksource_init(struct device_node *np) ...@@ -505,5 +505,5 @@ static int __init s5p_pwm_clocksource_init(struct device_node *np)
{ {
return samsung_pwm_alloc(np, &s5p_variant); return samsung_pwm_alloc(np, &s5p_variant);
} }
CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init); TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif #endif
...@@ -233,5 +233,5 @@ static int __init sun4i_timer_init(struct device_node *node) ...@@ -233,5 +233,5 @@ static int __init sun4i_timer_init(struct device_node *node)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init); sun4i_timer_init);
...@@ -53,4 +53,4 @@ static int __init tango_clocksource_init(struct device_node *np) ...@@ -53,4 +53,4 @@ static int __init tango_clocksource_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(tango, "sigma,tick-counter", tango_clocksource_init); TIMER_OF_DECLARE(tango, "sigma,tick-counter", tango_clocksource_init);
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/atmel_tc.h> #include <linux/atmel_tc.h>
...@@ -40,6 +41,14 @@ ...@@ -40,6 +41,14 @@
*/ */
static void __iomem *tcaddr; static void __iomem *tcaddr;
static struct
{
u32 cmr;
u32 imr;
u32 rc;
bool clken;
} tcb_cache[3];
static u32 bmr_cache;
static u64 tc_get_cycles(struct clocksource *cs) static u64 tc_get_cycles(struct clocksource *cs)
{ {
...@@ -61,12 +70,54 @@ static u64 tc_get_cycles32(struct clocksource *cs) ...@@ -61,12 +70,54 @@ static u64 tc_get_cycles32(struct clocksource *cs)
return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
} }
void tc_clksrc_suspend(struct clocksource *cs)
{
int i;
for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
ATMEL_TC_CLKSTA);
}
bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
}
void tc_clksrc_resume(struct clocksource *cs)
{
int i;
for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
/* Restore registers for the channel, RA and RB are not used */
writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
writel(0, tcaddr + ATMEL_TC_REG(i, RA));
writel(0, tcaddr + ATMEL_TC_REG(i, RB));
/* Disable all the interrupts */
writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
/* Reenable interrupts that were enabled before suspending */
writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
/* Start the clock if it was used */
if (tcb_cache[i].clken)
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
}
/* Dual channel, chain channels */
writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
/* Finally, trigger all the channels*/
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}
static struct clocksource clksrc = { static struct clocksource clksrc = {
.name = "tcb_clksrc", .name = "tcb_clksrc",
.rating = 200, .rating = 200,
.read = tc_get_cycles, .read = tc_get_cycles,
.mask = CLOCKSOURCE_MASK(32), .mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS, .flags = CLOCK_SOURCE_IS_CONTINUOUS,
.suspend = tc_clksrc_suspend,
.resume = tc_clksrc_resume,
}; };
#ifdef CONFIG_GENERIC_CLOCKEVENTS #ifdef CONFIG_GENERIC_CLOCKEVENTS
......
...@@ -237,7 +237,7 @@ static int __init tegra20_init_timer(struct device_node *np) ...@@ -237,7 +237,7 @@ static int __init tegra20_init_timer(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
static int __init tegra20_init_rtc(struct device_node *np) static int __init tegra20_init_rtc(struct device_node *np)
{ {
...@@ -261,4 +261,4 @@ static int __init tegra20_init_rtc(struct device_node *np) ...@@ -261,4 +261,4 @@ static int __init tegra20_init_rtc(struct device_node *np)
return register_persistent_clock(NULL, tegra_read_persistent_clock64); return register_persistent_clock(NULL, tegra_read_persistent_clock64);
} }
CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
...@@ -351,7 +351,7 @@ static int __init armada_xp_timer_init(struct device_node *np) ...@@ -351,7 +351,7 @@ static int __init armada_xp_timer_init(struct device_node *np)
return armada_370_xp_timer_common_init(np); return armada_370_xp_timer_common_init(np);
} }
CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer", TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
armada_xp_timer_init); armada_xp_timer_init);
static int __init armada_375_timer_init(struct device_node *np) static int __init armada_375_timer_init(struct device_node *np)
...@@ -389,7 +389,7 @@ static int __init armada_375_timer_init(struct device_node *np) ...@@ -389,7 +389,7 @@ static int __init armada_375_timer_init(struct device_node *np)
return armada_370_xp_timer_common_init(np); return armada_370_xp_timer_common_init(np);
} }
CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer", TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
armada_375_timer_init); armada_375_timer_init);
static int __init armada_370_timer_init(struct device_node *np) static int __init armada_370_timer_init(struct device_node *np)
...@@ -412,5 +412,5 @@ static int __init armada_370_timer_init(struct device_node *np) ...@@ -412,5 +412,5 @@ static int __init armada_370_timer_init(struct device_node *np)
return armada_370_xp_timer_common_init(np); return armada_370_xp_timer_common_init(np);
} }
CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer", TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
armada_370_timer_init); armada_370_timer_init);
...@@ -283,5 +283,5 @@ static int __init efm32_timer_init(struct device_node *np) ...@@ -283,5 +283,5 @@ static int __init efm32_timer_init(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(efm32compat, "efm32,timer", efm32_timer_init); TIMER_OF_DECLARE(efm32compat, "efm32,timer", efm32_timer_init);
CLOCKSOURCE_OF_DECLARE(efm32, "energymicro,efm32-timer", efm32_timer_init); TIMER_OF_DECLARE(efm32, "energymicro,efm32-timer", efm32_timer_init);
...@@ -311,4 +311,4 @@ static int __init lpc32xx_timer_init(struct device_node *np) ...@@ -311,4 +311,4 @@ static int __init lpc32xx_timer_init(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init); TIMER_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init);
...@@ -189,4 +189,4 @@ static int __init orion_timer_init(struct device_node *np) ...@@ -189,4 +189,4 @@ static int __init orion_timer_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init); TIMER_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);
...@@ -214,5 +214,5 @@ static int __init pistachio_clksrc_of_init(struct device_node *node) ...@@ -214,5 +214,5 @@ static int __init pistachio_clksrc_of_init(struct device_node *node)
sched_clock_register(pistachio_read_sched_clock, 32, rate); sched_clock_register(pistachio_read_sched_clock, 32, rate);
return clocksource_register_hz(&pcs_gpt.cs, rate); return clocksource_register_hz(&pcs_gpt.cs, rate);
} }
CLOCKSOURCE_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer", TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
pistachio_clksrc_of_init); pistachio_clksrc_of_init);
...@@ -283,4 +283,4 @@ static int __init sirfsoc_of_timer_init(struct device_node *np) ...@@ -283,4 +283,4 @@ static int __init sirfsoc_of_timer_init(struct device_node *np)
return sirfsoc_atlas7_timer_init(np); return sirfsoc_atlas7_timer_init(np);
} }
CLOCKSOURCE_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init); TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);
...@@ -255,5 +255,5 @@ static int __init at91sam926x_pit_dt_init(struct device_node *node) ...@@ -255,5 +255,5 @@ static int __init at91sam926x_pit_dt_init(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit", TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
at91sam926x_pit_dt_init); at91sam926x_pit_dt_init);
...@@ -260,5 +260,5 @@ static int __init atmel_st_timer_init(struct device_node *node) ...@@ -260,5 +260,5 @@ static int __init atmel_st_timer_init(struct device_node *node)
/* register clocksource */ /* register clocksource */
return clocksource_register_hz(&clk32k, sclk_rate); return clocksource_register_hz(&clk32k, sclk_rate);
} }
CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st", TIMER_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
atmel_st_timer_init); atmel_st_timer_init);
...@@ -203,5 +203,5 @@ static int __init digicolor_timer_init(struct device_node *node) ...@@ -203,5 +203,5 @@ static int __init digicolor_timer_init(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer", TIMER_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer",
digicolor_timer_init); digicolor_timer_init);
...@@ -11,12 +11,13 @@ ...@@ -11,12 +11,13 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/clockchips.h> #include <linux/clockchips.h>
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <linux/sched_clock.h> #include <linux/sched_clock.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/delay.h>
/* /*
* Register definitions for the timers * Register definitions for the timers
...@@ -37,267 +38,368 @@ ...@@ -37,267 +38,368 @@
#define TIMER_INTR_STATE (0x34) #define TIMER_INTR_STATE (0x34)
#define TIMER_INTR_MASK (0x38) #define TIMER_INTR_MASK (0x38)
#define TIMER_1_CR_ENABLE (1 << 0) #define TIMER_1_CR_ENABLE BIT(0)
#define TIMER_1_CR_CLOCK (1 << 1) #define TIMER_1_CR_CLOCK BIT(1)
#define TIMER_1_CR_INT (1 << 2) #define TIMER_1_CR_INT BIT(2)
#define TIMER_2_CR_ENABLE (1 << 3) #define TIMER_2_CR_ENABLE BIT(3)
#define TIMER_2_CR_CLOCK (1 << 4) #define TIMER_2_CR_CLOCK BIT(4)
#define TIMER_2_CR_INT (1 << 5) #define TIMER_2_CR_INT BIT(5)
#define TIMER_3_CR_ENABLE (1 << 6) #define TIMER_3_CR_ENABLE BIT(6)
#define TIMER_3_CR_CLOCK (1 << 7) #define TIMER_3_CR_CLOCK BIT(7)
#define TIMER_3_CR_INT (1 << 8) #define TIMER_3_CR_INT BIT(8)
#define TIMER_1_CR_UPDOWN (1 << 9) #define TIMER_1_CR_UPDOWN BIT(9)
#define TIMER_2_CR_UPDOWN (1 << 10) #define TIMER_2_CR_UPDOWN BIT(10)
#define TIMER_3_CR_UPDOWN (1 << 11) #define TIMER_3_CR_UPDOWN BIT(11)
#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
TIMER_3_CR_ENABLE | \ /*
TIMER_3_CR_UPDOWN) * The Aspeed AST2400 moves bits around in the control register
* and lacks bits for setting the timer to count upwards.
#define TIMER_1_INT_MATCH1 (1 << 0) */
#define TIMER_1_INT_MATCH2 (1 << 1) #define TIMER_1_CR_ASPEED_ENABLE BIT(0)
#define TIMER_1_INT_OVERFLOW (1 << 2) #define TIMER_1_CR_ASPEED_CLOCK BIT(1)
#define TIMER_2_INT_MATCH1 (1 << 3) #define TIMER_1_CR_ASPEED_INT BIT(2)
#define TIMER_2_INT_MATCH2 (1 << 4) #define TIMER_2_CR_ASPEED_ENABLE BIT(4)
#define TIMER_2_INT_OVERFLOW (1 << 5) #define TIMER_2_CR_ASPEED_CLOCK BIT(5)
#define TIMER_3_INT_MATCH1 (1 << 6) #define TIMER_2_CR_ASPEED_INT BIT(6)
#define TIMER_3_INT_MATCH2 (1 << 7) #define TIMER_3_CR_ASPEED_ENABLE BIT(8)
#define TIMER_3_INT_OVERFLOW (1 << 8) #define TIMER_3_CR_ASPEED_CLOCK BIT(9)
#define TIMER_3_CR_ASPEED_INT BIT(10)
#define TIMER_1_INT_MATCH1 BIT(0)
#define TIMER_1_INT_MATCH2 BIT(1)
#define TIMER_1_INT_OVERFLOW BIT(2)
#define TIMER_2_INT_MATCH1 BIT(3)
#define TIMER_2_INT_MATCH2 BIT(4)
#define TIMER_2_INT_OVERFLOW BIT(5)
#define TIMER_3_INT_MATCH1 BIT(6)
#define TIMER_3_INT_MATCH2 BIT(7)
#define TIMER_3_INT_OVERFLOW BIT(8)
#define TIMER_INT_ALL_MASK 0x1ff #define TIMER_INT_ALL_MASK 0x1ff
static unsigned int tick_rate; struct fttmr010 {
static void __iomem *base; void __iomem *base;
unsigned int tick_rate;
bool count_down;
u32 t1_enable_val;
struct clock_event_device clkevt;
#ifdef CONFIG_ARM
struct delay_timer delay_timer;
#endif
};
/*
* A local singleton used by sched_clock and delay timer reads, which are
* fast and stateless
*/
static struct fttmr010 *local_fttmr;
static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
{
return container_of(evt, struct fttmr010, clkevt);
}
static unsigned long fttmr010_read_current_timer_up(void)
{
return readl(local_fttmr->base + TIMER2_COUNT);
}
static unsigned long fttmr010_read_current_timer_down(void)
{
return ~readl(local_fttmr->base + TIMER2_COUNT);
}
static u64 notrace fttmr010_read_sched_clock_up(void)
{
return fttmr010_read_current_timer_up();
}
static u64 notrace fttmr010_read_sched_clock(void) static u64 notrace fttmr010_read_sched_clock_down(void)
{ {
return readl(base + TIMER3_COUNT); return fttmr010_read_current_timer_down();
} }
static int fttmr010_timer_set_next_event(unsigned long cycles, static int fttmr010_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt) struct clock_event_device *evt)
{ {
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 cr; u32 cr;
/* Setup the match register */ /* Stop */
cr = readl(base + TIMER1_COUNT); cr = readl(fttmr010->base + TIMER_CR);
writel(cr + cycles, base + TIMER1_MATCH1); cr &= ~fttmr010->t1_enable_val;
if (readl(base + TIMER1_COUNT) - cr > cycles) writel(cr, fttmr010->base + TIMER_CR);
return -ETIME;
/* Setup the match register forward/backward in time */
cr = readl(fttmr010->base + TIMER1_COUNT);
if (fttmr010->count_down)
cr -= cycles;
else
cr += cycles;
writel(cr, fttmr010->base + TIMER1_MATCH1);
/* Start */
cr = readl(fttmr010->base + TIMER_CR);
cr |= fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
return 0; return 0;
} }
static int fttmr010_timer_shutdown(struct clock_event_device *evt) static int fttmr010_timer_shutdown(struct clock_event_device *evt)
{ {
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 cr; u32 cr;
/* /* Stop */
* Disable also for oneshot: the set_next() call will arm the timer cr = readl(fttmr010->base + TIMER_CR);
* instead. cr &= ~fttmr010->t1_enable_val;
*/ writel(cr, fttmr010->base + TIMER_CR);
/* Stop timer and interrupt. */
cr = readl(base + TIMER_CR); return 0;
cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); }
writel(cr, base + TIMER_CR);
static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
{
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 cr;
/* Stop */
cr = readl(fttmr010->base + TIMER_CR);
cr &= ~fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
/* Setup counter start from 0 */ /* Setup counter start from 0 or ~0 */
writel(0, base + TIMER1_COUNT); writel(0, fttmr010->base + TIMER1_COUNT);
writel(0, base + TIMER1_LOAD); if (fttmr010->count_down)
writel(~0, fttmr010->base + TIMER1_LOAD);
else
writel(0, fttmr010->base + TIMER1_LOAD);
/* enable interrupt */ /* Enable interrupt */
cr = readl(base + TIMER_INTR_MASK); cr = readl(fttmr010->base + TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_MATCH1; cr |= TIMER_1_INT_MATCH1;
writel(cr, base + TIMER_INTR_MASK); writel(cr, fttmr010->base + TIMER_INTR_MASK);
/* start the timer */
cr = readl(base + TIMER_CR);
cr |= TIMER_1_CR_ENABLE;
writel(cr, base + TIMER_CR);
return 0; return 0;
} }
static int fttmr010_timer_set_periodic(struct clock_event_device *evt) static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
{ {
u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
u32 cr; u32 cr;
/* Stop timer and interrupt */ /* Stop */
cr = readl(base + TIMER_CR); cr = readl(fttmr010->base + TIMER_CR);
cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); cr &= ~fttmr010->t1_enable_val;
writel(cr, base + TIMER_CR); writel(cr, fttmr010->base + TIMER_CR);
/* Setup timer to fire at 1/HT intervals. */ /* Setup timer to fire at 1/HZ intervals. */
cr = 0xffffffff - (period - 1); if (fttmr010->count_down) {
writel(cr, base + TIMER1_COUNT); writel(period, fttmr010->base + TIMER1_LOAD);
writel(cr, base + TIMER1_LOAD); writel(0, fttmr010->base + TIMER1_MATCH1);
} else {
/* enable interrupt on overflow */ cr = 0xffffffff - (period - 1);
cr = readl(base + TIMER_INTR_MASK); writel(cr, fttmr010->base + TIMER1_COUNT);
cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); writel(cr, fttmr010->base + TIMER1_LOAD);
cr |= TIMER_1_INT_OVERFLOW;
writel(cr, base + TIMER_INTR_MASK); /* Enable interrupt on overflow */
cr = readl(fttmr010->base + TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_OVERFLOW;
writel(cr, fttmr010->base + TIMER_INTR_MASK);
}
/* Start the timer */ /* Start the timer */
cr = readl(base + TIMER_CR); cr = readl(fttmr010->base + TIMER_CR);
cr |= TIMER_1_CR_ENABLE; cr |= fttmr010->t1_enable_val;
cr |= TIMER_1_CR_INT; writel(cr, fttmr010->base + TIMER_CR);
writel(cr, base + TIMER_CR);
return 0; return 0;
} }
/* Use TIMER1 as clock event */
static struct clock_event_device fttmr010_clockevent = {
.name = "TIMER1",
/* Reasonably fast and accurate clock event */
.rating = 300,
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = fttmr010_timer_set_next_event,
.set_state_shutdown = fttmr010_timer_shutdown,
.set_state_periodic = fttmr010_timer_set_periodic,
.set_state_oneshot = fttmr010_timer_shutdown,
.tick_resume = fttmr010_timer_shutdown,
};
/* /*
* IRQ handler for the timer * IRQ handler for the timer
*/ */
static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
{ {
struct clock_event_device *evt = &fttmr010_clockevent; struct clock_event_device *evt = dev_id;
evt->event_handler(evt); evt->event_handler(evt);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static struct irqaction fttmr010_timer_irq = { static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
.name = "Faraday FTTMR010 Timer Tick",
.flags = IRQF_TIMER,
.handler = fttmr010_timer_interrupt,
};
static int __init fttmr010_timer_common_init(struct device_node *np)
{ {
struct fttmr010 *fttmr010;
int irq; int irq;
struct clk *clk;
int ret;
u32 val;
/*
* These implementations require a clock reference.
* FIXME: we currently only support clocking using PCLK
* and using EXTCLK is not supported in the driver.
*/
clk = of_clk_get_by_name(np, "PCLK");
if (IS_ERR(clk)) {
pr_err("could not get PCLK\n");
return PTR_ERR(clk);
}
ret = clk_prepare_enable(clk);
if (ret) {
pr_err("failed to enable PCLK\n");
return ret;
}
base = of_iomap(np, 0); fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
if (!base) { if (!fttmr010) {
ret = -ENOMEM;
goto out_disable_clock;
}
fttmr010->tick_rate = clk_get_rate(clk);
fttmr010->base = of_iomap(np, 0);
if (!fttmr010->base) {
pr_err("Can't remap registers"); pr_err("Can't remap registers");
return -ENXIO; ret = -ENXIO;
goto out_free;
} }
/* IRQ for timer 1 */ /* IRQ for timer 1 */
irq = irq_of_parse_and_map(np, 0); irq = irq_of_parse_and_map(np, 0);
if (irq <= 0) { if (irq <= 0) {
pr_err("Can't parse IRQ"); pr_err("Can't parse IRQ");
return -EINVAL; ret = -EINVAL;
goto out_unmap;
}
/*
* The Aspeed AST2400 moves bits around in the control register,
* otherwise it works the same.
*/
if (is_aspeed) {
fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
TIMER_1_CR_ASPEED_INT;
/* Downward not available */
fttmr010->count_down = true;
} else {
fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
} }
/* /*
* Reset the interrupt mask and status * Reset the interrupt mask and status
*/ */
writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK); writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
writel(0, base + TIMER_INTR_STATE); writel(0, fttmr010->base + TIMER_INTR_STATE);
writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR);
/*
* Enable timer 1 count up, timer 2 count up, except on Aspeed,
* where everything just counts down.
*/
if (is_aspeed)
val = TIMER_2_CR_ASPEED_ENABLE;
else {
val = TIMER_2_CR_ENABLE;
if (!fttmr010->count_down)
val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
}
writel(val, fttmr010->base + TIMER_CR);
/* /*
* Setup free-running clocksource timer (interrupts * Setup free-running clocksource timer (interrupts
* disabled.) * disabled.)
*/ */
writel(0, base + TIMER3_COUNT); local_fttmr = fttmr010;
writel(0, base + TIMER3_LOAD); writel(0, fttmr010->base + TIMER2_COUNT);
writel(0, base + TIMER3_MATCH1); writel(0, fttmr010->base + TIMER2_MATCH1);
writel(0, base + TIMER3_MATCH2); writel(0, fttmr010->base + TIMER2_MATCH2);
clocksource_mmio_init(base + TIMER3_COUNT,
"fttmr010_clocksource", tick_rate, if (fttmr010->count_down) {
300, 32, clocksource_mmio_readl_up); writel(~0, fttmr010->base + TIMER2_LOAD);
sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate); clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
"FTTMR010-TIMER2",
fttmr010->tick_rate,
300, 32, clocksource_mmio_readl_down);
sched_clock_register(fttmr010_read_sched_clock_down, 32,
fttmr010->tick_rate);
} else {
writel(0, fttmr010->base + TIMER2_LOAD);
clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
"FTTMR010-TIMER2",
fttmr010->tick_rate,
300, 32, clocksource_mmio_readl_up);
sched_clock_register(fttmr010_read_sched_clock_up, 32,
fttmr010->tick_rate);
}
/* /*
* Setup clockevent timer (interrupt-driven.) * Setup clockevent timer (interrupt-driven) on timer 1.
*/ */
writel(0, base + TIMER1_COUNT); writel(0, fttmr010->base + TIMER1_COUNT);
writel(0, base + TIMER1_LOAD); writel(0, fttmr010->base + TIMER1_LOAD);
writel(0, base + TIMER1_MATCH1); writel(0, fttmr010->base + TIMER1_MATCH1);
writel(0, base + TIMER1_MATCH2); writel(0, fttmr010->base + TIMER1_MATCH2);
setup_irq(irq, &fttmr010_timer_irq); ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
fttmr010_clockevent.cpumask = cpumask_of(0); "FTTMR010-TIMER1", &fttmr010->clkevt);
clockevents_config_and_register(&fttmr010_clockevent, tick_rate, if (ret) {
pr_err("FTTMR010-TIMER1 no IRQ\n");
goto out_unmap;
}
fttmr010->clkevt.name = "FTTMR010-TIMER1";
/* Reasonably fast and accurate clock event */
fttmr010->clkevt.rating = 300;
fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;
fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
fttmr010->clkevt.cpumask = cpumask_of(0);
fttmr010->clkevt.irq = irq;
clockevents_config_and_register(&fttmr010->clkevt,
fttmr010->tick_rate,
1, 0xffffffff); 1, 0xffffffff);
return 0; #ifdef CONFIG_ARM
} /* Also use this timer for delays */
if (fttmr010->count_down)
fttmr010->delay_timer.read_current_timer =
fttmr010_read_current_timer_down;
else
fttmr010->delay_timer.read_current_timer =
fttmr010_read_current_timer_up;
fttmr010->delay_timer.freq = fttmr010->tick_rate;
register_current_timer_delay(&fttmr010->delay_timer);
#endif
static int __init fttmr010_timer_of_init(struct device_node *np) return 0;
{
/*
* These implementations require a clock reference.
* FIXME: we currently only support clocking using PCLK
* and using EXTCLK is not supported in the driver.
*/
struct clk *clk;
clk = of_clk_get_by_name(np, "PCLK"); out_unmap:
if (IS_ERR(clk)) { iounmap(fttmr010->base);
pr_err("could not get PCLK"); out_free:
return PTR_ERR(clk); kfree(fttmr010);
} out_disable_clock:
tick_rate = clk_get_rate(clk); clk_disable_unprepare(clk);
return fttmr010_timer_common_init(np); return ret;
} }
CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init);
/* static __init int aspeed_timer_init(struct device_node *np)
* Gemini-specific: relevant registers in the global syscon
*/
#define GLOBAL_STATUS 0x04
#define CPU_AHB_RATIO_MASK (0x3 << 18)
#define CPU_AHB_1_1 (0x0 << 18)
#define CPU_AHB_3_2 (0x1 << 18)
#define CPU_AHB_24_13 (0x2 << 18)
#define CPU_AHB_2_1 (0x3 << 18)
#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
static int __init gemini_timer_of_init(struct device_node *np)
{ {
static struct regmap *map; return fttmr010_common_init(np, true);
int ret; }
u32 val;
map = syscon_regmap_lookup_by_phandle(np, "syscon");
if (IS_ERR(map)) {
pr_err("Can't get regmap for syscon handle\n");
return -ENODEV;
}
ret = regmap_read(map, GLOBAL_STATUS, &val);
if (ret) {
pr_err("Can't read syscon status register\n");
return -ENXIO;
}
tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
pr_info("Bus: %dMHz ", tick_rate / 1000000);
tick_rate /= 6; /* APB bus run AHB*(1/6) */
switch (val & CPU_AHB_RATIO_MASK) {
case CPU_AHB_1_1:
pr_cont("(1/1)\n");
break;
case CPU_AHB_3_2:
pr_cont("(3/2)\n");
break;
case CPU_AHB_24_13:
pr_cont("(24/13)\n");
break;
case CPU_AHB_2_1:
pr_cont("(2/1)\n");
break;
}
return fttmr010_timer_common_init(np); static __init int fttmr010_timer_init(struct device_node *np)
{
return fttmr010_common_init(np, false);
} }
CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init);
TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
...@@ -545,15 +545,15 @@ static int __init imx6dl_timer_init_dt(struct device_node *np) ...@@ -545,15 +545,15 @@ static int __init imx6dl_timer_init_dt(struct device_node *np)
return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
} }
CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt); TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
...@@ -232,5 +232,5 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) ...@@ -232,5 +232,5 @@ static int __init integrator_ap_timer_init_of(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer", TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
integrator_ap_timer_init_of); integrator_ap_timer_init_of);
...@@ -226,5 +226,5 @@ static int __init keystone_timer_init(struct device_node *np) ...@@ -226,5 +226,5 @@ static int __init keystone_timer_init(struct device_node *np)
return error; return error;
} }
CLOCKSOURCE_OF_DECLARE(keystone_timer, "ti,keystone-timer", TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
keystone_timer_init); keystone_timer_init);
...@@ -110,9 +110,9 @@ static int __init nps_setup_clocksource(struct device_node *node) ...@@ -110,9 +110,9 @@ static int __init nps_setup_clocksource(struct device_node *node)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
nps_setup_clocksource); nps_setup_clocksource);
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1", TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
nps_setup_clocksource); nps_setup_clocksource);
#ifdef CONFIG_EZNPS_MTM_EXT #ifdef CONFIG_EZNPS_MTM_EXT
...@@ -279,6 +279,6 @@ static int __init nps_setup_clockevent(struct device_node *node) ...@@ -279,6 +279,6 @@ static int __init nps_setup_clockevent(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0", TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
nps_setup_clockevent); nps_setup_clockevent);
#endif /* CONFIG_EZNPS_MTM_EXT */ #endif /* CONFIG_EZNPS_MTM_EXT */
/*
* Copyright (c) 2017, Linaro Ltd. All rights reserved.
*
* Author: Daniel Lezcano <daniel.lezcano@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include "timer-of.h"
static __init void timer_irq_exit(struct of_timer_irq *of_irq)
{
struct timer_of *to = container_of(of_irq, struct timer_of, of_irq);
struct clock_event_device *clkevt = &to->clkevt;
of_irq->percpu ? free_percpu_irq(of_irq->irq, clkevt) :
free_irq(of_irq->irq, clkevt);
}
static __init int timer_irq_init(struct device_node *np,
struct of_timer_irq *of_irq)
{
int ret;
struct timer_of *to = container_of(of_irq, struct timer_of, of_irq);
struct clock_event_device *clkevt = &to->clkevt;
of_irq->irq = of_irq->name ? of_irq_get_byname(np, of_irq->name):
irq_of_parse_and_map(np, of_irq->index);
if (!of_irq->irq) {
pr_err("Failed to map interrupt for %s\n", np->full_name);
return -EINVAL;
}
ret = of_irq->percpu ?
request_percpu_irq(of_irq->irq, of_irq->handler,
np->full_name, clkevt) :
request_irq(of_irq->irq, of_irq->handler,
of_irq->flags ? of_irq->flags : IRQF_TIMER,
np->full_name, clkevt);
if (ret) {
pr_err("Failed to request irq %d for %s\n", of_irq->irq,
np->full_name);
return ret;
}
clkevt->irq = of_irq->irq;
return 0;
}
static __init void timer_clk_exit(struct of_timer_clk *of_clk)
{
of_clk->rate = 0;
clk_disable_unprepare(of_clk->clk);
clk_put(of_clk->clk);
}
static __init int timer_clk_init(struct device_node *np,
struct of_timer_clk *of_clk)
{
int ret;
of_clk->clk = of_clk->name ? of_clk_get_by_name(np, of_clk->name) :
of_clk_get(np, of_clk->index);
if (IS_ERR(of_clk->clk)) {
pr_err("Failed to get clock for %s\n", np->full_name);
return PTR_ERR(of_clk->clk);
}
ret = clk_prepare_enable(of_clk->clk);
if (ret) {
pr_err("Failed for enable clock for %s\n", np->full_name);
goto out_clk_put;
}
of_clk->rate = clk_get_rate(of_clk->clk);
if (!of_clk->rate) {
ret = -EINVAL;
pr_err("Failed to get clock rate for %s\n", np->full_name);
goto out_clk_disable;
}
of_clk->period = DIV_ROUND_UP(of_clk->rate, HZ);
out:
return ret;
out_clk_disable:
clk_disable_unprepare(of_clk->clk);
out_clk_put:
clk_put(of_clk->clk);
goto out;
}
static __init void timer_base_exit(struct of_timer_base *of_base)
{
iounmap(of_base->base);
}
static __init int timer_base_init(struct device_node *np,
struct of_timer_base *of_base)
{
const char *name = of_base->name ? of_base->name : np->full_name;
of_base->base = of_io_request_and_map(np, of_base->index, name);
if (of_base->base) {
pr_err("Failed to iomap (%s)\n", name);
return -ENXIO;
}
return 0;
}
int __init timer_of_init(struct device_node *np, struct timer_of *to)
{
int ret;
int flags = 0;
if (to->flags & TIMER_OF_BASE) {
ret = timer_base_init(np, &to->of_base);
if (ret)
goto out_fail;
flags |= TIMER_OF_BASE;
}
if (to->flags & TIMER_OF_CLOCK) {
ret = timer_clk_init(np, &to->of_clk);
if (ret)
goto out_fail;
flags |= TIMER_OF_CLOCK;
}
if (to->flags & TIMER_OF_IRQ) {
ret = timer_irq_init(np, &to->of_irq);
if (ret)
goto out_fail;
flags |= TIMER_OF_IRQ;
}
if (!to->clkevt.name)
to->clkevt.name = np->name;
out:
return ret;
out_fail:
if (flags & TIMER_OF_IRQ)
timer_irq_exit(&to->of_irq);
if (flags & TIMER_OF_CLOCK)
timer_clk_exit(&to->of_clk);
if (flags & TIMER_OF_BASE)
timer_base_exit(&to->of_base);
goto out;
}
#ifndef __TIMER_OF_H__
#define __TIMER_OF_H__
#include <linux/clockchips.h>
#define TIMER_OF_BASE 0x1
#define TIMER_OF_CLOCK 0x2
#define TIMER_OF_IRQ 0x4
struct of_timer_irq {
int irq;
int index;
int percpu;
const char *name;
unsigned long flags;
irq_handler_t handler;
};
struct of_timer_base {
void __iomem *base;
const char *name;
int index;
};
struct of_timer_clk {
struct clk *clk;
const char *name;
int index;
unsigned long rate;
unsigned long period;
};
struct timer_of {
unsigned int flags;
struct clock_event_device clkevt;
struct of_timer_base of_base;
struct of_timer_irq of_irq;
struct of_timer_clk of_clk;
void *private_data;
};
static inline struct timer_of *to_timer_of(struct clock_event_device *clkevt)
{
return container_of(clkevt, struct timer_of, clkevt);
}
static inline void __iomem *timer_of_base(struct timer_of *to)
{
return to->of_base.base;
}
static inline int timer_of_irq(struct timer_of *to)
{
return to->of_irq.irq;
}
static inline unsigned long timer_of_rate(struct timer_of *to)
{
return to->of_clk.rate;
}
static inline unsigned long timer_of_period(struct timer_of *to)
{
return to->of_clk.period;
}
extern int __init timer_of_init(struct device_node *np,
struct timer_of *to);
#endif
...@@ -293,7 +293,7 @@ static int __init oxnas_rps_timer_init(struct device_node *np) ...@@ -293,7 +293,7 @@ static int __init oxnas_rps_timer_init(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(ox810se_rps, TIMER_OF_DECLARE(ox810se_rps,
"oxsemi,ox810se-rps-timer", oxnas_rps_timer_init); "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
CLOCKSOURCE_OF_DECLARE(ox820_rps, TIMER_OF_DECLARE(ox820_rps,
"oxsemi,ox820se-rps-timer", oxnas_rps_timer_init); "oxsemi,ox820se-rps-timer", oxnas_rps_timer_init);
...@@ -245,5 +245,5 @@ static int __init sirfsoc_prima2_timer_init(struct device_node *np) ...@@ -245,5 +245,5 @@ static int __init sirfsoc_prima2_timer_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, TIMER_OF_DECLARE(sirfsoc_prima2_timer,
"sirf,prima2-tick", sirfsoc_prima2_timer_init); "sirf,prima2-tick", sirfsoc_prima2_timer_init);
...@@ -19,20 +19,20 @@ ...@@ -19,20 +19,20 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/clocksource.h> #include <linux/clocksource.h>
extern struct of_device_id __clksrc_of_table[]; extern struct of_device_id __timer_of_table[];
static const struct of_device_id __clksrc_of_table_sentinel static const struct of_device_id __timer_of_table_sentinel
__used __section(__clksrc_of_table_end); __used __section(__timer_of_table_end);
void __init clocksource_probe(void) void __init timer_probe(void)
{ {
struct device_node *np; struct device_node *np;
const struct of_device_id *match; const struct of_device_id *match;
of_init_fn_1_ret init_func_ret; of_init_fn_1_ret init_func_ret;
unsigned clocksources = 0; unsigned timers = 0;
int ret; int ret;
for_each_matching_node_and_match(np, __clksrc_of_table, &match) { for_each_matching_node_and_match(np, __timer_of_table, &match) {
if (!of_device_is_available(np)) if (!of_device_is_available(np))
continue; continue;
...@@ -45,11 +45,11 @@ void __init clocksource_probe(void) ...@@ -45,11 +45,11 @@ void __init clocksource_probe(void)
continue; continue;
} }
clocksources++; timers++;
} }
clocksources += acpi_probe_device_table(clksrc); timers += acpi_probe_device_table(timer);
if (!clocksources) if (!timers)
pr_crit("%s: no matching clocksources found\n", __func__); pr_crit("%s: no matching timers found\n", __func__);
} }
...@@ -287,7 +287,7 @@ static int __init sp804_of_init(struct device_node *np) ...@@ -287,7 +287,7 @@ static int __init sp804_of_init(struct device_node *np)
iounmap(base); iounmap(base);
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
static int __init integrator_cp_of_init(struct device_node *np) static int __init integrator_cp_of_init(struct device_node *np)
{ {
...@@ -335,4 +335,4 @@ static int __init integrator_cp_of_init(struct device_node *np) ...@@ -335,4 +335,4 @@ static int __init integrator_cp_of_init(struct device_node *np)
iounmap(base); iounmap(base);
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init); TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
...@@ -187,4 +187,4 @@ static int __init stm32_clockevent_init(struct device_node *np) ...@@ -187,4 +187,4 @@ static int __init stm32_clockevent_init(struct device_node *np)
return ret; return ret;
} }
CLOCKSOURCE_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init);
...@@ -358,7 +358,7 @@ static int __init sun5i_timer_init(struct device_node *node) ...@@ -358,7 +358,7 @@ static int __init sun5i_timer_init(struct device_node *node)
return sun5i_setup_clockevent(node, timer_base, clk, irq); return sun5i_setup_clockevent(node, timer_base, clk, irq);
} }
CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer", TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
sun5i_timer_init); sun5i_timer_init);
CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer", TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
sun5i_timer_init); sun5i_timer_init);
...@@ -124,5 +124,5 @@ static int __init ti_32k_timer_init(struct device_node *np) ...@@ -124,5 +124,5 @@ static int __init ti_32k_timer_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k", TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
ti_32k_timer_init); ti_32k_timer_init);
...@@ -458,5 +458,5 @@ static int __init u300_timer_init_of(struct device_node *np) ...@@ -458,5 +458,5 @@ static int __init u300_timer_init_of(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer", TIMER_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
u300_timer_init_of); u300_timer_init_of);
...@@ -38,7 +38,7 @@ static int __init versatile_sched_clock_init(struct device_node *node) ...@@ -38,7 +38,7 @@ static int __init versatile_sched_clock_init(struct device_node *node)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(vexpress, "arm,vexpress-sysreg", TIMER_OF_DECLARE(vexpress, "arm,vexpress-sysreg",
versatile_sched_clock_init); versatile_sched_clock_init);
CLOCKSOURCE_OF_DECLARE(versatile, "arm,versatile-sysreg", TIMER_OF_DECLARE(versatile, "arm,versatile-sysreg",
versatile_sched_clock_init); versatile_sched_clock_init);
...@@ -201,4 +201,4 @@ static int __init pit_timer_init(struct device_node *np) ...@@ -201,4 +201,4 @@ static int __init pit_timer_init(struct device_node *np)
return pit_clockevent_init(clk_rate, irq); return pit_clockevent_init(clk_rate, irq);
} }
CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init); TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
...@@ -165,4 +165,4 @@ static int __init vt8500_timer_init(struct device_node *np) ...@@ -165,4 +165,4 @@ static int __init vt8500_timer_init(struct device_node *np)
return 0; return 0;
} }
CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init); TIMER_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);
...@@ -215,4 +215,4 @@ static int __init zevio_timer_init(struct device_node *node) ...@@ -215,4 +215,4 @@ static int __init zevio_timer_init(struct device_node *node)
return zevio_timer_add(node); return zevio_timer_add(node);
} }
CLOCKSOURCE_OF_DECLARE(zevio_timer, "lsi,zevio-timer", zevio_timer_init); TIMER_OF_DECLARE(zevio_timer, "lsi,zevio-timer", zevio_timer_init);
...@@ -172,8 +172,7 @@ ...@@ -172,8 +172,7 @@
KEEP(*(__##name##_of_table)) \ KEEP(*(__##name##_of_table)) \
KEEP(*(__##name##_of_table_end)) KEEP(*(__##name##_of_table_end))
#define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) #define TIMER_OF_TABLES() OF_TABLE(CONFIG_TIMER_OF, timer)
#define CLKEVT_OF_TABLES() OF_TABLE(CONFIG_CLKEVT_OF, clkevt)
#define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip)
#define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk) #define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk)
#define IOMMU_OF_TABLES() OF_TABLE(CONFIG_OF_IOMMU, iommu) #define IOMMU_OF_TABLES() OF_TABLE(CONFIG_OF_IOMMU, iommu)
...@@ -557,15 +556,15 @@ ...@@ -557,15 +556,15 @@
MEM_DISCARD(init.rodata) \ MEM_DISCARD(init.rodata) \
CLK_OF_TABLES() \ CLK_OF_TABLES() \
RESERVEDMEM_OF_TABLES() \ RESERVEDMEM_OF_TABLES() \
CLKSRC_OF_TABLES() \ TIMER_OF_TABLES() \
CLKEVT_OF_TABLES() \
IOMMU_OF_TABLES() \ IOMMU_OF_TABLES() \
CPU_METHOD_OF_TABLES() \ CPU_METHOD_OF_TABLES() \
CPUIDLE_METHOD_OF_TABLES() \ CPUIDLE_METHOD_OF_TABLES() \
KERNEL_DTB() \ KERNEL_DTB() \
IRQCHIP_OF_MATCH_TABLE() \ IRQCHIP_OF_MATCH_TABLE() \
ACPI_PROBE_TABLE(irqchip) \ ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(clksrc) \ ACPI_PROBE_TABLE(timer) \
ACPI_PROBE_TABLE(iort) \
EARLYCON_TABLE() EARLYCON_TABLE()
#define INIT_TEXT \ #define INIT_TEXT \
......
...@@ -223,13 +223,4 @@ static inline void tick_setup_hrtimer_broadcast(void) { } ...@@ -223,13 +223,4 @@ static inline void tick_setup_hrtimer_broadcast(void) { }
#endif /* !CONFIG_GENERIC_CLOCKEVENTS */ #endif /* !CONFIG_GENERIC_CLOCKEVENTS */
#define CLOCKEVENT_OF_DECLARE(name, compat, fn) \
OF_DECLARE_1_RET(clkevt, name, compat, fn)
#ifdef CONFIG_CLKEVT_PROBE
extern int clockevent_probe(void);
#else
static inline int clockevent_probe(void) { return 0; }
#endif
#endif /* _LINUX_CLOCKCHIPS_H */ #endif /* _LINUX_CLOCKCHIPS_H */
...@@ -249,16 +249,19 @@ extern int clocksource_mmio_init(void __iomem *, const char *, ...@@ -249,16 +249,19 @@ extern int clocksource_mmio_init(void __iomem *, const char *,
extern int clocksource_i8253_init(void); extern int clocksource_i8253_init(void);
#define TIMER_OF_DECLARE(name, compat, fn) \
OF_DECLARE_1_RET(timer, name, compat, fn)
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
OF_DECLARE_1_RET(clksrc, name, compat, fn) TIMER_OF_DECLARE(name, compat, fn)
#ifdef CONFIG_CLKSRC_PROBE #ifdef CONFIG_TIMER_PROBE
extern void clocksource_probe(void); extern void timer_probe(void);
#else #else
static inline void clocksource_probe(void) {} static inline void timer_probe(void) {}
#endif #endif
#define CLOCKSOURCE_ACPI_DECLARE(name, table_id, fn) \ #define TIMER_ACPI_DECLARE(name, table_id, fn) \
ACPI_DECLARE_PROBE_ENTRY(clksrc, name, table_id, 0, NULL, 0, fn) ACPI_DECLARE_PROBE_ENTRY(timer, name, table_id, 0, NULL, 0, fn)
#endif /* _LINUX_CLOCKSOURCE_H */ #endif /* _LINUX_CLOCKSOURCE_H */
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