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Commit e867f429 authored by Akash Asthana's avatar Akash Asthana Committed by Bjorn Andersson
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arm64: dts: sc7180: Add interconnect for QUP and QSPI 

Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
Signed-off-by: default avatarAkash Asthana <akashast@codeaurora.org>
Link: https://lore.kernel.org/r/1592908737-7068-9-git-send-email-akashast@codeaurora.orgSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 5e09bc51
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arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ e867f429
...@@ -547,6 +547,8 @@ qupv3_id_0: geniqup@8c0000 { ...@@ -547,6 +547,8 @@ qupv3_id_0: geniqup@8c0000 {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
iommus = <&apps_smmu 0x43 0x0>; iommus = <&apps_smmu 0x43 0x0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
interconnect-names = "qup-core";
status = "disabled"; status = "disabled";
i2c0: i2c@880000 { i2c0: i2c@880000 {
...@@ -559,6 +561,11 @@ i2c0: i2c@880000 { ...@@ -559,6 +561,11 @@ i2c0: i2c@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -572,6 +579,9 @@ spi0: spi@880000 { ...@@ -572,6 +579,9 @@ spi0: spi@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -583,6 +593,9 @@ uart0: serial@880000 { ...@@ -583,6 +593,9 @@ uart0: serial@880000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>; pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -596,6 +609,11 @@ i2c1: i2c@884000 { ...@@ -596,6 +609,11 @@ i2c1: i2c@884000 {
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -609,6 +627,9 @@ spi1: spi@884000 { ...@@ -609,6 +627,9 @@ spi1: spi@884000 {
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -620,6 +641,9 @@ uart1: serial@884000 { ...@@ -620,6 +641,9 @@ uart1: serial@884000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>; pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -633,6 +657,11 @@ i2c2: i2c@888000 { ...@@ -633,6 +657,11 @@ i2c2: i2c@888000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -644,6 +673,9 @@ uart2: serial@888000 { ...@@ -644,6 +673,9 @@ uart2: serial@888000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>; pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -657,6 +689,11 @@ i2c3: i2c@88c000 { ...@@ -657,6 +689,11 @@ i2c3: i2c@88c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -670,6 +707,9 @@ spi3: spi@88c000 { ...@@ -670,6 +707,9 @@ spi3: spi@88c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -681,6 +721,9 @@ uart3: serial@88c000 { ...@@ -681,6 +721,9 @@ uart3: serial@88c000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>; pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -694,6 +737,11 @@ i2c4: i2c@890000 { ...@@ -694,6 +737,11 @@ i2c4: i2c@890000 {
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -705,6 +753,9 @@ uart4: serial@890000 { ...@@ -705,6 +753,9 @@ uart4: serial@890000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>; pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -718,6 +769,11 @@ i2c5: i2c@894000 { ...@@ -718,6 +769,11 @@ i2c5: i2c@894000 {
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -731,6 +787,9 @@ spi5: spi@894000 { ...@@ -731,6 +787,9 @@ spi5: spi@894000 {
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -742,6 +801,9 @@ uart5: serial@894000 { ...@@ -742,6 +801,9 @@ uart5: serial@894000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>; pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -756,6 +818,8 @@ qupv3_id_1: geniqup@ac0000 { ...@@ -756,6 +818,8 @@ qupv3_id_1: geniqup@ac0000 {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
iommus = <&apps_smmu 0x4c3 0x0>; iommus = <&apps_smmu 0x4c3 0x0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
interconnect-names = "qup-core";
status = "disabled"; status = "disabled";
i2c6: i2c@a80000 { i2c6: i2c@a80000 {
...@@ -768,6 +832,11 @@ i2c6: i2c@a80000 { ...@@ -768,6 +832,11 @@ i2c6: i2c@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -781,6 +850,9 @@ spi6: spi@a80000 { ...@@ -781,6 +850,9 @@ spi6: spi@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -792,6 +864,9 @@ uart6: serial@a80000 { ...@@ -792,6 +864,9 @@ uart6: serial@a80000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>; pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -805,6 +880,11 @@ i2c7: i2c@a84000 { ...@@ -805,6 +880,11 @@ i2c7: i2c@a84000 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -816,6 +896,9 @@ uart7: serial@a84000 { ...@@ -816,6 +896,9 @@ uart7: serial@a84000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>; pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -829,6 +912,11 @@ i2c8: i2c@a88000 { ...@@ -829,6 +912,11 @@ i2c8: i2c@a88000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -842,6 +930,9 @@ spi8: spi@a88000 { ...@@ -842,6 +930,9 @@ spi8: spi@a88000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -853,6 +944,9 @@ uart8: serial@a88000 { ...@@ -853,6 +944,9 @@ uart8: serial@a88000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>; pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -866,6 +960,11 @@ i2c9: i2c@a8c000 { ...@@ -866,6 +960,11 @@ i2c9: i2c@a8c000 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -877,6 +976,9 @@ uart9: serial@a8c000 { ...@@ -877,6 +976,9 @@ uart9: serial@a8c000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>; pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -890,6 +992,11 @@ i2c10: i2c@a90000 { ...@@ -890,6 +992,11 @@ i2c10: i2c@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -903,6 +1010,9 @@ spi10: spi@a90000 { ...@@ -903,6 +1010,9 @@ spi10: spi@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -914,6 +1024,9 @@ uart10: serial@a90000 { ...@@ -914,6 +1024,9 @@ uart10: serial@a90000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>; pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -927,6 +1040,11 @@ i2c11: i2c@a94000 { ...@@ -927,6 +1040,11 @@ i2c11: i2c@a94000 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled"; status = "disabled";
}; };
...@@ -940,6 +1058,9 @@ spi11: spi@a94000 { ...@@ -940,6 +1058,9 @@ spi11: spi@a94000 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
...@@ -951,6 +1072,9 @@ uart11: serial@a94000 { ...@@ -951,6 +1072,9 @@ uart11: serial@a94000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>; pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -2132,6 +2256,9 @@ qspi: spi@88dc000 { ...@@ -2132,6 +2256,9 @@ qspi: spi@88dc000 {
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>; <&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core"; clock-names = "iface", "core";
interconnects = <&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_QSPI_0>;
interconnect-names = "qspi-config";
status = "disabled"; status = "disabled";
}; };
......
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