Skip to content

L
linux
Commit e918a18d authored by Michael Turquette's avatar Michael Turquette
Browse files
Options

Merge branch 'clk-meson-gxbb' into clk-next

parents 54fe0791 19a2a85d
Expand all Show whitespace changes
Inline Side-by-side
Showing with 506 additions and 121 deletions
drivers/clk/meson/Makefile
View file @ e918a18d
......@@ -3,5 +3,5 @@
#
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
drivers/clk/meson/clkc.h
View file @ e918a18d
......@@ -98,7 +98,7 @@ struct meson_clk_mpll {
};
#define MESON_GATE(_name, _reg, _bit) \
struct clk_gate gxbb_##_name = { \
struct clk_gate _name = { \
.reg = (void __iomem *) _reg, \
.bit_idx = (_bit), \
.lock = &clk_lock, \
......
drivers/clk/meson/gxbb.c
View file @ e918a18d
......@@ -565,93 +565,93 @@ static struct clk_gate gxbb_clk81 = {
};
/* Everything Else (EE) domain gates */
static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);
static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);
static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);
static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);
static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);
static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);
static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);
static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);
static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
static MESON_GATE(emmc_a, HHI_GCLK_MPEG0, 24);
static MESON_GATE(emmc_b, HHI_GCLK_MPEG0, 25);
static MESON_GATE(emmc_c, HHI_GCLK_MPEG0, 26);
static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);
static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);
static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);
static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);
static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);
static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);
static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);
static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);
static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);
static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);
static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);
static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);
static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);
static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);
static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);
static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);
static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);
static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);
static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);
static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);
static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);
static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);
static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);
static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);
static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);
static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);
static MESON_GATE(edp, HHI_GCLK_OTHER, 31);
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
/* Always On (AO) domain gates */
static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);
static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);
static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
/* Array of all clocks provided by this provider */
......
drivers/clk/meson/gxbb.h
View file @ e918a18d
......@@ -170,11 +170,11 @@
*/
#define CLKID_SYS_PLL 0
/* CLKID_CPUCLK */
#define CLKID_HDMI_PLL 2
/* CLKID_HDMI_PLL */
#define CLKID_FIXED_PLL 3
/* CLKID_FCLK_DIV2 */
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
/* CLKID_FCLK_DIV3 */
/* CLKID_FCLK_DIV4 */
#define CLKID_FCLK_DIV5 7
#define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9
......
drivers/clk/meson/meson8b.h 0 → 100644
View file @ e918a18d
/*
* Copyright (c) 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* Copyright (c) 2016 BayLibre, Inc.
* Michael Turquette <mturquette@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __MESON8B_H
#define __MESON8B_H
/*
* Clock controller register offsets
*
* Register offsets from the HardKernel[0] data sheet are listed in comment
* blocks below. Those offsets must be multiplied by 4 before adding them to
* the base address to get the right value
*
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
*/
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
/*
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
* Migrate them out of this header and into the DT header file when they need
* to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
*/
/* CLKID_UNUSED */
/* CLKID_XTAL */
/* CLKID_PLL_FIXED */
/* CLKID_PLL_VID */
/* CLKID_PLL_SYS */
/* CLKID_FCLK_DIV2 */
/* CLKID_FCLK_DIV3 */
/* CLKID_FCLK_DIV4 */
/* CLKID_FCLK_DIV5 */
/* CLKID_FCLK_DIV7 */
/* CLKID_CLK81 */
/* CLKID_MALI */
/* CLKID_CPUCLK */
/* CLKID_ZERO */
/* CLKID_MPEG_SEL */
/* CLKID_MPEG_DIV */
#define CLKID_DDR 16
#define CLKID_DOS 17
#define CLKID_ISA 18
#define CLKID_PL301 19
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
#define CLKID_SDHC 27
#define CLKID_STREAM 28
#define CLKID_ASYNC_FIFO 29
#define CLKID_SDIO 30
#define CLKID_ABUF 31
#define CLKID_HIU_IFACE 32
#define CLKID_ASSIST_MISC 33
#define CLKID_SPI 34
#define CLKID_I2S_SPDIF 35
#define CLKID_ETH 36
#define CLKID_DEMUX 37
#define CLKID_AIU_GLUE 38
#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40
#define CLKID_AMCLK 41
#define CLKID_AIFIFO2 42
#define CLKID_MIXER 43
#define CLKID_MIXER_IFACE 44
#define CLKID_ADC 45
#define CLKID_BLKMV 46
#define CLKID_AIU 47
#define CLKID_UART1 48
#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_RESET 52
#define CLKID_NAND 53
#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
#define CLKID_VDIN1 56
#define CLKID_AHB_ARB0 57
#define CLKID_EFUSE 58
#define CLKID_BOOT_ROM 59
#define CLKID_AHB_DATA_BUS 60
#define CLKID_AHB_CTRL_BUS 61
#define CLKID_HDMI_INTR_SYNC 62
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
#define CLKID_SANA 69
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A9 72
#define CLKID_VCLK2_VENCI0 73
#define CLKID_VCLK2_VENCI1 74
#define CLKID_VCLK2_VENCP0 75
#define CLKID_VCLK2_VENCP1 76
#define CLKID_GCLK_VENCI_INT 77
#define CLKID_GCLK_VENCP_INT 78
#define CLKID_DAC_CLK 79
#define CLKID_AOCLK_GATE 80
#define CLKID_IEC958_GATE 81
#define CLKID_ENC480P 82
#define CLKID_RNG1 83
#define CLKID_GCLK_VENCL_INT 84
#define CLKID_VCLK2_VENCLMCC 85
#define CLKID_VCLK2_VENCL 86
#define CLKID_VCLK2_OTHER 87
#define CLKID_EDP 88
#define CLKID_AO_MEDIA_CPU 89
#define CLKID_AO_AHB_SRAM 90
#define CLKID_AO_AHB_BUS 91
#define CLKID_AO_IFACE 92
#define CLK_NR_CLKS 93
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/meson8b-clkc.h>
#endif /* __MESON8B_H */
include/dt-bindings/clock/gxbb-clkc.h
View file @ e918a18d
......@@ -6,7 +6,10 @@
#define __GXBB_CLKC_H
#define CLKID_CPUCLK 1
#define CLKID_HDMI_PLL 2
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
#define CLKID_CLK81 12
#define CLKID_ETH 36
#define CLKID_SD_EMMC_A 94
......
include/dt-bindings/clock/meson8b-clkc.h
View file @ e918a18d
......@@ -22,6 +22,4 @@
#define CLKID_MPEG_SEL 14
#define CLKID_MPEG_DIV 15
#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1)
#endif /* __MESON8B_CLKC_H */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7