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Commit e9f5f1e4 authored by Tony Lindgren's avatar Tony Lindgren
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ARM: OMAP2+: Remove legacy mux code 

All the boards booting with device tree use
drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux,
so let's move the related Kconfig options from plat-omap
to mach-omap1.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent b4281455
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Showing with 27 additions and 4098 deletions
arch/arm/mach-omap1/Kconfig
View file @ e9f5f1e4
...@@ -31,6 +31,32 @@ config ARCH_OMAP16XX ...@@ -31,6 +31,32 @@ config ARCH_OMAP16XX
select ARCH_OMAP_OTG select ARCH_OMAP_OTG
select CPU_ARM926T select CPU_ARM926T
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
sets the multiplexing correctly, say N. Otherwise, or if unsure,
say Y.
config OMAP_MUX_DEBUG
bool "Multiplexing debug output"
depends on OMAP_MUX
help
Makes the multiplexing functions print out a lot of debug info.
This is useful if you want to find out the correct values of the
multiplexing registers.
config OMAP_MUX_WARNINGS
bool "Warn about pins the bootloader didn't set up"
depends on OMAP_MUX
default y
help
Choose Y here to warn whenever driver initialization logic needs
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
comment "OMAP Board Type" comment "OMAP Board Type"
depends on ARCH_OMAP1 depends on ARCH_OMAP1
......
arch/arm/mach-omap2/Makefile
View file @ e9f5f1e4
...@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \ ...@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-omap/include -I$(srctree)/arch/arm/plat-omap/include
# Common support # Common support
obj-y := id.o io.o control.o mux.o devices.o fb.o timer.o pm.o \ obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o drm.o omap_device.o omap-headsmp.o sram.o drm.o
...@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o ...@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
# SMS/SDRC # SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
......
arch/arm/mach-omap2/common.h
View file @ e9f5f1e4
...@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void) ...@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void)
} }
#endif #endif
#ifdef CONFIG_OMAP_MUX
int omap_mux_late_init(void);
#else
static inline int omap_mux_late_init(void)
{
return 0;
}
#endif
extern void omap2_init_common_infrastructure(void); extern void omap2_init_common_infrastructure(void);
extern void omap_init_time(void); extern void omap_init_time(void);
......
arch/arm/mach-omap2/dss-common.c
View file @ e9f5f1e4
...@@ -32,6 +32,5 @@ ...@@ -32,6 +32,5 @@
#include "soc.h" #include "soc.h"
#include "dss-common.h" #include "dss-common.h"
#include "mux.h"
#include "display.h" #include "display.h"
arch/arm/mach-omap2/hsmmc.c
View file @ e9f5f1e4
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
#include "omap_device.h" #include "omap_device.h"
#include "omap-pm.h" #include "omap-pm.h"
#include "mux.h"
#include "hsmmc.h" #include "hsmmc.h"
#include "control.h" #include "control.h"
...@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd) ...@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
return 0; return 0;
} }
static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
*mmc_controller, int controller_nr)
{
if (gpio_is_valid(mmc_controller->gpio_cd) &&
(mmc_controller->gpio_cd < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_cd,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->gpio_cod) &&
(mmc_controller->gpio_cod < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_cod,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->gpio_wp) &&
(mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7
* need to be muxed in the board-*.c files
*/
if (mmc_controller->caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_hsmmc_platform_data *mmc) struct omap_hsmmc_platform_data *mmc)
{ {
...@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, ...@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
if (res < 0) if (res < 0)
goto free_mmc; goto free_mmc;
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc"; name = "omap_hsmmc";
res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
"mmc%d", ctrl_nr); "mmc%d", ctrl_nr);
......
arch/arm/mach-omap2/io.c
View file @ e9f5f1e4
...@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void) ...@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void)
static void __init __maybe_unused omap_common_late_init(void) static void __init __maybe_unused omap_common_late_init(void)
{ {
omap_mux_late_init();
omap2_common_pm_late_init(); omap2_common_pm_late_init();
omap_soc_device_init(); omap_soc_device_init();
} }
......
arch/arm/mach-omap2/msdi.c
View file @ e9f5f1e4
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#include "control.h" #include "control.h"
#include "omap_hwmod.h" #include "omap_hwmod.h"
#include "omap_device.h" #include "omap_device.h"
#include "mux.h"
#include "mmc.h" #include "mmc.h"
/* /*
......
arch/arm/mach-omap2/mux.c deleted 100644 → 0
View file @ b4281455
/*
* linux/arch/arm/mach-omap2/mux.c
*
* OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
*
* Copyright (C) 2004 - 2010 Texas Instruments Inc.
* Copyright (C) 2003 - 2008 Nokia Corporation
*
* Written by Tony Lindgren
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/uaccess.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include "omap_hwmod.h"
#include "soc.h"
#include "control.h"
#include "mux.h"
#include "prm.h"
#include "common.h"
#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
#define OMAP_MUX_BASE_SZ 0x5ca
struct omap_mux_entry {
struct omap_mux mux;
struct list_head node;
};
static LIST_HEAD(mux_partitions);
static DEFINE_MUTEX(muxmode_mutex);
struct omap_mux_partition *omap_mux_get(const char *name)
{
struct omap_mux_partition *partition;
list_for_each_entry(partition, &mux_partitions, node) {
if (!strcmp(name, partition->name))
return partition;
}
return NULL;
}
u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
return readb_relaxed(partition->base + reg);
else
return readw_relaxed(partition->base + reg);
}
void omap_mux_write(struct omap_mux_partition *partition, u16 val,
u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
writeb_relaxed(val, partition->base + reg);
else
writew_relaxed(val, partition->base + reg);
}
void omap_mux_write_array(struct omap_mux_partition *partition,
struct omap_board_mux *board_mux)
{
if (!board_mux)
return;
while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
omap_mux_write(partition, board_mux->value,
board_mux->reg_offset);
board_mux++;
}
}
#ifdef CONFIG_OMAP_MUX
static char *omap_mux_options;
static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
int gpio, int val)
{
struct omap_mux_entry *e;
struct omap_mux *gpio_mux = NULL;
u16 old_mode;
u16 mux_mode;
int found = 0;
struct list_head *muxmodes = &partition->muxmodes;
if (!gpio)
return -EINVAL;
list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
if (gpio == m->gpio) {
gpio_mux = m;
found++;
}
}
if (found == 0) {
pr_err("%s: Could not set gpio%i\n", __func__, gpio);
return -ENODEV;
}
if (found > 1) {
pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
found, gpio);
return -EINVAL;
}
old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
mux_mode |= partition->gpio;
pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
return 0;
}
int __init omap_mux_init_gpio(int gpio, int val)
{
struct omap_mux_partition *partition;
int ret;
list_for_each_entry(partition, &mux_partitions, node) {
ret = _omap_mux_init_gpio(partition, gpio, val);
if (!ret)
return ret;
}
return -ENODEV;
}
static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
const char *muxname,
struct omap_mux **found_mux)
{
struct omap_mux *mux = NULL;
struct omap_mux_entry *e;
const char *mode_name;
int found = 0, found_mode = 0, mode0_len = 0;
struct list_head *muxmodes = &partition->muxmodes;
mode_name = strchr(muxname, '.');
if (mode_name) {
mode0_len = strlen(muxname) - strlen(mode_name);
mode_name++;
} else {
mode_name = muxname;
}
list_for_each_entry(e, muxmodes, node) {
char *m0_entry;
int i;
mux = &e->mux;
m0_entry = mux->muxnames[0];
/* First check for full name in mode0.muxmode format */
if (mode0_len)
if (strncmp(muxname, m0_entry, mode0_len) ||
(strlen(m0_entry) != mode0_len))
continue;
/* Then check for muxmode only */
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
char *mode_cur = mux->muxnames[i];
if (!mode_cur)
continue;
if (!strcmp(mode_name, mode_cur)) {
*found_mux = mux;
found++;
found_mode = i;
}
}
}
if (found == 1) {
return found_mode;
}
if (found > 1) {
pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
found, muxname);
return -EINVAL;
}
return -ENODEV;
}
int __init omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux)
{
struct omap_mux_partition *partition;
list_for_each_entry(partition, &mux_partitions, node) {
struct omap_mux *mux = NULL;
int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
if (mux_mode < 0)
continue;
*found_partition = partition;
*found_mux = mux;
return mux_mode;
}
pr_err("%s: Could not find signal %s\n", __func__, muxname);
return -ENODEV;
}
int __init omap_mux_init_signal(const char *muxname, int val)
{
struct omap_mux_partition *partition = NULL;
struct omap_mux *mux = NULL;
u16 old_mode;
int mux_mode;
mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
if (mux_mode < 0 || !mux)
return mux_mode;
old_mode = omap_mux_read(partition, mux->reg_offset);
mux_mode |= val;
pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
__func__, muxname, old_mode, mux_mode);
omap_mux_write(partition, mux_mode, mux->reg_offset);
return 0;
}
struct omap_hwmod_mux_info * __init
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
{
struct omap_hwmod_mux_info *hmux;
int i, nr_pads_dynamic = 0;
if (!bpads || nr_pads < 1)
return NULL;
hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
if (!hmux)
goto err1;
hmux->nr_pads = nr_pads;
hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
nr_pads, GFP_KERNEL);
if (!hmux->pads)
goto err2;
for (i = 0; i < hmux->nr_pads; i++) {
struct omap_mux_partition *partition;
struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
struct omap_mux *mux;
int mux_mode;
mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
if (mux_mode < 0)
goto err3;
if (!pad->partition)
pad->partition = partition;
if (!pad->mux)
pad->mux = mux;
pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
if (!pad->name) {
int j;
for (j = i - 1; j >= 0; j--)
kfree(hmux->pads[j].name);
goto err3;
}
strcpy(pad->name, bpad->name);
pad->flags = bpad->flags;
pad->enable = bpad->enable;
pad->idle = bpad->idle;
pad->off = bpad->off;
if (pad->flags &
(OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
nr_pads_dynamic++;
pr_debug("%s: Initialized %s\n", __func__, pad->name);
}
if (!nr_pads_dynamic)
return hmux;
/*
* Add pads that need dynamic muxing into a separate list
*/
hmux->nr_pads_dynamic = nr_pads_dynamic;
hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
nr_pads_dynamic, GFP_KERNEL);
if (!hmux->pads_dynamic) {
pr_err("%s: Could not allocate dynamic pads\n", __func__);
return hmux;
}
nr_pads_dynamic = 0;
for (i = 0; i < hmux->nr_pads; i++) {
struct omap_device_pad *pad = &hmux->pads[i];
if (pad->flags &
(OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
pr_debug("%s: pad %s tagged dynamic\n",
__func__, pad->name);
hmux->pads_dynamic[nr_pads_dynamic] = pad;
nr_pads_dynamic++;
}
}
return hmux;
err3:
kfree(hmux->pads);
err2:
kfree(hmux);
err1:
pr_err("%s: Could not allocate device mux entry\n", __func__);
return NULL;
}
/**
* omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
* @hmux: Pads for a hwmod
* @mpu_irqs: MPU irq array for a hwmod
*
* Scans the wakeup status of pads for a single hwmod. If an irq
* array is defined for this mux, the parser will call the registered
* ISRs for corresponding pads, otherwise the parser will stop at the
* first wakeup active pad and return. Returns true if there is a
* pending and non-served wakeup event for the mux, otherwise false.
*/
static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
struct omap_hwmod_irq_info *mpu_irqs)
{
int i, irq;
unsigned int val;
u32 handled_irqs = 0;
for (i = 0; i < hmux->nr_pads_dynamic; i++) {
struct omap_device_pad *pad = hmux->pads_dynamic[i];
if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
!(pad->idle & OMAP_WAKEUP_EN))
continue;
val = omap_mux_read(pad->partition, pad->mux->reg_offset);
if (!(val & OMAP_WAKEUP_EVENT))
continue;
if (!hmux->irqs)
return true;
irq = hmux->irqs[i];
/* make sure we only handle each irq once */
if (handled_irqs & 1 << irq)
continue;
handled_irqs |= 1 << irq;
generic_handle_irq(mpu_irqs[irq].irq);
}
return false;
}
/**
* _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
*
* Checks a single hwmod for every wakeup capable pad to see if there is an
* active wakeup event. If this is the case, call the corresponding ISR.
*/
static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
{
if (!oh->mux || !oh->mux->enabled)
return 0;
if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
generic_handle_irq(oh->mpu_irqs[0].irq);
return 0;
}
/**
* omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
*
* Calls a function for each registered omap_hwmod to check
* pad wakeup statuses.
*/
static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
{
omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
return IRQ_HANDLED;
}
/* Assumes the calling function takes care of locking */
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
int i;
/* Runtime idling of dynamic pads */
if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
for (i = 0; i < hmux->nr_pads_dynamic; i++) {
struct omap_device_pad *pad = hmux->pads_dynamic[i];
int val = -EINVAL;
val = pad->idle;
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
}
return;
}
/* Runtime enabling of dynamic pads */
if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
&& hmux->enabled) {
for (i = 0; i < hmux->nr_pads_dynamic; i++) {
struct omap_device_pad *pad = hmux->pads_dynamic[i];
int val = -EINVAL;
val = pad->enable;
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
}
return;
}
/* Enabling or disabling of all pads */
for (i = 0; i < hmux->nr_pads; i++) {
struct omap_device_pad *pad = &hmux->pads[i];
int flags, val = -EINVAL;
flags = pad->flags;
switch (state) {
case _HWMOD_STATE_ENABLED:
val = pad->enable;
pr_debug("%s: Enabling %s %x\n", __func__,
pad->name, val);
break;
case _HWMOD_STATE_DISABLED:
/* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
if (flags & OMAP_DEVICE_PAD_REMUX)
val = pad->off;
else
val = OMAP_MUX_MODE7;
pr_debug("%s: Disabling %s %x\n", __func__,
pad->name, val);
break;
default:
/* Nothing to be done */
break;
}
if (val >= 0) {
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
pad->flags = flags;
}
}
if (state == _HWMOD_STATE_ENABLED)
hmux->enabled = true;
else
hmux->enabled = false;
}
#ifdef CONFIG_DEBUG_FS
#define OMAP_MUX_MAX_NR_FLAGS 10
#define OMAP_MUX_TEST_FLAG(val, mask) \
if (((val) & (mask)) == (mask)) { \
i++; \
flags[i] = #mask; \
}
/* REVISIT: Add checking for non-optimal mux settings */
static inline void omap_mux_decode(struct seq_file *s, u16 val)
{
char *flags[OMAP_MUX_MAX_NR_FLAGS];
char mode[sizeof("OMAP_MUX_MODE") + 1];
int i = -1;
sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
i++;
flags[i] = mode;
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
if (val & OMAP_OFF_EN) {
if (!(val & OMAP_OFFOUT_EN)) {
if (!(val & OMAP_OFF_PULL_UP)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_INPUT_PULLDOWN);
} else {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_INPUT_PULLUP);
}
} else {
if (!(val & OMAP_OFFOUT_VAL)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_OUTPUT_LOW);
} else {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_OUTPUT_HIGH);
}
}
}
if (val & OMAP_INPUT_EN) {
if (val & OMAP_PULL_ENA) {
if (!(val & OMAP_PULL_UP)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_INPUT_PULLDOWN);
} else {
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
}
} else {
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
}
} else {
i++;
flags[i] = "OMAP_PIN_OUTPUT";
}
do {
seq_printf(s, "%s", flags[i]);
if (i > 0)
seq_puts(s, " | ");
} while (i-- > 0);
}
#define OMAP_MUX_DEFNAME_LEN 32
static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
{
struct omap_mux_partition *partition = s->private;
struct omap_mux_entry *e;
u8 omap_gen = omap_rev() >> 28;
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
char m0_def[OMAP_MUX_DEFNAME_LEN];
char *m0_name = m->muxnames[0];
u16 val;
int i, mode;
if (!m0_name)
continue;
/* REVISIT: Needs to be updated if mode0 names get longer */
for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
if (m0_name[i] == '\0') {
m0_def[i] = m0_name[i];
break;
}
m0_def[i] = toupper(m0_name[i]);
}
val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
if (mode != 0)
seq_printf(s, "/* %s */\n", m->muxnames[mode]);
/*
* XXX: Might be revisited to support differences across
* same OMAP generation.
*/
seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
omap_mux_decode(s, val);
seq_puts(s, "),\n");
}
return 0;
}
static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_mux_dbg_board_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_board_fops = {
.open = omap_mux_dbg_board_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
{
struct omap_mux_partition *partition;
list_for_each_entry(partition, &mux_partitions, node) {
struct list_head *muxmodes = &partition->muxmodes;
struct omap_mux_entry *e;
list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m == mux)
return partition;
}
}
return NULL;
}
static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
{
struct omap_mux *m = s->private;
struct omap_mux_partition *partition;
const char *none = "NA";
u16 val;
int mode;
partition = omap_mux_get_partition(m);
if (!partition)
return 0;
val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
m->muxnames[0], m->muxnames[mode],
partition->phys + m->reg_offset, m->reg_offset, val,
m->balls[0] ? m->balls[0] : none,
m->balls[1] ? m->balls[1] : none);
seq_puts(s, "mode: ");
omap_mux_decode(s, val);
seq_putc(s, '\n');
seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
m->muxnames[0] ? m->muxnames[0] : none,
m->muxnames[1] ? m->muxnames[1] : none,
m->muxnames[2] ? m->muxnames[2] : none,
m->muxnames[3] ? m->muxnames[3] : none,
m->muxnames[4] ? m->muxnames[4] : none,
m->muxnames[5] ? m->muxnames[5] : none,
m->muxnames[6] ? m->muxnames[6] : none,
m->muxnames[7] ? m->muxnames[7] : none);
return 0;
}
#define OMAP_MUX_MAX_ARG_CHAR 7
static ssize_t omap_mux_dbg_signal_write(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct seq_file *seqf;
struct omap_mux *m;
u16 val;
int ret;
struct omap_mux_partition *partition;
if (count > OMAP_MUX_MAX_ARG_CHAR)
return -EINVAL;
ret = kstrtou16_from_user(user_buf, count, 0x10, &val);
if (ret < 0)
return ret;
seqf = file->private_data;
m = seqf->private;
partition = omap_mux_get_partition(m);
if (!partition)
return -ENODEV;
omap_mux_write(partition, val, m->reg_offset);
*ppos += count;
return count;
}
static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_signal_fops = {
.open = omap_mux_dbg_signal_open,
.read = seq_read,
.write = omap_mux_dbg_signal_write,
.llseek = seq_lseek,
.release = single_release,
};
static struct dentry *mux_dbg_dir;
static void __init omap_mux_dbg_create_entry(
struct omap_mux_partition *partition,
struct dentry *mux_dbg_dir)
{
struct omap_mux_entry *e;
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
(void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO,
mux_dbg_dir, m,
&omap_mux_dbg_signal_fops);
}
}
static void __init omap_mux_dbg_init(void)
{
struct omap_mux_partition *partition;
static struct dentry *mux_dbg_board_dir;
mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
if (!mux_dbg_dir)
return;
mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
if (!mux_dbg_board_dir)
return;
list_for_each_entry(partition, &mux_partitions, node) {
omap_mux_dbg_create_entry(partition, mux_dbg_dir);
(void)debugfs_create_file(partition->name, S_IRUGO,
mux_dbg_board_dir, partition,
&omap_mux_dbg_board_fops);
}
}
#else
static inline void omap_mux_dbg_init(void)
{
}
#endif /* CONFIG_DEBUG_FS */
static void __init omap_mux_free_names(struct omap_mux *m)
{
int i;
for (i = 0; i < OMAP_MUX_NR_MODES; i++)
kfree(m->muxnames[i]);
#ifdef CONFIG_DEBUG_FS
for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
kfree(m->balls[i]);
#endif
}
/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
int __init omap_mux_late_init(void)
{
struct omap_mux_partition *partition;
int ret;
list_for_each_entry(partition, &mux_partitions, node) {
struct omap_mux_entry *e, *tmp;
list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
u16 mode = omap_mux_read(partition, m->reg_offset);
if (OMAP_MODE_GPIO(partition, mode))
continue;
#ifndef CONFIG_DEBUG_FS
mutex_lock(&muxmode_mutex);
list_del(&e->node);
mutex_unlock(&muxmode_mutex);
omap_mux_free_names(m);
kfree(m);
#endif
}
}
omap_mux_dbg_init();
/* see pinctrl-single-omap for the wake-up interrupt handling */
if (of_have_populated_dt())
return 0;
ret = request_irq(omap_prcm_event_to_irq("io"),
omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
"hwmod_io", omap_mux_late_init);
if (ret)
pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
return 0;
}
static void __init omap_mux_package_fixup(struct omap_mux *p,
struct omap_mux *superset)
{
while (p->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *s = superset;
int found = 0;
while (s->reg_offset != OMAP_MUX_TERMINATOR) {
if (s->reg_offset == p->reg_offset) {
*s = *p;
found++;
break;
}
s++;
}
if (!found)
pr_err("%s: Unknown entry offset 0x%x\n", __func__,
p->reg_offset);
p++;
}
}
#ifdef CONFIG_DEBUG_FS
static void __init omap_mux_package_init_balls(struct omap_ball *b,
struct omap_mux *superset)
{
while (b->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *s = superset;
int found = 0;
while (s->reg_offset != OMAP_MUX_TERMINATOR) {
if (s->reg_offset == b->reg_offset) {
s->balls[0] = b->balls[0];
s->balls[1] = b->balls[1];
found++;
break;
}
s++;
}
if (!found)
pr_err("%s: Unknown ball offset 0x%x\n", __func__,
b->reg_offset);
b++;
}
}
#else /* CONFIG_DEBUG_FS */
static inline void omap_mux_package_init_balls(struct omap_ball *b,
struct omap_mux *superset)
{
}
#endif /* CONFIG_DEBUG_FS */
static int __init omap_mux_setup(char *options)
{
if (!options)
return 0;
omap_mux_options = options;
return 1;
}
__setup("omap_mux=", omap_mux_setup);
/*
* Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
* cmdline options only override the bootloader values.
* During development, please enable CONFIG_DEBUG_FS, and use the
* signal specific entries under debugfs.
*/
static void __init omap_mux_set_cmdline_signals(void)
{
char *options, *next_opt, *token;
if (!omap_mux_options)
return;
options = kstrdup(omap_mux_options, GFP_KERNEL);
if (!options)
return;
next_opt = options;
while ((token = strsep(&next_opt, ",")) != NULL) {
char *keyval, *name;
u16 val;
keyval = token;
name = strsep(&keyval, "=");
if (name) {
int res;
res = kstrtou16(keyval, 0x10, &val);
if (res < 0)
continue;
omap_mux_init_signal(name, (u16)val);
}
}
kfree(options);
}
static int __init omap_mux_copy_names(struct omap_mux *src,
struct omap_mux *dst)
{
int i;
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
if (src->muxnames[i]) {
dst->muxnames[i] = kstrdup(src->muxnames[i],
GFP_KERNEL);
if (!dst->muxnames[i])
goto free;
}
}
#ifdef CONFIG_DEBUG_FS
for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
if (src->balls[i]) {
dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
if (!dst->balls[i])
goto free;
}
}
#endif
return 0;
free:
omap_mux_free_names(dst);
return -ENOMEM;
}
#endif /* CONFIG_OMAP_MUX */
static struct omap_mux *omap_mux_get_by_gpio(
struct omap_mux_partition *partition,
int gpio)
{
struct omap_mux_entry *e;
struct omap_mux *ret = NULL;
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m->gpio == gpio) {
ret = m;
break;
}
}
return ret;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
u16 omap_mux_get_gpio(int gpio)
{
struct omap_mux_partition *partition;
struct omap_mux *m = NULL;
list_for_each_entry(partition, &mux_partitions, node) {
m = omap_mux_get_by_gpio(partition, gpio);
if (m)
return omap_mux_read(partition, m->reg_offset);
}
if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
pr_err("%s: Could not get gpio%i\n", __func__, gpio);
return OMAP_MUX_TERMINATOR;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
void omap_mux_set_gpio(u16 val, int gpio)
{
struct omap_mux_partition *partition;
struct omap_mux *m = NULL;
list_for_each_entry(partition, &mux_partitions, node) {
m = omap_mux_get_by_gpio(partition, gpio);
if (m) {
omap_mux_write(partition, val, m->reg_offset);
return;
}
}
if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
pr_err("%s: Could not set gpio%i\n", __func__, gpio);
}
static struct omap_mux * __init omap_mux_list_add(
struct omap_mux_partition *partition,
struct omap_mux *src)
{
struct omap_mux_entry *entry;
struct omap_mux *m;
entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
if (!entry)
return NULL;
m = &entry->mux;
entry->mux = *src;
#ifdef CONFIG_OMAP_MUX
if (omap_mux_copy_names(src, m)) {
kfree(entry);
return NULL;
}
#endif
mutex_lock(&muxmode_mutex);
list_add_tail(&entry->node, &partition->muxmodes);
mutex_unlock(&muxmode_mutex);
return m;
}
/*
* Note if CONFIG_OMAP_MUX is not selected, we will only initialize
* the GPIO to mux offset mapping that is needed for dynamic muxing
* of GPIO pins for off-idle.
*/
static void __init omap_mux_init_list(struct omap_mux_partition *partition,
struct omap_mux *superset)
{
while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *entry;
#ifdef CONFIG_OMAP_MUX
if (!superset->muxnames[0]) {
superset++;
continue;
}
#else
/* Skip pins that are not muxed as GPIO by bootloader */
if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
superset->reg_offset))) {
superset++;
continue;
}
#endif
entry = omap_mux_list_add(partition, superset);
if (!entry) {
pr_err("%s: Could not add entry\n", __func__);
return;
}
superset++;
}
}
#ifdef CONFIG_OMAP_MUX
static void omap_mux_init_package(struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_ball *package_balls)
{
if (package_subset)
omap_mux_package_fixup(package_subset, superset);
if (package_balls)
omap_mux_package_init_balls(package_balls, superset);
}
static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
struct omap_board_mux *board_mux)
{
omap_mux_set_cmdline_signals();
omap_mux_write_array(partition, board_mux);
}
#else
static void omap_mux_init_package(struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_ball *package_balls)
{
}
static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
struct omap_board_mux *board_mux)
{
}
#endif
static u32 mux_partitions_cnt;
int __init omap_mux_init(const char *name, u32 flags,
u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls)
{
struct omap_mux_partition *partition;
partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
if (!partition)
return -ENOMEM;
partition->name = name;
partition->flags = flags;
partition->gpio = flags & OMAP_MUX_MODE7;
partition->size = mux_size;
partition->phys = mux_pbase;
partition->base = ioremap(mux_pbase, mux_size);
if (!partition->base) {
pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
__func__, partition->phys);
kfree(partition);
return -ENODEV;
}
INIT_LIST_HEAD(&partition->muxmodes);
list_add_tail(&partition->node, &mux_partitions);
mux_partitions_cnt++;
pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
mux_partitions_cnt, partition->name, partition->flags);
omap_mux_init_package(superset, package_subset, package_balls);
omap_mux_init_list(partition, superset);
omap_mux_init_signals(partition, board_mux);
return 0;
}
arch/arm/mach-omap2/mux.h deleted 100644 → 0
View file @ b4281455
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009-2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "mux34xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP_MUX_MODE0 0
#define OMAP_MUX_MODE1 1
#define OMAP_MUX_MODE2 2
#define OMAP_MUX_MODE3 3
#define OMAP_MUX_MODE4 4
#define OMAP_MUX_MODE5 5
#define OMAP_MUX_MODE6 6
#define OMAP_MUX_MODE7 7
/* 24xx/34xx mux bit defines */
#define OMAP_PULL_ENA (1 << 3)
#define OMAP_PULL_UP (1 << 4)
#define OMAP_ALTELECTRICALSEL (1 << 5)
/* omap3/4/5 specific mux bit defines */
#define OMAP_INPUT_EN (1 << 8)
#define OMAP_OFF_EN (1 << 9)
#define OMAP_OFFOUT_EN (1 << 10)
#define OMAP_OFFOUT_VAL (1 << 11)
#define OMAP_OFF_PULL_EN (1 << 12)
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
#define OMAP_WAKEUP_EVENT (1 << 15)
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
| OMAP_PULL_UP)
#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
/* Off mode states */
#define OMAP_PIN_OFF_NONE 0
#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
| OMAP_OFFOUT_VAL)
#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
| OMAP_OFF_PULL_UP)
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
partition->gpio)
#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */
#define OMAP_MUX_NR_MODES 8 /* Available modes */
#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
/*
* omap_mux_init flags definition:
*
* OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
* register which includes values from 0-7.
* OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
* The default value is 16 bits.
*/
#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
#define OMAP_MUX_REG_8BIT (1 << 3)
/**
* struct omap_board_data - board specific device data
* @id: instance id
* @flags: additional flags for platform init code
* @pads: array of device specific pads
* @pads_cnt: ARRAY_SIZE() of pads
*/
struct omap_board_data {
int id;
u32 flags;
struct omap_device_pad *pads;
int pads_cnt;
};
/**
* struct mux_partition - contain partition related information
* @name: name of the current partition
* @flags: flags specific to this partition
* @gpio: gpio mux mode
* @phys: physical address
* @size: partition size
* @base: virtual address after ioremap
* @muxmodes: list of nodes that belong to a partition
* @node: list node for the partitions linked list
*/
struct omap_mux_partition {
const char *name;
u32 flags;
u32 gpio;
u32 phys;
u32 size;
void __iomem *base;
struct list_head muxmodes;
struct list_head node;
};
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
* @balls: available balls on the package
*/
struct omap_mux {
u16 reg_offset;
u16 gpio;
#ifdef CONFIG_OMAP_MUX
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
#endif
#endif
};
/**
* struct omap_ball - data for balls on omap package
* @reg_offset: mux register offset from the mux base
* @balls: available balls on the package
*/
struct omap_ball {
u16 reg_offset;
char *balls[OMAP_MUX_NR_SIDES];
};
/**
* struct omap_board_mux - data for initializing mux registers
* @reg_offset: mux register offset from the mux base
* @mux_value: desired mux value to set
*/
struct omap_board_mux {
u16 reg_offset;
u16 value;
};
#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
needs enable, idle and off
values */
#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */
/**
* struct omap_device_pad - device specific pad configuration
* @name: signal name
* @flags: pad specific runtime flags
* @enable: runtime value for a pad
* @idle: idle value for a pad
* @off: off value for a pad, defaults to safe mode
* @partition: mux partition
* @mux: mux register
*/
struct omap_device_pad {
char *name;
u8 flags;
u16 enable;
u16 idle;
u16 off;
struct omap_mux_partition *partition;
struct omap_mux *mux;
};
struct omap_hwmod_mux_info;
#define OMAP_MUX_STATIC(signal, mode) \
{ \
.name = (signal), \
.enable = (mode), \
}
#if defined(CONFIG_OMAP_MUX)
/**
* omap_mux_init_gpio - initialize a signal based on the GPIO number
* @gpio: GPIO number
* @val: Options for the mux register value
*/
int omap_mux_init_gpio(int gpio, int val);
/**
* omap_mux_init_signal - initialize a signal based on the signal name
* @muxname: Mux name in mode0_name.signal_name format
* @val: Options for the mux register value
*/
int omap_mux_init_signal(const char *muxname, int val);
/**
* omap_hwmod_mux_init - initialize hwmod specific mux data
* @bpads: Board specific device signal names
* @nr_pads: Number of signal names for the device
*/
extern struct omap_hwmod_mux_info *
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
/**
* omap_hwmod_mux - omap hwmod specific pin muxing
* @hmux: Pads for a hwmod
* @state: Desired _HWMOD_STATE
*
* Called only from omap_hwmod.c, do not use.
*/
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
int omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux);
#else
static inline int omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux)
{
return 0;
}
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
}
static inline int omap_mux_init_signal(char *muxname, int val)
{
return 0;
}
static inline struct omap_hwmod_mux_info *
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
{
return NULL;
}
static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
}
static struct omap_board_mux *board_mux __maybe_unused;
#endif
/**
* omap_mux_get_gpio() - get mux register value based on GPIO number
* @gpio: GPIO number
*
*/
u16 omap_mux_get_gpio(int gpio);
/**
* omap_mux_set_gpio() - set mux register value based on GPIO number
* @val: New mux register value
* @gpio: GPIO number
*
*/
void omap_mux_set_gpio(u16 val, int gpio);
/**
* omap_mux_get() - get a mux partition by name
* @name: Name of the mux partition
*
*/
struct omap_mux_partition *omap_mux_get(const char *name);
/**
* omap_mux_read() - read mux register
* @partition: Mux partition
* @mux_offset: Offset of the mux register
*
*/
u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
/**
* omap_mux_write() - write mux register
* @partition: Mux partition
* @val: New mux register value
* @mux_offset: Offset of the mux register
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
/**
* omap_mux_write_array() - write an array of mux registers
* @partition: Mux partition
* @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write_array(struct omap_mux_partition *p,
struct omap_board_mux *board_mux);
/**
* omap2420_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap2430_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap4_mux_init() - initialize mux system with board specific set
* @board_subset: Board specific mux table
* @board_wkup_subset: Board specific mux table for wakeup instance
* @flags: OMAP package type used for the board
*/
int omap4_mux_init(struct omap_board_mux *board_subset,
struct omap_board_mux *board_wkup_subset, int flags);
/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(const char *name, u32 flags,
u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls);
arch/arm/mach-omap2/mux34xx.c deleted 100644 → 0
View file @ b4281455
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/init.h>
#include "mux.h"
#ifdef CONFIG_OMAP_MUX
#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.gpio = (g), \
.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
}
#else
#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.gpio = (g), \
}
#endif
#define _OMAP3_BALLENTRY(M0, bb, bt) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.balls = { bb, bt }, \
}
/*
* Superset of all mux modes for omap3
*/
static struct omap_mux __initdata omap3_muxmodes[] = {
_OMAP3_MUXENTRY(CAM_D0, 99,
"cam_d0", NULL, NULL, NULL,
"gpio_99", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D1, 100,
"cam_d1", NULL, NULL, NULL,
"gpio_100", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", "hw_dbg8", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", "hw_dbg9", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", "hw_dbg4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", "hw_dbg5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", "hw_dbg6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", "hw_dbg7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D6, 105,
"cam_d6", NULL, NULL, NULL,
"gpio_105", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D7, 106,
"cam_d7", NULL, NULL, NULL,
"gpio_106", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D8, 107,
"cam_d8", NULL, NULL, NULL,
"gpio_107", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D9, 108,
"cam_d9", NULL, NULL, NULL,
"gpio_108", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", "hw_dbg3", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", "hw_dbg0", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", "hw_dbg2", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", "hw_dbg11", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", "hw_dbg1", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", "hw_dbg10", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_XCLKA, 96,
"cam_xclka", NULL, NULL, NULL,
"gpio_96", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_XCLKB, 111,
"cam_xclkb", NULL, NULL, NULL,
"gpio_111", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DX0, 112,
"csi2_dx0", NULL, NULL, NULL,
"gpio_112", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DX1, 114,
"csi2_dx1", NULL, NULL, NULL,
"gpio_114", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DY0, 113,
"csi2_dy0", NULL, NULL, NULL,
"gpio_113", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DY1, 115,
"csi2_dy1", NULL, NULL, NULL,
"gpio_115", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_ACBIAS, 69,
"dss_acbias", NULL, NULL, NULL,
"gpio_69", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA0, 70,
"dss_data0", NULL, "uart1_cts", NULL,
"gpio_70", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA1, 71,
"dss_data1", NULL, "uart1_rts", NULL,
"gpio_71", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA10, 80,
"dss_data10", NULL, NULL, NULL,
"gpio_80", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA11, 81,
"dss_data11", NULL, NULL, NULL,
"gpio_81", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA12, 82,
"dss_data12", NULL, NULL, NULL,
"gpio_82", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA13, 83,
"dss_data13", NULL, NULL, NULL,
"gpio_83", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA14, 84,
"dss_data14", NULL, NULL, NULL,
"gpio_84", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA15, 85,
"dss_data15", NULL, NULL, NULL,
"gpio_85", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA16, 86,
"dss_data16", NULL, NULL, NULL,
"gpio_86", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA17, 87,
"dss_data17", NULL, NULL, NULL,
"gpio_87", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA18, 88,
"dss_data18", NULL, "mcspi3_clk", "dss_data0",
"gpio_88", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA19, 89,
"dss_data19", NULL, "mcspi3_simo", "dss_data1",
"gpio_89", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA20, 90,
"dss_data20", NULL, "mcspi3_somi", "dss_data2",
"gpio_90", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA21, 91,
"dss_data21", NULL, "mcspi3_cs0", "dss_data3",
"gpio_91", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA22, 92,
"dss_data22", NULL, "mcspi3_cs1", "dss_data4",
"gpio_92", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA23, 93,
"dss_data23", NULL, NULL, "dss_data5",
"gpio_93", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", NULL, NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA3, 73,
"dss_data3", NULL, NULL, NULL,
"gpio_73", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA4, 74,
"dss_data4", NULL, "uart3_rx_irrx", NULL,
"gpio_74", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA5, 75,
"dss_data5", NULL, "uart3_tx_irtx", NULL,
"gpio_75", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", "hw_dbg14", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", "hw_dbg15", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", "hw_dbg16", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", "hw_dbg17", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", "hw_dbg13", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", "hw_dbg12", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_VSYNC, 68,
"dss_vsync", NULL, NULL, NULL,
"gpio_68", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
_OMAP3_MUXENTRY(GPMC_A1, 34,
"gpmc_a1", NULL, NULL, NULL,
"gpio_34", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A10, 43,
"gpmc_a10", "sys_ndmareq3", NULL, NULL,
"gpio_43", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A2, 35,
"gpmc_a2", NULL, NULL, NULL,
"gpio_35", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A3, 36,
"gpmc_a3", NULL, NULL, NULL,
"gpio_36", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A4, 37,
"gpmc_a4", NULL, NULL, NULL,
"gpio_37", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A5, 38,
"gpmc_a5", NULL, NULL, NULL,
"gpio_38", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A6, 39,
"gpmc_a6", NULL, NULL, NULL,
"gpio_39", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A7, 40,
"gpmc_a7", NULL, NULL, NULL,
"gpio_40", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A8, 41,
"gpmc_a8", NULL, NULL, NULL,
"gpio_41", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A9, 42,
"gpmc_a9", "sys_ndmareq2", NULL, NULL,
"gpio_42", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_CLK, 59,
"gpmc_clk", NULL, NULL, NULL,
"gpio_59", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D10, 46,
"gpmc_d10", NULL, NULL, NULL,
"gpio_46", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D11, 47,
"gpmc_d11", NULL, NULL, NULL,
"gpio_47", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D12, 48,
"gpmc_d12", NULL, NULL, NULL,
"gpio_48", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D13, 49,
"gpmc_d13", NULL, NULL, NULL,
"gpio_49", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D14, 50,
"gpmc_d14", NULL, NULL, NULL,
"gpio_50", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D15, 51,
"gpmc_d15", NULL, NULL, NULL,
"gpio_51", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D8, 44,
"gpmc_d8", NULL, NULL, NULL,
"gpio_44", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D9, 45,
"gpmc_d9", NULL, NULL, NULL,
"gpio_45", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
"gpmc_nbe0_cle", NULL, NULL, NULL,
"gpio_60", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NBE1, 61,
"gpmc_nbe1", NULL, NULL, NULL,
"gpio_61", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS1, 52,
"gpmc_ncs1", NULL, NULL, NULL,
"gpio_52", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS2, 53,
"gpmc_ncs2", NULL, NULL, NULL,
"gpio_53", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS3, 54,
"gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
"gpio_54", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS4, 55,
"gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
"gpio_55", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS5, 56,
"gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
"gpio_56", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS6, 57,
"gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
"gpio_57", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS7, 58,
"gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
"gpio_58", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NWP, 62,
"gpmc_nwp", NULL, NULL, NULL,
"gpio_62", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT1, 63,
"gpmc_wait1", NULL, NULL, NULL,
"gpio_63", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT2, 64,
"gpmc_wait2", NULL, NULL, NULL,
"gpio_64", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT3, 65,
"gpmc_wait3", "sys_ndmareq1", NULL, NULL,
"gpio_65", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HDQ_SIO, 170,
"hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
"gpio_170", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_CLK, 120,
"hsusb0_clk", NULL, NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
"hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
"hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
"gpio_130", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
"hsusb0_data2", NULL, "uart3_rts_sd", NULL,
"gpio_131", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
"hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
"gpio_169", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
"hsusb0_data4", NULL, NULL, NULL,
"gpio_188", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
"hsusb0_data5", NULL, NULL, NULL,
"gpio_189", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
"hsusb0_data6", NULL, NULL, NULL,
"gpio_190", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
"hsusb0_data7", NULL, NULL, NULL,
"gpio_191", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DIR, 122,
"hsusb0_dir", NULL, NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_NXT, 124,
"hsusb0_nxt", NULL, NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_STP, 121,
"hsusb0_stp", NULL, NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C2_SCL, 168,
"i2c2_scl", NULL, NULL, NULL,
"gpio_168", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C2_SDA, 183,
"i2c2_sda", NULL, NULL, NULL,
"gpio_183", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C3_SCL, 184,
"i2c3_scl", NULL, NULL, NULL,
"gpio_184", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C3_SDA, 185,
"i2c3_sda", NULL, NULL, NULL,
"gpio_185", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C4_SCL, 0,
"i2c4_scl", "sys_nvmode1", NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C4_SDA, 0,
"i2c4_sda", "sys_nvmode2", NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(JTAG_EMU0, 11,
"jtag_emu0", NULL, NULL, NULL,
"gpio_11", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(JTAG_EMU1, 31,
"jtag_emu1", NULL, NULL, NULL,
"gpio_31", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
"mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
"gpio_156", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
"mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
"gpio_162", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_DR, 159,
"mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
"gpio_159", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_DX, 158,
"mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
"gpio_158", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSR, 157,
"mcbsp1_fsr", NULL, "cam_global_reset", NULL,
"gpio_157", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSX, 161,
"mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
"gpio_161", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
"mcbsp2_clkx", NULL, NULL, NULL,
"gpio_117", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_DR, 118,
"mcbsp2_dr", NULL, NULL, NULL,
"gpio_118", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_DX, 119,
"mcbsp2_dx", NULL, NULL, NULL,
"gpio_119", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_FSX, 116,
"mcbsp2_fsx", NULL, NULL, NULL,
"gpio_116", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
"mcbsp3_clkx", "uart2_tx", NULL, NULL,
"gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DR, 141,
"mcbsp3_dr", "uart2_rts", NULL, NULL,
"gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DX, 140,
"mcbsp3_dx", "uart2_cts", NULL, NULL,
"gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_FSX, 143,
"mcbsp3_fsx", "uart2_rx", NULL, NULL,
"gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
"mcbsp4_clkx", NULL, NULL, NULL,
"gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DR, 153,
"mcbsp4_dr", NULL, NULL, NULL,
"gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DX, 154,
"mcbsp4_dx", NULL, NULL, NULL,
"gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_FSX, 155,
"mcbsp4_fsx", NULL, NULL, NULL,
"gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP_CLKS, 160,
"mcbsp_clks", NULL, "cam_shutter", NULL,
"gpio_160", "uart1_cts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CLK, 171,
"mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
"gpio_171", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS0, 174,
"mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
"gpio_174", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS1, 175,
"mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
"gpio_175", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS2, 176,
"mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
"gpio_176", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS3, 177,
"mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
"gpio_177", "mm2_txdat", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
"mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
"gpio_172", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
"mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
"gpio_173", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CLK, 178,
"mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
"gpio_178", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CS0, 181,
"mcspi2_cs0", "gpt11_pwm_evt",
"hsusb2_tll_data6", "hsusb2_data6",
"gpio_181", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CS1, 182,
"mcspi2_cs1", "gpt8_pwm_evt",
"hsusb2_tll_data3", "hsusb2_data3",
"gpio_182", "mm2_txen_n", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
"mcspi2_simo", "gpt9_pwm_evt",
"hsusb2_tll_data4", "hsusb2_data4",
"gpio_179", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
"mcspi2_somi", "gpt10_pwm_evt",
"hsusb2_tll_data5", "hsusb2_data5",
"gpio_180", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CLK, 120,
"sdmmc1_clk", NULL, NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CMD, 121,
"sdmmc1_cmd", NULL, NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
"sdmmc1_dat0", NULL, NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
"sdmmc1_dat1", NULL, NULL, NULL,
"gpio_123", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
"sdmmc1_dat2", NULL, NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
"sdmmc1_dat3", NULL, NULL, NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
"sdmmc1_dat4", NULL, "sim_io", NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
"sdmmc1_dat5", NULL, "sim_clk", NULL,
"gpio_127", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
"sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
"gpio_128", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
"sdmmc1_dat7", NULL, "sim_rst", NULL,
"gpio_129", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_CLK, 130,
"sdmmc2_clk", "mcspi3_clk", NULL, NULL,
"gpio_130", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_CMD, 131,
"sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
"gpio_131", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
"sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
"gpio_132", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
"sdmmc2_dat1", NULL, NULL, NULL,
"gpio_133", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
"sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
"gpio_134", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
"sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
"gpio_135", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
"sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
"gpio_136", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
"sdmmc2_dat5", "sdmmc2_dir_dat1",
"cam_global_reset", "sdmmc3_dat1",
"gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
"sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
"gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
"sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
"gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE0, 0,
"sdrc_cke0", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE1, 0,
"sdrc_cke1", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT0, 2,
"sys_boot0", NULL, NULL, NULL,
"gpio_2", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT1, 3,
"sys_boot1", NULL, NULL, NULL,
"gpio_3", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT2, 4,
"sys_boot2", NULL, NULL, NULL,
"gpio_4", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT3, 5,
"sys_boot3", NULL, NULL, NULL,
"gpio_5", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT4, 6,
"sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
"gpio_6", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT5, 7,
"sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
"gpio_7", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT6, 8,
"sys_boot6", NULL, NULL, NULL,
"gpio_8", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
"sys_clkout1", NULL, NULL, NULL,
"gpio_10", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
"sys_clkout2", NULL, NULL, NULL,
"gpio_186", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKREQ, 1,
"sys_clkreq", NULL, NULL, NULL,
"gpio_1", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_NIRQ, 0,
"sys_nirq", NULL, NULL, NULL,
"gpio_0", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_NRESWARM, 30,
"sys_nreswarm", NULL, NULL, NULL,
"gpio_30", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
"sys_off_mode", NULL, NULL, NULL,
"gpio_9", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RX, 151,
"uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
"gpio_151", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_CTS, 144,
"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
"gpio_144", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_RTS, 145,
"uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
"gpio_145", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_RX, 147,
"uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
"gpio_147", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_TX, 146,
"uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
"gpio_146", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
"uart3_cts_rctx", NULL, NULL, NULL,
"gpio_163", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_RTS_SD, 164,
"uart3_rts_sd", NULL, NULL, NULL,
"gpio_164", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
"uart3_rx_irrx", NULL, NULL, NULL,
"gpio_165", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
"uart3_tx_irtx", NULL, NULL, NULL,
"gpio_166", NULL, NULL, "safe_mode"),
/* Only on 3630, see omap36xx_cbp_subset for the signals */
_OMAP3_MUXENTRY(GPMC_A11, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(GPMC_A11, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
/*
* Signals different on CBC package compared to the superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
static struct omap_mux __initdata omap3_cbc_subset[] = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbc_subset NULL
#endif
/*
* Balls for CBC package
* 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
*
* FIXME: What's up with the outdated TI documentation? See:
*
* http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
* http://community.ti.com/forums/t/10982.aspx
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBC)
static struct omap_ball __initdata omap3_cbc_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
_OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
_OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
_OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
_OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
_OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
_OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
_OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
_OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
_OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
_OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
_OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
_OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
_OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
_OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
_OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
_OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
_OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
_OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
_OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
_OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
_OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
_OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
_OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
_OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
_OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
_OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
_OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
_OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
_OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
_OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
_OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
_OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
_OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
_OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbc_ball NULL
#endif
/*
* Signals different on CUS package compared to superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
static struct omap_mux __initdata omap3_cus_subset[] = {
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", NULL),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", NULL),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", NULL),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", NULL),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
_OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
"mcbsp3_clkx", "uart2_tx", NULL, NULL,
"gpio_142", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DR, 141,
"mcbsp3_dr", "uart2_rts", NULL, NULL,
"gpio_141", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DX, 140,
"mcbsp3_dx", "uart2_cts", NULL, NULL,
"gpio_140", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_FSX, 143,
"mcbsp3_fsx", "uart2_rx", NULL, NULL,
"gpio_143", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
"sdmmc2_dat5", "sdmmc2_dir_dat1",
"cam_global_reset", "sdmmc3_dat1",
"gpio_137", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
"sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
"gpio_138", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
"sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
"gpio_139", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", NULL, NULL, NULL,
"gpio_150", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cus_subset NULL
#endif
/*
* Balls for CUS package
* 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CUS)
static struct omap_ball __initdata omap3_cus_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
_OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
_OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
_OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
_OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
_OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
_OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
_OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
_OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
_OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
_OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
_OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
_OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
_OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
_OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
_OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
_OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
_OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
_OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
_OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
_OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
_OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
_OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
_OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
_OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
_OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
_OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
_OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
_OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
_OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
_OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
_OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
_OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
_OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
_OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
_OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
_OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cus_ball NULL
#endif
/*
* Signals different on CBB package compared to superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
static struct omap_mux __initdata omap3_cbb_subset[] = {
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", NULL),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", NULL),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", NULL),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", NULL),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbb_subset NULL
#endif
/*
* Balls for CBB package
* 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBB)
static struct omap_ball __initdata omap3_cbb_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
_OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
_OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
_OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
_OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
_OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
_OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
_OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
_OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
_OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
_OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
_OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
_OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
_OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
_OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
_OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
_OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
_OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
_OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
_OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
_OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
_OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
_OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
_OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
_OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
_OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
_OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
_OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
_OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
_OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
_OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
_OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbb_ball NULL
#endif
/*
* Signals different on 36XX CBP package compared to 34XX CBC package
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
static struct omap_mux __initdata omap36xx_cbp_subset[] = {
_OMAP3_MUXENTRY(CAM_D0, 99,
"cam_d0", NULL, "csi2_dx2", NULL,
"gpio_99", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D1, 100,
"cam_d1", NULL, "csi2_dy2", NULL,
"gpio_100", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", "ssi2_wake", NULL, NULL,
"gpio_109", "hw_dbg8", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", "ssi2_rdy_tx", NULL, NULL,
"gpio_101", "hw_dbg4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", "ssi2_dat_rx", NULL, NULL,
"gpio_102", "hw_dbg5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", "ssi2_flag_rx", NULL, NULL,
"gpio_103", "hw_dbg6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", "ssi2_rdy_rx", NULL, NULL,
"gpio_104", "hw_dbg7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", "ssi2_dat_tx", NULL, NULL,
"gpio_94", "hw_dbg0", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", "ssi2_flag_tx", NULL, NULL,
"gpio_95", "hw_dbg1", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA0, 70,
"dss_data0", "dsi_dx0", "uart1_cts", NULL,
"gpio_70", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA1, 71,
"dss_data1", "dsi_dy0", "uart1_rts", NULL,
"gpio_71", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", "dsi_dx1", NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA3, 73,
"dss_data3", "dsi_dy1", NULL, NULL,
"gpio_73", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA4, 74,
"dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
"gpio_74", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA5, 75,
"dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
"gpio_75", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
"gpio_76", "hw_dbg14", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
"gpio_77", "hw_dbg15", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, "uart3_rx_irrx", NULL,
"gpio_78", "hw_dbg16", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, "uart3_tx_irtx", NULL,
"gpio_79", "hw_dbg17", NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
_OMAP3_MUXENTRY(GPMC_A11, 0,
"gpmc_a11", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT2, 64,
"gpmc_wait2", NULL, "uart4_tx", NULL,
"gpio_64", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT3, 65,
"gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
"gpio_65", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
"hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
"gpio_125", "uart2_tx", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
"hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
"gpio_130", "uart2_rx", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
"hsusb0_data2", NULL, "uart3_rts_sd", NULL,
"gpio_131", "uart2_rts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
"hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
"gpio_169", "uart2_cts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
"mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
"gpio_156", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSR, 157,
"mcbsp1_fsr", "adpllv2d_dithering_en1",
"cam_global_reset", NULL,
"gpio_157", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
"mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
"gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DR, 153,
"mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
"gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DX, 154,
"mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
"gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_FSX, 155,
"mcbsp4_fsx", "ssi1_wake", NULL, NULL,
"gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS1, 175,
"mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
"gpio_175", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
"sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
"sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
"sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
"sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
"sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
"sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
"sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
"sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
"sad2d_mread", "mad2d_sread", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
"sad2d_mwrite", "mad2d_swrite", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
"sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
"sad2d_sread", "mad2d_mread", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
"sad2d_swrite", "mad2d_mwrite", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SDMMC1_CLK, 120,
"sdmmc1_clk", "ms_clk", NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CMD, 121,
"sdmmc1_cmd", "ms_bs", NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
"sdmmc1_dat0", "ms_dat0", NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
"sdmmc1_dat1", "ms_dat1", NULL, NULL,
"gpio_123", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
"sdmmc1_dat2", "ms_dat2", NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
"sdmmc1_dat3", "ms_dat3", NULL, NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE0, 0,
"sdrc_cke0", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode_out1"),
_OMAP3_MUXENTRY(SDRC_CKE1, 0,
"sdrc_cke1", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode_out1"),
_OMAP3_MUXENTRY(SIM_IO, 126,
"sim_io", "sim_io_low_impedance", NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_CLK, 127,
"sim_clk", NULL, NULL, NULL,
"gpio_127", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
"sim_pwrctrl", NULL, NULL, NULL,
"gpio_128", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_RST, 129,
"sim_rst", NULL, NULL, NULL,
"gpio_129", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT0, 2,
"sys_boot0", NULL, NULL, "dss_data18",
"gpio_2", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT1, 3,
"sys_boot1", NULL, NULL, "dss_data19",
"gpio_3", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT3, 5,
"sys_boot3", NULL, NULL, "dss_data20",
"gpio_5", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT4, 6,
"sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
"gpio_6", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT5, 7,
"sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
"gpio_7", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT6, 8,
"sys_boot6", NULL, NULL, "dss_data23",
"gpio_8", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap36xx_cbp_subset NULL
#endif
/*
* Balls for 36XX CBP package
* 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined (CONFIG_OMAP_PACKAGE_CBP)
static struct omap_ball __initdata omap36xx_cbp_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
_OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
_OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
_OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
_OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
_OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
_OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
_OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
_OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
_OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
_OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
_OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
_OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
_OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
_OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
_OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
_OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
_OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
_OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
_OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
_OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
_OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
_OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
_OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
_OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
_OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
_OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
_OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
_OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
_OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
_OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
_OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
_OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
_OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
_OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
_OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
_OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
_OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap36xx_cbp_ball NULL
#endif
int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
{
struct omap_mux *package_subset;
struct omap_ball *package_balls;
switch (flags & OMAP_PACKAGE_MASK) {
case OMAP_PACKAGE_CBC:
package_subset = omap3_cbc_subset;
package_balls = omap3_cbc_ball;
break;
case OMAP_PACKAGE_CBB:
package_subset = omap3_cbb_subset;
package_balls = omap3_cbb_ball;
break;
case OMAP_PACKAGE_CUS:
package_subset = omap3_cus_subset;
package_balls = omap3_cus_ball;
break;
case OMAP_PACKAGE_CBP:
package_subset = omap36xx_cbp_subset;
package_balls = omap36xx_cbp_ball;
break;
default:
pr_err("%s Unknown omap package, mux disabled\n", __func__);
return -EINVAL;
}
return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
OMAP3_CONTROL_PADCONF_MUX_PBASE,
OMAP3_CONTROL_PADCONF_MUX_SIZE,
omap3_muxmodes, package_subset, board_subset,
package_balls);
}
arch/arm/mach-omap2/mux34xx.h deleted 100644 → 0
View file @ b4281455
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
#define OMAP3_MUX(mode0, mux_value) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
.value = (mux_value), \
}
/*
* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
*
* Extracted from the TRM. Add 0x48002030 to these values to get the
* absolute addresses. The name in the macro is the mode-0 name of
* the pin. NOTE: These registers are 16-bits wide.
*
* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
* of CHASSIS for some registers. For the defines, we follow the
* 36XX naming, and use SDMMC and CHASSIS.
*/
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
/* 36xx only */
#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
(OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)
arch/arm/plat-omap/Kconfig
View file @ e9f5f1e4
...@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS ...@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS
probably do not want this option enabled until your probably do not want this option enabled until your
device drivers work properly. device drivers work properly.
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
sets the multiplexing correctly, say N. Otherwise, or if unsure,
say Y.
config OMAP_MUX_DEBUG
bool "Multiplexing debug output"
depends on OMAP_MUX
help
Makes the multiplexing functions print out a lot of debug info.
This is useful if you want to find out the correct values of the
multiplexing registers.
config OMAP_MUX_WARNINGS
bool "Warn about pins the bootloader didn't set up"
depends on OMAP_MUX
default y
help
Choose Y here to warn whenever driver initialization logic needs
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
config OMAP_MPU_TIMER config OMAP_MPU_TIMER
bool "Use mpu timer" bool "Use mpu timer"
depends on ARCH_OMAP1 depends on ARCH_OMAP1
......
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