Skip to content

L
linux
Commit eb12511f authored by Thor Thayer's avatar Thor Thayer Committed by Moritz Fischer
Browse files
Options

fpga: altera-cvp: Discover Vendor Specific offset 

Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read and write abstraction functions to
handle the offset (altera_read_config_dword() and
altera_write_config_dword()).
Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: default avatarMoritz Fischer <mdf@kernel.org>
parent 2949dc44
Show whitespace changes
Inline Side-by-side
Showing with 58 additions and 37 deletions
drivers/fpga/altera-cvp.c
View file @ eb12511f
...@@ -22,10 +22,10 @@ ...@@ -22,10 +22,10 @@
#define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */ #define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */
/* Vendor Specific Extended Capability Registers */ /* Vendor Specific Extended Capability Registers */
#define VSE_PCIE_EXT_CAP_ID 0x200 #define VSE_PCIE_EXT_CAP_ID 0x0
#define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */ #define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */
#define VSE_CVP_STATUS 0x21c /* 32bit */ #define VSE_CVP_STATUS 0x1c /* 32bit */
#define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */ #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */
#define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */ #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */
#define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */ #define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */
...@@ -33,18 +33,18 @@ ...@@ -33,18 +33,18 @@
#define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */ #define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */
#define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */ #define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */
#define VSE_CVP_MODE_CTRL 0x220 /* 32bit */ #define VSE_CVP_MODE_CTRL 0x20 /* 32bit */
#define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */ #define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */
#define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */ #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */
#define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */ #define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */
#define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8) #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)
#define VSE_CVP_DATA 0x228 /* 32bit */ #define VSE_CVP_DATA 0x28 /* 32bit */
#define VSE_CVP_PROG_CTRL 0x22c /* 32bit */ #define VSE_CVP_PROG_CTRL 0x2c /* 32bit */
#define VSE_CVP_PROG_CTRL_CONFIG BIT(0) #define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
#define VSE_CVP_PROG_CTRL_START_XFER BIT(1) #define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
#define VSE_UNCOR_ERR_STATUS 0x234 /* 32bit */ #define VSE_UNCOR_ERR_STATUS 0x34 /* 32bit */
#define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */ #define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
#define DRV_NAME "altera-cvp" #define DRV_NAME "altera-cvp"
...@@ -61,14 +61,29 @@ struct altera_cvp_conf { ...@@ -61,14 +61,29 @@ struct altera_cvp_conf {
u32 data); u32 data);
char mgr_name[64]; char mgr_name[64];
u8 numclks; u8 numclks;
u32 vsec_offset;
}; };
static int altera_read_config_dword(struct altera_cvp_conf *conf,
int where, u32 *val)
{
return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
val);
}
static int altera_write_config_dword(struct altera_cvp_conf *conf,
int where, u32 val)
{
return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
val);
}
static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr) static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
{ {
struct altera_cvp_conf *conf = mgr->priv; struct altera_cvp_conf *conf = mgr->priv;
u32 status; u32 status;
pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &status); altera_read_config_dword(conf, VSE_CVP_STATUS, &status);
if (status & VSE_CVP_STATUS_CFG_DONE) if (status & VSE_CVP_STATUS_CFG_DONE)
return FPGA_MGR_STATE_OPERATING; return FPGA_MGR_STATE_OPERATING;
...@@ -86,7 +101,8 @@ static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val) ...@@ -86,7 +101,8 @@ static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val) static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
{ {
pci_write_config_dword(conf->pci_dev, VSE_CVP_DATA, val); pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
val);
} }
/* switches between CvP clock and internal clock */ /* switches between CvP clock and internal clock */
...@@ -96,10 +112,10 @@ static void altera_cvp_dummy_write(struct altera_cvp_conf *conf) ...@@ -96,10 +112,10 @@ static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
u32 val; u32 val;
/* set 1 CVP clock cycle for every CVP Data Register Write */ /* set 1 CVP clock cycle for every CVP Data Register Write */
pci_read_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK; val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF; val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
pci_write_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, val); altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
for (i = 0; i < CVP_DUMMY_WR; i++) for (i = 0; i < CVP_DUMMY_WR; i++)
conf->write_data(conf, 0); /* dummy data, could be any value */ conf->write_data(conf, 0); /* dummy data, could be any value */
...@@ -116,7 +132,7 @@ static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask, ...@@ -116,7 +132,7 @@ static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
retries++; retries++;
do { do {
pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val); altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
if ((val & status_mask) == status_val) if ((val & status_mask) == status_val)
return 0; return 0;
...@@ -131,18 +147,17 @@ static int altera_cvp_teardown(struct fpga_manager *mgr, ...@@ -131,18 +147,17 @@ static int altera_cvp_teardown(struct fpga_manager *mgr,
struct fpga_image_info *info) struct fpga_image_info *info)
{ {
struct altera_cvp_conf *conf = mgr->priv; struct altera_cvp_conf *conf = mgr->priv;
struct pci_dev *pdev = conf->pci_dev;
int ret; int ret;
u32 val; u32 val;
/* STEP 12 - reset START_XFER bit */ /* STEP 12 - reset START_XFER bit */
pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
val &= ~VSE_CVP_PROG_CTRL_START_XFER; val &= ~VSE_CVP_PROG_CTRL_START_XFER;
pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
/* STEP 13 - reset CVP_CONFIG bit */ /* STEP 13 - reset CVP_CONFIG bit */
val &= ~VSE_CVP_PROG_CTRL_CONFIG; val &= ~VSE_CVP_PROG_CTRL_CONFIG;
pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
/* /*
* STEP 14 * STEP 14
...@@ -164,7 +179,6 @@ static int altera_cvp_write_init(struct fpga_manager *mgr, ...@@ -164,7 +179,6 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
const char *buf, size_t count) const char *buf, size_t count)
{ {
struct altera_cvp_conf *conf = mgr->priv; struct altera_cvp_conf *conf = mgr->priv;
struct pci_dev *pdev = conf->pci_dev;
u32 iflags, val; u32 iflags, val;
int ret; int ret;
...@@ -184,7 +198,7 @@ static int altera_cvp_write_init(struct fpga_manager *mgr, ...@@ -184,7 +198,7 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
conf->numclks = 1; /* for uncompressed and unencrypted images */ conf->numclks = 1; /* for uncompressed and unencrypted images */
/* STEP 1 - read CVP status and check CVP_EN flag */ /* STEP 1 - read CVP status and check CVP_EN flag */
pci_read_config_dword(pdev, VSE_CVP_STATUS, &val); altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
if (!(val & VSE_CVP_STATUS_CVP_EN)) { if (!(val & VSE_CVP_STATUS_CVP_EN)) {
dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val); dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
return -ENODEV; return -ENODEV;
...@@ -202,14 +216,14 @@ static int altera_cvp_write_init(struct fpga_manager *mgr, ...@@ -202,14 +216,14 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
* - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned) * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
*/ */
/* switch from fabric to PMA clock */ /* switch from fabric to PMA clock */
pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL; val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
/* set CVP mode */ /* set CVP mode */
pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
val |= VSE_CVP_MODE_CTRL_CVP_MODE; val |= VSE_CVP_MODE_CTRL_CVP_MODE;
pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
/* /*
* STEP 3 * STEP 3
...@@ -218,10 +232,10 @@ static int altera_cvp_write_init(struct fpga_manager *mgr, ...@@ -218,10 +232,10 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
altera_cvp_dummy_write(conf); altera_cvp_dummy_write(conf);
/* STEP 4 - set CVP_CONFIG bit */ /* STEP 4 - set CVP_CONFIG bit */
pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
/* request control block to begin transfer using CVP */ /* request control block to begin transfer using CVP */
val |= VSE_CVP_PROG_CTRL_CONFIG; val |= VSE_CVP_PROG_CTRL_CONFIG;
pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
/* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */ /* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
...@@ -238,15 +252,15 @@ static int altera_cvp_write_init(struct fpga_manager *mgr, ...@@ -238,15 +252,15 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
altera_cvp_dummy_write(conf); altera_cvp_dummy_write(conf);
/* STEP 7 - set START_XFER */ /* STEP 7 - set START_XFER */
pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
val |= VSE_CVP_PROG_CTRL_START_XFER; val |= VSE_CVP_PROG_CTRL_START_XFER;
pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */ /* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK; val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF; val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
return 0; return 0;
} }
...@@ -257,7 +271,7 @@ static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes) ...@@ -257,7 +271,7 @@ static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
u32 val; u32 val;
/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */ /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val); altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
if (val & VSE_CVP_STATUS_CFG_ERR) { if (val & VSE_CVP_STATUS_CFG_ERR) {
dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n", dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
bytes); bytes);
...@@ -316,27 +330,25 @@ static int altera_cvp_write_complete(struct fpga_manager *mgr, ...@@ -316,27 +330,25 @@ static int altera_cvp_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info) struct fpga_image_info *info)
{ {
struct altera_cvp_conf *conf = mgr->priv; struct altera_cvp_conf *conf = mgr->priv;
struct pci_dev *pdev = conf->pci_dev; u32 mask, val;
int ret; int ret;
u32 mask;
u32 val;
ret = altera_cvp_teardown(mgr, info); ret = altera_cvp_teardown(mgr, info);
if (ret) if (ret)
return ret; return ret;
/* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */ /* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
pci_read_config_dword(pdev, VSE_UNCOR_ERR_STATUS, &val); altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) { if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n"); dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
return -EPROTO; return -EPROTO;
} }
/* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */ /* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL; val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
val &= ~VSE_CVP_MODE_CTRL_CVP_MODE; val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */ /* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE; mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
...@@ -395,22 +407,29 @@ static int altera_cvp_probe(struct pci_dev *pdev, ...@@ -395,22 +407,29 @@ static int altera_cvp_probe(struct pci_dev *pdev,
{ {
struct altera_cvp_conf *conf; struct altera_cvp_conf *conf;
struct fpga_manager *mgr; struct fpga_manager *mgr;
int ret, offset;
u16 cmd, val; u16 cmd, val;
u32 regval; u32 regval;
int ret;
/* Discover the Vendor Specific Offset for this device */
offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
if (!offset) {
dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
return -ENODEV;
}
/* /*
* First check if this is the expected FPGA device. PCI config * First check if this is the expected FPGA device. PCI config
* space access works without enabling the PCI device, memory * space access works without enabling the PCI device, memory
* space access is enabled further down. * space access is enabled further down.
*/ */
pci_read_config_word(pdev, VSE_PCIE_EXT_CAP_ID, &val); pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
if (val != VSE_PCIE_EXT_CAP_ID_VAL) { if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val); dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
return -ENODEV; return -ENODEV;
} }
pci_read_config_dword(pdev, VSE_CVP_STATUS, &regval); pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, &regval);
if (!(regval & VSE_CVP_STATUS_CVP_EN)) { if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
dev_err(&pdev->dev, dev_err(&pdev->dev,
"CVP is disabled for this device: CVP_STATUS Reg 0x%x\n", "CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
...@@ -422,6 +441,8 @@ static int altera_cvp_probe(struct pci_dev *pdev, ...@@ -422,6 +441,8 @@ static int altera_cvp_probe(struct pci_dev *pdev,
if (!conf) if (!conf)
return -ENOMEM; return -ENOMEM;
conf->vsec_offset = offset;
/* /*
* Enable memory BAR access. We cannot use pci_enable_device() here * Enable memory BAR access. We cannot use pci_enable_device() here
* because it will make the driver unusable with FPGA devices that * because it will make the driver unusable with FPGA devices that
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7