Commit ecad2ce8 authored by Srujana Challa's avatar Srujana Challa Committed by David S. Miller

octeontx2-af: cn10k: Add mailbox to configure reassembly timeout

CN10K CPT coprocessor includes a component named RXC which
is responsible for reassembly of inner IP packets. RXC has
the feature to evict oldest entries based on age/threshold.
This patch adds a new mailbox to configure reassembly age
or threshold.
Signed-off-by: default avatarJerin Jacob Kollanukkaran <jerinj@marvell.com>
Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e4bbc5c5
...@@ -177,6 +177,8 @@ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ ...@@ -177,6 +177,8 @@ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
cpt_rd_wr_reg_msg) \ cpt_rd_wr_reg_msg) \
M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
msg_rsp) \
/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
npc_mcam_alloc_entry_rsp) \ npc_mcam_alloc_entry_rsp) \
...@@ -1255,4 +1257,15 @@ struct cpt_lf_alloc_req_msg { ...@@ -1255,4 +1257,15 @@ struct cpt_lf_alloc_req_msg {
int blkaddr; int blkaddr;
}; };
/* Mailbox message request format to configure reassembly timeout. */
struct cpt_rxc_time_cfg_req {
struct mbox_msghdr hdr;
int blkaddr;
u32 step;
u16 zombie_thres;
u16 zombie_limit;
u16 active_thres;
u16 active_limit;
};
#endif /* MBOX_H */ #endif /* MBOX_H */
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2020 Marvell. */ /* Copyright (C) 2020 Marvell. */
#include <linux/bitfield.h>
#include <linux/pci.h> #include <linux/pci.h>
#include "rvu_struct.h" #include "rvu_struct.h"
#include "rvu_reg.h" #include "rvu_reg.h"
...@@ -60,6 +61,17 @@ static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc) ...@@ -60,6 +61,17 @@ static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc)
return true; return true;
} }
static int validate_and_get_cpt_blkaddr(int req_blkaddr)
{
int blkaddr;
blkaddr = req_blkaddr ? req_blkaddr : BLKADDR_CPT0;
if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
return -EINVAL;
return blkaddr;
}
int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
struct cpt_lf_alloc_req_msg *req, struct cpt_lf_alloc_req_msg *req,
struct msg_rsp *rsp) struct msg_rsp *rsp)
...@@ -70,9 +82,9 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, ...@@ -70,9 +82,9 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
int num_lfs, slot; int num_lfs, slot;
u64 val; u64 val;
blkaddr = req->blkaddr ? req->blkaddr : BLKADDR_CPT0; blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) if (blkaddr < 0)
return -ENODEV; return blkaddr;
if (req->eng_grpmsk == 0x0) if (req->eng_grpmsk == 0x0)
return CPT_AF_ERR_GRP_INVALID; return CPT_AF_ERR_GRP_INVALID;
...@@ -170,7 +182,9 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) ...@@ -170,7 +182,9 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
struct rvu_block *block; struct rvu_block *block;
struct rvu_pfvf *pfvf; struct rvu_pfvf *pfvf;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0); blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
if (blkaddr < 0)
return blkaddr;
/* Registers that can be accessed from PF/VF */ /* Registers that can be accessed from PF/VF */
if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) ||
...@@ -226,9 +240,9 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, ...@@ -226,9 +240,9 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
{ {
int blkaddr; int blkaddr;
blkaddr = req->blkaddr ? req->blkaddr : BLKADDR_CPT0; blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) if (blkaddr < 0)
return -ENODEV; return blkaddr;
/* This message is accepted only if sent from CPT PF/VF */ /* This message is accepted only if sent from CPT PF/VF */
if (!is_cpt_pf(rvu, req->hdr.pcifunc) && if (!is_cpt_pf(rvu, req->hdr.pcifunc) &&
...@@ -250,6 +264,47 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, ...@@ -250,6 +264,47 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
return 0; return 0;
} }
#define RXC_ZOMBIE_THRES GENMASK_ULL(59, 48)
#define RXC_ZOMBIE_LIMIT GENMASK_ULL(43, 32)
#define RXC_ACTIVE_THRES GENMASK_ULL(27, 16)
#define RXC_ACTIVE_LIMIT GENMASK_ULL(11, 0)
#define RXC_ACTIVE_COUNT GENMASK_ULL(60, 48)
#define RXC_ZOMBIE_COUNT GENMASK_ULL(60, 48)
static void cpt_rxc_time_cfg(struct rvu *rvu, struct cpt_rxc_time_cfg_req *req,
int blkaddr)
{
u64 dfrg_reg;
dfrg_reg = FIELD_PREP(RXC_ZOMBIE_THRES, req->zombie_thres);
dfrg_reg |= FIELD_PREP(RXC_ZOMBIE_LIMIT, req->zombie_limit);
dfrg_reg |= FIELD_PREP(RXC_ACTIVE_THRES, req->active_thres);
dfrg_reg |= FIELD_PREP(RXC_ACTIVE_LIMIT, req->active_limit);
rvu_write64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG, req->step);
rvu_write64(rvu, blkaddr, CPT_AF_RXC_DFRG, dfrg_reg);
}
int rvu_mbox_handler_cpt_rxc_time_cfg(struct rvu *rvu,
struct cpt_rxc_time_cfg_req *req,
struct msg_rsp *rsp)
{
int blkaddr;
blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
if (blkaddr < 0)
return blkaddr;
/* This message is accepted only if sent from CPT PF/VF */
if (!is_cpt_pf(rvu, req->hdr.pcifunc) &&
!is_cpt_vf(rvu, req->hdr.pcifunc))
return CPT_AF_ERR_ACCESS_DENIED;
cpt_rxc_time_cfg(rvu, req, blkaddr);
return 0;
}
#define INPROG_INFLIGHT(reg) ((reg) & 0x1FF) #define INPROG_INFLIGHT(reg) ((reg) & 0x1FF)
#define INPROG_GRB_PARTIAL(reg) ((reg) & BIT_ULL(31)) #define INPROG_GRB_PARTIAL(reg) ((reg) & BIT_ULL(31))
#define INPROG_GRB(reg) (((reg) >> 32) & 0xFF) #define INPROG_GRB(reg) (((reg) >> 32) & 0xFF)
......
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