Commit ed712d30 authored by Robert Foss's avatar Robert Foss

Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting"

Revert this patch since it depends on devicetree functionality that
previously has been reverted in the below commit.

commit e798ba33 ("Revert "dt-bindings: Add byteswap order to chrontel ch7033"")

This reverts commit ce9564cf.
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220919102009.150503-3-robert.foss@linaro.org
parent f47f537c
...@@ -68,7 +68,6 @@ enum { ...@@ -68,7 +68,6 @@ enum {
BYTE_SWAP_GBR = 3, BYTE_SWAP_GBR = 3,
BYTE_SWAP_BRG = 4, BYTE_SWAP_BRG = 4,
BYTE_SWAP_BGR = 5, BYTE_SWAP_BGR = 5,
BYTE_SWAP_MAX = 6,
}; };
/* Page 0, Register 0x19 */ /* Page 0, Register 0x19 */
...@@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, ...@@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
int hsynclen = mode->hsync_end - mode->hsync_start; int hsynclen = mode->hsync_end - mode->hsync_start;
int vbporch = mode->vsync_start - mode->vdisplay; int vbporch = mode->vsync_start - mode->vdisplay;
int vsynclen = mode->vsync_end - mode->vsync_start; int vsynclen = mode->vsync_end - mode->vsync_start;
u8 byte_swap;
int ret;
/* /*
* Page 4 * Page 4
...@@ -401,15 +398,7 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, ...@@ -401,15 +398,7 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
regmap_write(priv->regmap, 0x15, vbporch); regmap_write(priv->regmap, 0x15, vbporch);
regmap_write(priv->regmap, 0x16, vsynclen); regmap_write(priv->regmap, 0x16, vsynclen);
/* Input color swap. Byte order is optional and will default to /* Input color swap. */
* BYTE_SWAP_BGR to preserve backwards compatibility with existing
* driver.
*/
ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
&byte_swap);
if (!ret && byte_swap < BYTE_SWAP_MAX)
regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
else
regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
/* Input clock and sync polarity. */ /* Input clock and sync polarity. */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment