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Commit ef222347 authored by David Mosberger's avatar David Mosberger
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ia64: Various updates: ia32 subsystem fix, tracing-support for mmu-context switching, 

	etc.
parent fb4291ac
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Showing with 201 additions and 110 deletions
arch/ia64/ia32/sys_ia32.c
View file @ ef222347
...@@ -2010,6 +2010,10 @@ semctl32 (int first, int second, int third, void *uptr) ...@@ -2010,6 +2010,10 @@ semctl32 (int first, int second, int third, void *uptr)
else else
fourth.__pad = (void *)A(pad); fourth.__pad = (void *)A(pad);
switch (third) { switch (third) {
default:
err = -EINVAL;
break;
case IPC_INFO: case IPC_INFO:
case IPC_RMID: case IPC_RMID:
case IPC_SET: case IPC_SET:
......
arch/ia64/kernel/acpi.c
View file @ ef222347
...@@ -888,4 +888,26 @@ acpi_irq_to_vector (u32 irq) ...@@ -888,4 +888,26 @@ acpi_irq_to_vector (u32 irq)
return gsi_to_vector(irq); return gsi_to_vector(irq);
} }
int __init
acpi_register_irq (u32 gsi, u32 polarity, u32 trigger)
{
int vector = 0;
u32 irq_base;
char *iosapic_address;
if (acpi_madt->flags.pcat_compat && (gsi < 16))
return isa_irq_to_vector(gsi);
if (!iosapic_register_intr)
return 0;
/* Find the IOSAPIC */
if (!acpi_find_iosapic(gsi, &irq_base, &iosapic_address)) {
/* Turn it on */
vector = iosapic_register_intr (gsi, polarity, trigger,
irq_base, iosapic_address);
}
return vector;
}
#endif /* CONFIG_ACPI_BOOT */ #endif /* CONFIG_ACPI_BOOT */
arch/ia64/kernel/ivt.S
View file @ ef222347
...@@ -192,7 +192,7 @@ ENTRY(vhpt_miss) ...@@ -192,7 +192,7 @@ ENTRY(vhpt_miss)
rfi rfi
END(vhpt_miss) END(vhpt_miss)
.align 1024 .org ia64_ivt+0x400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x0400 Entry 1 (size 64 bundles) ITLB (21) // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
ENTRY(itlb_miss) ENTRY(itlb_miss)
...@@ -206,7 +206,7 @@ ENTRY(itlb_miss) ...@@ -206,7 +206,7 @@ ENTRY(itlb_miss)
mov r16=cr.ifa // get virtual address mov r16=cr.ifa // get virtual address
mov r29=b0 // save b0 mov r29=b0 // save b0
mov r31=pr // save predicates mov r31=pr // save predicates
itlb_fault: .itlb_fault:
mov r17=cr.iha // get virtual address of L3 PTE mov r17=cr.iha // get virtual address of L3 PTE
movl r30=1f // load nested fault continuation point movl r30=1f // load nested fault continuation point
;; ;;
...@@ -230,7 +230,7 @@ itlb_fault: ...@@ -230,7 +230,7 @@ itlb_fault:
rfi rfi
END(itlb_miss) END(itlb_miss)
.align 1024 .org ia64_ivt+0x0800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
ENTRY(dtlb_miss) ENTRY(dtlb_miss)
...@@ -268,7 +268,7 @@ dtlb_fault: ...@@ -268,7 +268,7 @@ dtlb_fault:
rfi rfi
END(dtlb_miss) END(dtlb_miss)
.align 1024 .org ia64_ivt+0x0c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
ENTRY(alt_itlb_miss) ENTRY(alt_itlb_miss)
...@@ -288,7 +288,7 @@ ENTRY(alt_itlb_miss) ...@@ -288,7 +288,7 @@ ENTRY(alt_itlb_miss)
;; ;;
(p8) mov cr.iha=r17 (p8) mov cr.iha=r17
(p8) mov r29=b0 // save b0 (p8) mov r29=b0 // save b0
(p8) br.cond.dptk itlb_fault (p8) br.cond.dptk .itlb_fault
#endif #endif
extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
and r19=r19,r16 // clear ed, reserved bits, and PTE control bits and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
...@@ -306,7 +306,7 @@ ENTRY(alt_itlb_miss) ...@@ -306,7 +306,7 @@ ENTRY(alt_itlb_miss)
rfi rfi
END(alt_itlb_miss) END(alt_itlb_miss)
.align 1024 .org ia64_ivt+0x1000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
ENTRY(alt_dtlb_miss) ENTRY(alt_dtlb_miss)
...@@ -379,7 +379,7 @@ ENTRY(page_fault) ...@@ -379,7 +379,7 @@ ENTRY(page_fault)
br.call.sptk.many b6=ia64_do_page_fault // ignore return address br.call.sptk.many b6=ia64_do_page_fault // ignore return address
END(page_fault) END(page_fault)
.align 1024 .org ia64_ivt+0x1400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45) // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
ENTRY(nested_dtlb_miss) ENTRY(nested_dtlb_miss)
...@@ -440,7 +440,7 @@ ENTRY(nested_dtlb_miss) ...@@ -440,7 +440,7 @@ ENTRY(nested_dtlb_miss)
br.sptk.many b0 // return to continuation point br.sptk.many b0 // return to continuation point
END(nested_dtlb_miss) END(nested_dtlb_miss)
.align 1024 .org ia64_ivt+0x1800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
ENTRY(ikey_miss) ENTRY(ikey_miss)
...@@ -448,7 +448,7 @@ ENTRY(ikey_miss) ...@@ -448,7 +448,7 @@ ENTRY(ikey_miss)
FAULT(6) FAULT(6)
END(ikey_miss) END(ikey_miss)
.align 1024 .org ia64_ivt+0x1c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
ENTRY(dkey_miss) ENTRY(dkey_miss)
...@@ -456,7 +456,7 @@ ENTRY(dkey_miss) ...@@ -456,7 +456,7 @@ ENTRY(dkey_miss)
FAULT(7) FAULT(7)
END(dkey_miss) END(dkey_miss)
.align 1024 .org ia64_ivt+0x2000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
ENTRY(dirty_bit) ENTRY(dirty_bit)
...@@ -512,7 +512,7 @@ ENTRY(dirty_bit) ...@@ -512,7 +512,7 @@ ENTRY(dirty_bit)
rfi rfi
END(idirty_bit) END(idirty_bit)
.align 1024 .org ia64_ivt+0x2400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
ENTRY(iaccess_bit) ENTRY(iaccess_bit)
...@@ -571,7 +571,7 @@ ENTRY(iaccess_bit) ...@@ -571,7 +571,7 @@ ENTRY(iaccess_bit)
rfi rfi
END(iaccess_bit) END(iaccess_bit)
.align 1024 .org ia64_ivt+0x2800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
ENTRY(daccess_bit) ENTRY(daccess_bit)
...@@ -618,7 +618,7 @@ ENTRY(daccess_bit) ...@@ -618,7 +618,7 @@ ENTRY(daccess_bit)
rfi rfi
END(daccess_bit) END(daccess_bit)
.align 1024 .org ia64_ivt+0x2c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33) // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
ENTRY(break_fault) ENTRY(break_fault)
...@@ -690,7 +690,7 @@ ENTRY(break_fault) ...@@ -690,7 +690,7 @@ ENTRY(break_fault)
// NOT REACHED // NOT REACHED
END(break_fault) END(break_fault)
ENTRY(demine_args) ENTRY_MIN_ALIGN(demine_args)
alloc r2=ar.pfs,8,0,0,0 alloc r2=ar.pfs,8,0,0,0
tnat.nz p8,p0=in0 tnat.nz p8,p0=in0
tnat.nz p9,p0=in1 tnat.nz p9,p0=in1
...@@ -719,7 +719,7 @@ ENTRY(demine_args) ...@@ -719,7 +719,7 @@ ENTRY(demine_args)
br.ret.sptk.many rp br.ret.sptk.many rp
END(demine_args) END(demine_args)
.align 1024 .org ia64_ivt+0x3000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
ENTRY(interrupt) ENTRY(interrupt)
...@@ -746,19 +746,19 @@ ENTRY(interrupt) ...@@ -746,19 +746,19 @@ ENTRY(interrupt)
br.call.sptk.many b6=ia64_handle_irq br.call.sptk.many b6=ia64_handle_irq
END(interrupt) END(interrupt)
.align 1024 .org ia64_ivt+3400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x3400 Entry 13 (size 64 bundles) Reserved // 0x3400 Entry 13 (size 64 bundles) Reserved
DBG_FAULT(13) DBG_FAULT(13)
FAULT(13) FAULT(13)
.align 1024 .org ia64_ivt+3800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x3800 Entry 14 (size 64 bundles) Reserved // 0x3800 Entry 14 (size 64 bundles) Reserved
DBG_FAULT(14) DBG_FAULT(14)
FAULT(14) FAULT(14)
.align 1024 .org ia64_ivt+3c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x3c00 Entry 15 (size 64 bundles) Reserved // 0x3c00 Entry 15 (size 64 bundles) Reserved
DBG_FAULT(15) DBG_FAULT(15)
...@@ -803,7 +803,7 @@ ENTRY(dispatch_illegal_op_fault) ...@@ -803,7 +803,7 @@ ENTRY(dispatch_illegal_op_fault)
br.sptk.many ia64_leave_kernel br.sptk.many ia64_leave_kernel
END(dispatch_illegal_op_fault) END(dispatch_illegal_op_fault)
.align 1024 .org ia64_ivt+0x4000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x4000 Entry 16 (size 64 bundles) Reserved // 0x4000 Entry 16 (size 64 bundles) Reserved
DBG_FAULT(16) DBG_FAULT(16)
...@@ -893,7 +893,7 @@ END(dispatch_to_ia32_handler) ...@@ -893,7 +893,7 @@ END(dispatch_to_ia32_handler)
#endif /* CONFIG_IA32_SUPPORT */ #endif /* CONFIG_IA32_SUPPORT */
.align 1024 .org ia64_ivt+4400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x4400 Entry 17 (size 64 bundles) Reserved // 0x4400 Entry 17 (size 64 bundles) Reserved
DBG_FAULT(17) DBG_FAULT(17)
...@@ -925,7 +925,7 @@ ENTRY(non_syscall) ...@@ -925,7 +925,7 @@ ENTRY(non_syscall)
br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
END(non_syscall) END(non_syscall)
.align 1024 .org ia64_ivt+4800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x4800 Entry 18 (size 64 bundles) Reserved // 0x4800 Entry 18 (size 64 bundles) Reserved
DBG_FAULT(18) DBG_FAULT(18)
...@@ -959,7 +959,7 @@ ENTRY(dispatch_unaligned_handler) ...@@ -959,7 +959,7 @@ ENTRY(dispatch_unaligned_handler)
br.sptk.many ia64_prepare_handle_unaligned br.sptk.many ia64_prepare_handle_unaligned
END(dispatch_unaligned_handler) END(dispatch_unaligned_handler)
.align 1024 .org ia64_ivt+4c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x4c00 Entry 19 (size 64 bundles) Reserved // 0x4c00 Entry 19 (size 64 bundles) Reserved
DBG_FAULT(19) DBG_FAULT(19)
...@@ -1005,7 +1005,7 @@ END(dispatch_to_fault_handler) ...@@ -1005,7 +1005,7 @@ END(dispatch_to_fault_handler)
// --- End of long entries, Beginning of short entries // --- End of long entries, Beginning of short entries
// //
.align 1024 .org ia64_ivt+5000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
ENTRY(page_not_present) ENTRY(page_not_present)
...@@ -1025,7 +1025,7 @@ ENTRY(page_not_present) ...@@ -1025,7 +1025,7 @@ ENTRY(page_not_present)
br.sptk.many page_fault br.sptk.many page_fault
END(page_not_present) END(page_not_present)
.align 256 .org ia64_ivt+5100
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
ENTRY(key_permission) ENTRY(key_permission)
...@@ -1038,7 +1038,7 @@ ENTRY(key_permission) ...@@ -1038,7 +1038,7 @@ ENTRY(key_permission)
br.sptk.many page_fault br.sptk.many page_fault
END(key_permission) END(key_permission)
.align 256 .org ia64_ivt+5200
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
ENTRY(iaccess_rights) ENTRY(iaccess_rights)
...@@ -1051,7 +1051,7 @@ ENTRY(iaccess_rights) ...@@ -1051,7 +1051,7 @@ ENTRY(iaccess_rights)
br.sptk.many page_fault br.sptk.many page_fault
END(iaccess_rights) END(iaccess_rights)
.align 256 .org ia64_ivt+5300
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
ENTRY(daccess_rights) ENTRY(daccess_rights)
...@@ -1064,7 +1064,7 @@ ENTRY(daccess_rights) ...@@ -1064,7 +1064,7 @@ ENTRY(daccess_rights)
br.sptk.many page_fault br.sptk.many page_fault
END(daccess_rights) END(daccess_rights)
.align 256 .org ia64_ivt+5400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39) // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
ENTRY(general_exception) ENTRY(general_exception)
...@@ -1079,7 +1079,7 @@ ENTRY(general_exception) ...@@ -1079,7 +1079,7 @@ ENTRY(general_exception)
br.sptk.many dispatch_to_fault_handler br.sptk.many dispatch_to_fault_handler
END(general_exception) END(general_exception)
.align 256 .org ia64_ivt+5500
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
ENTRY(disabled_fp_reg) ENTRY(disabled_fp_reg)
...@@ -1092,7 +1092,7 @@ ENTRY(disabled_fp_reg) ...@@ -1092,7 +1092,7 @@ ENTRY(disabled_fp_reg)
br.sptk.many dispatch_to_fault_handler br.sptk.many dispatch_to_fault_handler
END(disabled_fp_reg) END(disabled_fp_reg)
.align 256 .org ia64_ivt+5600
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
ENTRY(nat_consumption) ENTRY(nat_consumption)
...@@ -1100,7 +1100,7 @@ ENTRY(nat_consumption) ...@@ -1100,7 +1100,7 @@ ENTRY(nat_consumption)
FAULT(26) FAULT(26)
END(nat_consumption) END(nat_consumption)
.align 256 .org ia64_ivt+5700
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5700 Entry 27 (size 16 bundles) Speculation (40) // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
ENTRY(speculation_vector) ENTRY(speculation_vector)
...@@ -1137,13 +1137,13 @@ ENTRY(speculation_vector) ...@@ -1137,13 +1137,13 @@ ENTRY(speculation_vector)
rfi // and go back rfi // and go back
END(speculation_vector) END(speculation_vector)
.align 256 .org ia64_ivt+5800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5800 Entry 28 (size 16 bundles) Reserved // 0x5800 Entry 28 (size 16 bundles) Reserved
DBG_FAULT(28) DBG_FAULT(28)
FAULT(28) FAULT(28)
.align 256 .org ia64_ivt+5900
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
ENTRY(debug_vector) ENTRY(debug_vector)
...@@ -1151,7 +1151,7 @@ ENTRY(debug_vector) ...@@ -1151,7 +1151,7 @@ ENTRY(debug_vector)
FAULT(29) FAULT(29)
END(debug_vector) END(debug_vector)
.align 256 .org ia64_ivt+5a00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
ENTRY(unaligned_access) ENTRY(unaligned_access)
...@@ -1162,91 +1162,103 @@ ENTRY(unaligned_access) ...@@ -1162,91 +1162,103 @@ ENTRY(unaligned_access)
br.sptk.many dispatch_unaligned_handler br.sptk.many dispatch_unaligned_handler
END(unaligned_access) END(unaligned_access)
.align 256 .org ia64_ivt+5b00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
ENTRY(unsupported_data_reference)
DBG_FAULT(31) DBG_FAULT(31)
FAULT(31) FAULT(31)
END(unsupported_data_reference)
.align 256 .org ia64_ivt+5c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
ENTRY(floating_point_fault)
DBG_FAULT(32) DBG_FAULT(32)
FAULT(32) FAULT(32)
END(floating_point_fault)
.align 256 .org ia64_ivt+5d00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
ENTRY(floating_point_trap)
DBG_FAULT(33) DBG_FAULT(33)
FAULT(33) FAULT(33)
END(floating_point_trap)
.align 256 .org ia64_ivt+5e00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Tranfer Trap (66) // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
ENTRY(lower_privilege_trap)
DBG_FAULT(34) DBG_FAULT(34)
FAULT(34) FAULT(34)
END(lower_privilege_trap)
.align 256 .org ia64_ivt+5f00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
ENTRY(taken_branch_trap)
DBG_FAULT(35) DBG_FAULT(35)
FAULT(35) FAULT(35)
END(taken_branch_trap)
.align 256 .org ia64_ivt+6000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
ENTRY(single_step_trap)
DBG_FAULT(36) DBG_FAULT(36)
FAULT(36) FAULT(36)
END(single_step_trap)
.align 256 .org ia64_ivt+6100
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6100 Entry 37 (size 16 bundles) Reserved // 0x6100 Entry 37 (size 16 bundles) Reserved
DBG_FAULT(37) DBG_FAULT(37)
FAULT(37) FAULT(37)
.align 256 .org ia64_ivt+6200
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6200 Entry 38 (size 16 bundles) Reserved // 0x6200 Entry 38 (size 16 bundles) Reserved
DBG_FAULT(38) DBG_FAULT(38)
FAULT(38) FAULT(38)
.align 256 .org ia64_ivt+6300
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6300 Entry 39 (size 16 bundles) Reserved // 0x6300 Entry 39 (size 16 bundles) Reserved
DBG_FAULT(39) DBG_FAULT(39)
FAULT(39) FAULT(39)
.align 256 .org ia64_ivt+6400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6400 Entry 40 (size 16 bundles) Reserved // 0x6400 Entry 40 (size 16 bundles) Reserved
DBG_FAULT(40) DBG_FAULT(40)
FAULT(40) FAULT(40)
.align 256 .org ia64_ivt+6500
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6500 Entry 41 (size 16 bundles) Reserved // 0x6500 Entry 41 (size 16 bundles) Reserved
DBG_FAULT(41) DBG_FAULT(41)
FAULT(41) FAULT(41)
.align 256 .org ia64_ivt+6600
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6600 Entry 42 (size 16 bundles) Reserved // 0x6600 Entry 42 (size 16 bundles) Reserved
DBG_FAULT(42) DBG_FAULT(42)
FAULT(42) FAULT(42)
.align 256 .org ia64_ivt+6700
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6700 Entry 43 (size 16 bundles) Reserved // 0x6700 Entry 43 (size 16 bundles) Reserved
DBG_FAULT(43) DBG_FAULT(43)
FAULT(43) FAULT(43)
.align 256 .org ia64_ivt+6800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6800 Entry 44 (size 16 bundles) Reserved // 0x6800 Entry 44 (size 16 bundles) Reserved
DBG_FAULT(44) DBG_FAULT(44)
FAULT(44) FAULT(44)
.align 256 .org ia64_ivt+6900
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
ENTRY(ia32_exception) ENTRY(ia32_exception)
...@@ -1254,7 +1266,7 @@ ENTRY(ia32_exception) ...@@ -1254,7 +1266,7 @@ ENTRY(ia32_exception)
FAULT(45) FAULT(45)
END(ia32_exception) END(ia32_exception)
.align 256 .org ia64_ivt+6a00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
ENTRY(ia32_intercept) ENTRY(ia32_intercept)
...@@ -1284,7 +1296,7 @@ ENTRY(ia32_intercept) ...@@ -1284,7 +1296,7 @@ ENTRY(ia32_intercept)
FAULT(46) FAULT(46)
END(ia32_intercept) END(ia32_intercept)
.align 256 .org ia64_ivt+6b00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
ENTRY(ia32_interrupt) ENTRY(ia32_interrupt)
...@@ -1297,121 +1309,121 @@ ENTRY(ia32_interrupt) ...@@ -1297,121 +1309,121 @@ ENTRY(ia32_interrupt)
#endif #endif
END(ia32_interrupt) END(ia32_interrupt)
.align 256 .org ia64_ivt+6c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6c00 Entry 48 (size 16 bundles) Reserved // 0x6c00 Entry 48 (size 16 bundles) Reserved
DBG_FAULT(48) DBG_FAULT(48)
FAULT(48) FAULT(48)
.align 256 .org ia64_ivt+6d00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6d00 Entry 49 (size 16 bundles) Reserved // 0x6d00 Entry 49 (size 16 bundles) Reserved
DBG_FAULT(49) DBG_FAULT(49)
FAULT(49) FAULT(49)
.align 256 .org ia64_ivt+6e00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6e00 Entry 50 (size 16 bundles) Reserved // 0x6e00 Entry 50 (size 16 bundles) Reserved
DBG_FAULT(50) DBG_FAULT(50)
FAULT(50) FAULT(50)
.align 256 .org ia64_ivt+6f00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x6f00 Entry 51 (size 16 bundles) Reserved // 0x6f00 Entry 51 (size 16 bundles) Reserved
DBG_FAULT(51) DBG_FAULT(51)
FAULT(51) FAULT(51)
.align 256 .org ia64_ivt+7000
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7000 Entry 52 (size 16 bundles) Reserved // 0x7000 Entry 52 (size 16 bundles) Reserved
DBG_FAULT(52) DBG_FAULT(52)
FAULT(52) FAULT(52)
.align 256 .org ia64_ivt+7100
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7100 Entry 53 (size 16 bundles) Reserved // 0x7100 Entry 53 (size 16 bundles) Reserved
DBG_FAULT(53) DBG_FAULT(53)
FAULT(53) FAULT(53)
.align 256 .org ia64_ivt+7200
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7200 Entry 54 (size 16 bundles) Reserved // 0x7200 Entry 54 (size 16 bundles) Reserved
DBG_FAULT(54) DBG_FAULT(54)
FAULT(54) FAULT(54)
.align 256 .org ia64_ivt+7300
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7300 Entry 55 (size 16 bundles) Reserved // 0x7300 Entry 55 (size 16 bundles) Reserved
DBG_FAULT(55) DBG_FAULT(55)
FAULT(55) FAULT(55)
.align 256 .org ia64_ivt+7400
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7400 Entry 56 (size 16 bundles) Reserved // 0x7400 Entry 56 (size 16 bundles) Reserved
DBG_FAULT(56) DBG_FAULT(56)
FAULT(56) FAULT(56)
.align 256 .org ia64_ivt+7500
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7500 Entry 57 (size 16 bundles) Reserved // 0x7500 Entry 57 (size 16 bundles) Reserved
DBG_FAULT(57) DBG_FAULT(57)
FAULT(57) FAULT(57)
.align 256 .org ia64_ivt+7600
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7600 Entry 58 (size 16 bundles) Reserved // 0x7600 Entry 58 (size 16 bundles) Reserved
DBG_FAULT(58) DBG_FAULT(58)
FAULT(58) FAULT(58)
.align 256 .org ia64_ivt+7700
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7700 Entry 59 (size 16 bundles) Reserved // 0x7700 Entry 59 (size 16 bundles) Reserved
DBG_FAULT(59) DBG_FAULT(59)
FAULT(59) FAULT(59)
.align 256 .org ia64_ivt+7800
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7800 Entry 60 (size 16 bundles) Reserved // 0x7800 Entry 60 (size 16 bundles) Reserved
DBG_FAULT(60) DBG_FAULT(60)
FAULT(60) FAULT(60)
.align 256 .org ia64_ivt+7900
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7900 Entry 61 (size 16 bundles) Reserved // 0x7900 Entry 61 (size 16 bundles) Reserved
DBG_FAULT(61) DBG_FAULT(61)
FAULT(61) FAULT(61)
.align 256 .org ia64_ivt+7a00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7a00 Entry 62 (size 16 bundles) Reserved // 0x7a00 Entry 62 (size 16 bundles) Reserved
DBG_FAULT(62) DBG_FAULT(62)
FAULT(62) FAULT(62)
.align 256 .org ia64_ivt+7b00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7b00 Entry 63 (size 16 bundles) Reserved // 0x7b00 Entry 63 (size 16 bundles) Reserved
DBG_FAULT(63) DBG_FAULT(63)
FAULT(63) FAULT(63)
.align 256 .org ia64_ivt+7c00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7c00 Entry 64 (size 16 bundles) Reserved // 0x7c00 Entry 64 (size 16 bundles) Reserved
DBG_FAULT(64) DBG_FAULT(64)
FAULT(64) FAULT(64)
.align 256 .org ia64_ivt+7d00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7d00 Entry 65 (size 16 bundles) Reserved // 0x7d00 Entry 65 (size 16 bundles) Reserved
DBG_FAULT(65) DBG_FAULT(65)
FAULT(65) FAULT(65)
.align 256 .org ia64_ivt+7e00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7e00 Entry 66 (size 16 bundles) Reserved // 0x7e00 Entry 66 (size 16 bundles) Reserved
DBG_FAULT(66) DBG_FAULT(66)
FAULT(66) FAULT(66)
.align 256 .org ia64_ivt+7f00
///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////
// 0x7f00 Entry 67 (size 16 bundles) Reserved // 0x7f00 Entry 67 (size 16 bundles) Reserved
DBG_FAULT(67) DBG_FAULT(67)
......
arch/ia64/kernel/pal.S
View file @ ef222347
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* *
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com> * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
* Copyright (C) 1999 Walt Drummond <drummond@valinux.com> * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
* Copyright (C) 1999-2001 Hewlett-Packard Co * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
* David Mosberger <davidm@hpl.hp.com> * David Mosberger <davidm@hpl.hp.com>
* Stephane Eranian <eranian@hpl.hp.com> * Stephane Eranian <eranian@hpl.hp.com>
* *
...@@ -131,11 +131,11 @@ END(ia64_pal_call_stacked) ...@@ -131,11 +131,11 @@ END(ia64_pal_call_stacked)
* in0 Index of PAL service * in0 Index of PAL service
* in2 - in3 Remaning PAL arguments * in2 - in3 Remaning PAL arguments
* *
* PSR_DB, PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel. * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
* So we don't need to clear them. * So we don't need to clear them.
*/ */
#define PAL_PSR_BITS_TO_CLEAR \ #define PAL_PSR_BITS_TO_CLEAR \
(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_RT | \ (IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB | IA64_PSR_RT | \
IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \ IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \
IA64_PSR_DFL | IA64_PSR_DFH) IA64_PSR_DFL | IA64_PSR_DFH)
...@@ -275,7 +275,6 @@ END(ia64_save_scratch_fpregs) ...@@ -275,7 +275,6 @@ END(ia64_save_scratch_fpregs)
* Inputs: * Inputs:
* in0 Address of stack storage for fp regs * in0 Address of stack storage for fp regs
*/ */
GLOBAL_ENTRY(ia64_load_scratch_fpregs) GLOBAL_ENTRY(ia64_load_scratch_fpregs)
alloc r3=ar.pfs,1,0,0,0 alloc r3=ar.pfs,1,0,0,0
add r2=16,in0 add r2=16,in0
......
arch/ia64/kernel/process.c
View file @ ef222347
...@@ -96,7 +96,7 @@ show_regs (struct pt_regs *regs) ...@@ -96,7 +96,7 @@ show_regs (struct pt_regs *regs)
{ {
unsigned long ip = regs->cr_iip + ia64_psr(regs)->ri; unsigned long ip = regs->cr_iip + ia64_psr(regs)->ri;
printk("\nPid: %d, comm: %20s\n", current->pid, current->comm); printk("\nPid: %d, CPU %d, comm: %20s\n", current->pid, smp_processor_id(), current->comm);
printk("psr : %016lx ifs : %016lx ip : [<%016lx>] %s\n", printk("psr : %016lx ifs : %016lx ip : [<%016lx>] %s\n",
regs->cr_ipsr, regs->cr_ifs, ip, print_tainted()); regs->cr_ipsr, regs->cr_ifs, ip, print_tainted());
print_symbol("ip is at %s\n", ip); print_symbol("ip is at %s\n", ip);
......
arch/ia64/kernel/ptrace.c
View file @ ef222347
...@@ -834,20 +834,18 @@ access_uarea (struct task_struct *child, unsigned long addr, unsigned long *data ...@@ -834,20 +834,18 @@ access_uarea (struct task_struct *child, unsigned long addr, unsigned long *data
} }
#ifdef CONFIG_PERFMON #ifdef CONFIG_PERFMON
/* /*
* Check if debug registers are used * Check if debug registers are used by perfmon. This test must be done
* by perfmon. This test must be done once we know that we can * once we know that we can do the operation, i.e. the arguments are all
* do the operation, i.e. the arguments are all valid, but before * valid, but before we start modifying the state.
* we start modifying the state.
* *
* Perfmon needs to keep a count of how many processes are * Perfmon needs to keep a count of how many processes are trying to
* trying to modify the debug registers for system wide monitoring * modify the debug registers for system wide monitoring sessions.
* sessions.
* *
* We also include read access here, because they may cause * We also include read access here, because they may cause the
* the PMU-installed debug register state (dbr[], ibr[]) to * PMU-installed debug register state (dbr[], ibr[]) to be reset. The two
* be reset. The two arrays are also used by perfmon, but * arrays are also used by perfmon, but we do not use
* we do not use IA64_THREAD_DBG_VALID. The registers are restored * IA64_THREAD_DBG_VALID. The registers are restored by the PMU context
* by the PMU context switch code. * switch code.
*/ */
if (pfm_use_debug_registers(child)) return -1; if (pfm_use_debug_registers(child)) return -1;
#endif #endif
......
arch/ia64/vmlinux.lds.S
View file @ ef222347
...@@ -142,10 +142,6 @@ SECTIONS ...@@ -142,10 +142,6 @@ SECTIONS
.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - PAGE_OFFSET) .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - PAGE_OFFSET)
{ *(.data.cacheline_aligned) } { *(.data.cacheline_aligned) }
/* Kernel symbol names for modules: */
.kstrtab : AT(ADDR(.kstrtab) - PAGE_OFFSET)
{ *(.kstrtab) }
/* Per-cpu data: */ /* Per-cpu data: */
. = ALIGN(PERCPU_PAGE_SIZE); . = ALIGN(PERCPU_PAGE_SIZE);
__phys_per_cpu_start = .; __phys_per_cpu_start = .;
......
include/asm-ia64/mmu_context.h
View file @ ef222347
...@@ -28,6 +28,36 @@ ...@@ -28,6 +28,36 @@
#include <asm/processor.h> #include <asm/processor.h>
#define MMU_CONTEXT_DEBUG 0
#if MMU_CONTEXT_DEBUG
#include <ia64intrin.h>
extern struct mmu_trace_entry {
char op;
u8 cpu;
u32 context;
void *mm;
} mmu_tbuf[1024];
extern volatile int mmu_tbuf_index;
# define MMU_TRACE(_op,_cpu,_mm,_ctx) \
do { \
int i = __sync_fetch_and_add(&mmu_tbuf_index, 1) % ARRAY_SIZE(mmu_tbuf); \
struct mmu_trace_entry e; \
e.op = (_op); \
e.cpu = (_cpu); \
e.mm = (_mm); \
e.context = (_ctx); \
mmu_tbuf[i] = e; \
} while (0)
#else
# define MMU_TRACE(op,cpu,mm,ctx) do { ; } while (0)
#endif
struct ia64_ctx { struct ia64_ctx {
spinlock_t lock; spinlock_t lock;
unsigned int next; /* next context number to use */ unsigned int next; /* next context number to use */
...@@ -91,6 +121,7 @@ get_mmu_context (struct mm_struct *mm) ...@@ -91,6 +121,7 @@ get_mmu_context (struct mm_struct *mm)
static inline int static inline int
init_new_context (struct task_struct *p, struct mm_struct *mm) init_new_context (struct task_struct *p, struct mm_struct *mm)
{ {
MMU_TRACE('N', smp_processor_id(), mm, 0);
mm->context = 0; mm->context = 0;
return 0; return 0;
} }
...@@ -99,6 +130,7 @@ static inline void ...@@ -99,6 +130,7 @@ static inline void
destroy_context (struct mm_struct *mm) destroy_context (struct mm_struct *mm)
{ {
/* Nothing to do. */ /* Nothing to do. */
MMU_TRACE('D', smp_processor_id(), mm, mm->context);
} }
static inline void static inline void
...@@ -138,7 +170,9 @@ activate_context (struct mm_struct *mm) ...@@ -138,7 +170,9 @@ activate_context (struct mm_struct *mm)
do { do {
context = get_mmu_context(mm); context = get_mmu_context(mm);
MMU_TRACE('A', smp_processor_id(), mm, context);
reload_context(context); reload_context(context);
MMU_TRACE('a', smp_processor_id(), mm, context);
/* in the unlikely event of a TLB-flush by another thread, redo the load: */ /* in the unlikely event of a TLB-flush by another thread, redo the load: */
} while (unlikely(context != mm->context)); } while (unlikely(context != mm->context));
} }
......
include/asm-ia64/spinlock.h
View file @ ef222347
...@@ -74,6 +74,27 @@ typedef struct { ...@@ -74,6 +74,27 @@ typedef struct {
#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
#define spin_lock_init(x) ((x)->lock = 0) #define spin_lock_init(x) ((x)->lock = 0)
#define DEBUG_SPIN_LOCK 0
#if DEBUG_SPIN_LOCK
#include <ia64intrin.h>
#define _raw_spin_lock(x) \
do { \
unsigned long _timeout = 1000000000; \
volatile unsigned int _old = 0, _new = 1, *_ptr = &((x)->lock); \
do { \
if (_timeout-- == 0) { \
extern void dump_stack (void); \
printk("kernel DEADLOCK at %s:%d?\n", __FILE__, __LINE__); \
dump_stack(); \
} \
} while (__sync_val_compare_and_swap(_ptr, _old, _new) != _old); \
} while (0)
#else
/* /*
* Streamlined test_and_set_bit(0, (x)). We use test-and-test-and-set * Streamlined test_and_set_bit(0, (x)). We use test-and-test-and-set
* rather than a simple xchg to avoid writing the cache-line when * rather than a simple xchg to avoid writing the cache-line when
...@@ -95,6 +116,8 @@ typedef struct { ...@@ -95,6 +116,8 @@ typedef struct {
";;\n" \ ";;\n" \
:: "r"(&(x)->lock) : "ar.ccv", "p7", "r2", "r29", "memory") :: "r"(&(x)->lock) : "ar.ccv", "p7", "r2", "r29", "memory")
#endif /* !DEBUG_SPIN_LOCK */
#define spin_is_locked(x) ((x)->lock != 0) #define spin_is_locked(x) ((x)->lock != 0)
#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) #define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
#define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0) #define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
......
include/asm-ia64/tlbflush.h
View file @ ef222347
...@@ -47,19 +47,22 @@ local_finish_flush_tlb_mm (struct mm_struct *mm) ...@@ -47,19 +47,22 @@ local_finish_flush_tlb_mm (struct mm_struct *mm)
static inline void static inline void
flush_tlb_mm (struct mm_struct *mm) flush_tlb_mm (struct mm_struct *mm)
{ {
MMU_TRACE('F', smp_processor_id(), mm, mm->context);
if (!mm) if (!mm)
return; goto out;
mm->context = 0; mm->context = 0;
if (atomic_read(&mm->mm_users) == 0) if (atomic_read(&mm->mm_users) == 0)
return; /* happens as a result of exit_mmap() */ goto out; /* happens as a result of exit_mmap() */
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
smp_flush_tlb_mm(mm); smp_flush_tlb_mm(mm);
#else #else
local_finish_flush_tlb_mm(mm); local_finish_flush_tlb_mm(mm);
#endif #endif
out:
MMU_TRACE('f', smp_processor_id(), mm, mm->context);
} }
extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end);
......
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