Commit f2b0e8bf authored by Markos Chandras's avatar Markos Chandras Committed by Luis Henriques

MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line

commit 83fd4344 upstream.

Commit de8974e3 ("MIPS: asm: r4kcache: Add EVA cache flushing
functions") added cache function for EVA using the cachee instruction.
However, it didn't add a case for the protected_writeback_dcache_line.
mips_dsemul() calls r4k_flush_cache_sigtramp() which in turn uses
the protected_writeback_dcache_line() to flush the trampoline code
back to memory. This used the wrong "cache" instruction leading to
random userland crashes on non-FPU cores.
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8331/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarLuis Henriques <luis.henriques@canonical.com>
parent 67f3e840
...@@ -254,7 +254,11 @@ static inline void protected_flush_icache_line(unsigned long addr) ...@@ -254,7 +254,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
*/ */
static inline void protected_writeback_dcache_line(unsigned long addr) static inline void protected_writeback_dcache_line(unsigned long addr)
{ {
#ifdef CONFIG_EVA
protected_cachee_op(Hit_Writeback_Inv_D, addr);
#else
protected_cache_op(Hit_Writeback_Inv_D, addr); protected_cache_op(Hit_Writeback_Inv_D, addr);
#endif
} }
static inline void protected_writeback_scache_line(unsigned long addr) static inline void protected_writeback_scache_line(unsigned long addr)
......
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