Commit f2d03ba9 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo

arm64: dts: imx93: reorder device nodes

Reorder device nodes per address
 - Move eqos node after fec node
 - Move mediamix node after mlmix node
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5a866baa
...@@ -305,14 +305,6 @@ src: system-controller@44460000 { ...@@ -305,14 +305,6 @@ src: system-controller@44460000 {
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
mediamix: power-domain@44462400 {
compatible = "fsl,imx93-src-slice";
reg = <0x44462400 0x400>, <0x44465800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>;
};
mlmix: power-domain@44461800 { mlmix: power-domain@44461800 {
compatible = "fsl,imx93-src-slice"; compatible = "fsl,imx93-src-slice";
reg = <0x44461800 0x400>, <0x44464800 0x400>; reg = <0x44461800 0x400>, <0x44464800 0x400>;
...@@ -320,6 +312,14 @@ mlmix: power-domain@44461800 { ...@@ -320,6 +312,14 @@ mlmix: power-domain@44461800 {
clocks = <&clk IMX93_CLK_ML_APB>, clocks = <&clk IMX93_CLK_ML_APB>,
<&clk IMX93_CLK_ML>; <&clk IMX93_CLK_ML>;
}; };
mediamix: power-domain@44462400 {
compatible = "fsl,imx93-src-slice";
reg = <0x44462400 0x400>, <0x44465800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>;
};
}; };
anatop: anatop@44480000 { anatop: anatop@44480000 {
...@@ -685,28 +685,6 @@ usdhc2: mmc@42860000 { ...@@ -685,28 +685,6 @@ usdhc2: mmc@42860000 {
status = "disabled"; status = "disabled";
}; };
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_ENET_QOS_GATE>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
status = "disabled";
};
fec: ethernet@42890000 { fec: ethernet@42890000 {
compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x42890000 0x10000>; reg = <0x42890000 0x10000>;
...@@ -733,6 +711,28 @@ fec: ethernet@42890000 { ...@@ -733,6 +711,28 @@ fec: ethernet@42890000 {
status = "disabled"; status = "disabled";
}; };
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_ENET_QOS_GATE>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
status = "disabled";
};
usdhc3: mmc@428b0000 { usdhc3: mmc@428b0000 {
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
reg = <0x428b0000 0x10000>; reg = <0x428b0000 0x10000>;
......
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