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Commit f2e7bfbb authored by Diana Craciun's avatar Diana Craciun Committed by Scott Wood
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powerpc/fsl: Updated device trees for platforms with corenet version 2 

Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: default avatarDiana Craciun <Diana.Craciun@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 385510be
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Inline Side-by-side
Showing with 42 additions and 12 deletions
arch/powerpc/boot/dts/b4860emu.dts
View file @ f2e7bfbb
......@@ -61,21 +61,25 @@ cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
};
};
......@@ -157,7 +161,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,b4-corenet-cf";
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 0>;
fsl,ccf-num-csdids = <32>;
......@@ -167,6 +171,7 @@ corenet-cf@18000 {
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x4000>;
fsl,portid-mapping = <0x8000>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <
......
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
View file @ f2e7bfbb
......@@ -76,10 +76,6 @@ cpc: l3-cache-controller@10000 {
compatible = "fsl,b4420-l3-cache-controller", "cache";
};
corenet-cf@18000 {
compatible = "fsl,b4420-corenet-cf";
};
guts: global-utilities@e0000 {
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
};
......
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
View file @ f2e7bfbb
......@@ -66,12 +66,14 @@ cpu0: PowerPC,e6500@0 {
reg = <0 1>;
clocks = <&mux0>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&mux0>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
};
};
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
View file @ f2e7bfbb
......@@ -120,10 +120,6 @@ cpc: l3-cache-controller@10000 {
compatible = "fsl,b4860-l3-cache-controller", "cache";
};
corenet-cf@18000 {
compatible = "fsl,b4860-corenet-cf";
};
guts: global-utilities@e0000 {
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
};
......
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
View file @ f2e7bfbb
......@@ -66,24 +66,28 @@ cpu0: PowerPC,e6500@0 {
reg = <0 1>;
clocks = <&mux0>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&mux0>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
clocks = <&mux0>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
clocks = <&mux0>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
};
};
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
View file @ f2e7bfbb
......@@ -158,7 +158,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,b4-corenet-cf";
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 0>;
fsl,ccf-num-csdids = <32>;
......@@ -168,6 +168,7 @@ corenet-cf@18000 {
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x4000>;
fsl,portid-mapping = <0x8000>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <
......
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
View file @ f2e7bfbb
......@@ -343,7 +343,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
......@@ -353,6 +353,7 @@ corenet-cf@18000 {
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x6000>;
fsl,portid-mapping = <0x8000>;
interrupts = <
24 2 0 0
16 2 1 30>;
......
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
View file @ f2e7bfbb
......@@ -69,72 +69,84 @@ cpu0: PowerPC,e6500@0 {
reg = <0 1>;
clocks = <&mux0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&mux0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
clocks = <&mux0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
clocks = <&mux0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
clocks = <&mux1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
clocks = <&mux1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
clocks = <&mux1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
clocks = <&mux1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
clocks = <&mux2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
clocks = <&mux2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
clocks = <&mux2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
clocks = <&mux2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
};
};
arch/powerpc/boot/dts/t4240emu.dts
View file @ f2e7bfbb
......@@ -60,63 +60,75 @@ cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
};
};
......@@ -213,7 +225,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
......@@ -223,6 +235,7 @@ corenet-cf@18000 {
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x6000>;
fsl,portid-mapping = <0x8000>;
interrupts = <
24 2 0 0
16 2 1 30>;
......
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