Commit f4e2e9a4 authored by Thomas Gleixner's avatar Thomas Gleixner

xtensa: Use generic idle loop

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: default avatarSrivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: default avatarChris Zankel <chris@zankel.net>
Link: http://lkml.kernel.org/r/20130321215235.546600507@linutronix.deSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 7d1a9417
...@@ -19,6 +19,7 @@ config XTENSA ...@@ -19,6 +19,7 @@ config XTENSA
select CLONE_BACKWARDS select CLONE_BACKWARDS
select IRQ_DOMAIN select IRQ_DOMAIN
select HAVE_OPROFILE select HAVE_OPROFILE
select GENERIC_IDLE_LOOP
help help
Xtensa processors are 32-bit RISC machines designed by Tensilica Xtensa processors are 32-bit RISC machines designed by Tensilica
primarily for embedded systems. These processors are both primarily for embedded systems. These processors are both
......
...@@ -105,19 +105,9 @@ void coprocessor_flush_all(struct thread_info *ti) ...@@ -105,19 +105,9 @@ void coprocessor_flush_all(struct thread_info *ti)
/* /*
* Powermanagement idle function, if any is provided by the platform. * Powermanagement idle function, if any is provided by the platform.
*/ */
void arch_cpu_idle(void)
void cpu_idle(void)
{ {
local_irq_enable();
/* endless idle loop with no priority at all */
while (1) {
rcu_idle_enter();
while (!need_resched())
platform_idle(); platform_idle();
rcu_idle_exit();
schedule_preempt_disabled();
}
} }
/* /*
......
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