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Commit f676d861 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'clk-renesas-for-v4.20-tag1' of... 

Merge tag 'clk-renesas-for-v4.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs,
  - Add support for SATA and Fine Display Processor (FDP) clocks on
    R-Car M3-N,
  - Add support for the new RZ/G2M (r8a774a1) SoC,
  - Small fixes and clean ups.

* tag 'clk-renesas-for-v4.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a77990: Add missing I2C7 clock
  clk: renesas: r8a77965: Add FDP clock
  clk: renesas: cpg-mssr: Add r8a774a1 support
  clk: renesas: Add r8a774a1 CPG Core Clock Definitions
  clk: renesas: r8a77965: Add SATA clock
  clk: renesas: r8a77980: Add RCLK for watchdog timer
  clk: renesas: rcar-gen3: Add support for mode pin clock selection
  clk: renesas: r8a77995: Correct RCLK handling
  clk: renesas: r8a77990: Correct RCLK handling
  clk: renesas: rcar-gen3: Add support for RCKSEL clock selection
  clk: renesas: cpg-mssr: Add support for fixed rate clocks
  clk: renesas: r8a77980: Add OSC predivider configuration and clock
  clk: renesas: r8a77965: Add OSC EXTAL predivider configuration
  clk: renesas: r8a7796: Add OSC EXTAL predivider configuration
  clk: renesas: r8a7795: Add OSC EXTAL predivider configuration
  clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
  clk: renesas: rcar-gen3: Rename rint to .r
parents 5b394b2d b30c862f
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Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
View file @ f676d861
...@@ -16,6 +16,7 @@ Required Properties: ...@@ -16,6 +16,7 @@ Required Properties:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
...@@ -35,10 +36,10 @@ Required Properties: ...@@ -35,10 +36,10 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in - clocks: References to external parent clocks, one entry for each entry in
clock-names clock-names
- clock-names: List of external parent clock names. Valid names are: - clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792, - "extal" (r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790, r8a7791,
r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965,
r8a77980, r8a77990, r8a77995) r8a77970, r8a77980, r8a77990, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
r8a7794) r8a7794)
......
drivers/clk/renesas/Kconfig
View file @ f676d861
...@@ -8,6 +8,7 @@ config CLK_RENESAS ...@@ -8,6 +8,7 @@ config CLK_RENESAS
select CLK_R8A7743 if ARCH_R8A7743 select CLK_R8A7743 if ARCH_R8A7743
select CLK_R8A7745 if ARCH_R8A7745 select CLK_R8A7745 if ARCH_R8A7745
select CLK_R8A77470 if ARCH_R8A77470 select CLK_R8A77470 if ARCH_R8A77470
select CLK_R8A774A1 if ARCH_R8A774A1
select CLK_R8A7778 if ARCH_R8A7778 select CLK_R8A7778 if ARCH_R8A7778
select CLK_R8A7779 if ARCH_R8A7779 select CLK_R8A7779 if ARCH_R8A7779
select CLK_R8A7790 if ARCH_R8A7790 select CLK_R8A7790 if ARCH_R8A7790
...@@ -67,6 +68,10 @@ config CLK_R8A77470 ...@@ -67,6 +68,10 @@ config CLK_R8A77470
bool "RZ/G1C clock support" if COMPILE_TEST bool "RZ/G1C clock support" if COMPILE_TEST
select CLK_RCAR_GEN2_CPG select CLK_RCAR_GEN2_CPG
config CLK_R8A774A1
bool "RZ/G2M clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
config CLK_R8A7778 config CLK_R8A7778
bool "R-Car M1A clock support" if COMPILE_TEST bool "R-Car M1A clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP select CLK_RENESAS_CPG_MSTP
......
drivers/clk/renesas/Makefile
View file @ f676d861
...@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o ...@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
......
drivers/clk/renesas/r8a774a1-cpg-mssr.c 0 → 100644
View file @ f676d861
// SPDX-License-Identifier: GPL-2.0
/*
* r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018 Renesas Electronics Corp.
*
* Based on r8a7796-cpg-mssr.c
*
* Copyright (C) 2016 Glider bvba
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A774A1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A774A1_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A774A1_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A774A1_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A774A1_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4),
DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4),
DEF_MOD("scif0", 207, R8A774A1_CLK_S3D4),
DEF_MOD("msiof3", 208, R8A774A1_CLK_MSO),
DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
DEF_MOD("cmt1", 302, R8A774A1_CLK_R),
DEF_MOD("cmt0", 303, R8A774A1_CLK_R),
DEF_MOD("scif2", 310, R8A774A1_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A774A1_CLK_SD3),
DEF_MOD("sdif2", 312, R8A774A1_CLK_SD2),
DEF_MOD("sdif1", 313, R8A774A1_CLK_SD1),
DEF_MOD("sdif0", 314, R8A774A1_CLK_SD0),
DEF_MOD("pcie1", 318, R8A774A1_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A774A1_CLK_S3D1),
DEF_MOD("usb3-if0", 328, R8A774A1_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A774A1_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A774A1_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
DEF_MOD("hscif1", 519, R8A774A1_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A774A1_CLK_S3D1),
DEF_MOD("thermal", 522, R8A774A1_CLK_CP),
DEF_MOD("pwm", 523, R8A774A1_CLK_S0D12),
DEF_MOD("fcpvd2", 601, R8A774A1_CLK_S0D2),
DEF_MOD("fcpvd1", 602, R8A774A1_CLK_S0D2),
DEF_MOD("fcpvd0", 603, R8A774A1_CLK_S0D2),
DEF_MOD("fcpvb0", 607, R8A774A1_CLK_S0D1),
DEF_MOD("fcpvi0", 611, R8A774A1_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A774A1_CLK_S0D1),
DEF_MOD("fcpci0", 617, R8A774A1_CLK_S0D2),
DEF_MOD("fcpcs", 619, R8A774A1_CLK_S0D2),
DEF_MOD("vspd2", 621, R8A774A1_CLK_S0D2),
DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2),
DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
DEF_MOD("du1", 723, R8A774A1_CLK_S2D1),
DEF_MOD("du0", 724, R8A774A1_CLK_S2D1),
DEF_MOD("lvds", 727, R8A774A1_CLK_S2D1),
DEF_MOD("hdmi0", 729, R8A774A1_CLK_HDMI),
DEF_MOD("vin7", 804, R8A774A1_CLK_S0D2),
DEF_MOD("vin6", 805, R8A774A1_CLK_S0D2),
DEF_MOD("vin5", 806, R8A774A1_CLK_S0D2),
DEF_MOD("vin4", 807, R8A774A1_CLK_S0D2),
DEF_MOD("vin3", 808, R8A774A1_CLK_S0D2),
DEF_MOD("vin2", 809, R8A774A1_CLK_S0D2),
DEF_MOD("vin1", 810, R8A774A1_CLK_S0D2),
DEF_MOD("vin0", 811, R8A774A1_CLK_S0D2),
DEF_MOD("etheravb", 812, R8A774A1_CLK_S0D6),
DEF_MOD("gpio7", 905, R8A774A1_CLK_S3D4),
DEF_MOD("gpio6", 906, R8A774A1_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A774A1_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A774A1_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A774A1_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A774A1_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A774A1_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A774A1_CLK_S3D4),
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A774A1_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A774A1_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A774A1_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A774A1_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a774a1_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz)
*-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, 32, },
};
static int __init r8a774a1_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
return -EINVAL;
}
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a774a1_core_clks,
.num_core_clks = ARRAY_SIZE(r8a774a1_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a774a1_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a774a1_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a774a1_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks),
/* Callbacks */
.init = r8a774a1_cpg_mssr_init,
.cpg_clk_register = rcar_gen3_cpg_clk_register,
};
drivers/clk/renesas/r8a7795-cpg-mssr.c
View file @ f676d861
...@@ -73,6 +73,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { ...@@ -73,6 +73,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
...@@ -111,8 +113,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { ...@@ -111,8 +113,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
}; };
...@@ -283,25 +284,25 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = { ...@@ -283,25 +284,25 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
*/ */
/* /*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz) * 14 13 19 17 (MHz)
*------------------------------------------------------------------- *-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting * 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting * 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting * 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting * 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/ */
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \ (((md) & BIT(13)) >> 11) | \
...@@ -309,23 +310,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = { ...@@ -309,23 +310,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
(((md) & BIT(17)) >> 17)) (((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, }, { 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, }, { 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, }, { 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, }, { 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static const struct soc_device_attribute r8a7795es1[] __initconst = { static const struct soc_device_attribute r8a7795es1[] __initconst = {
......
drivers/clk/renesas/r8a7796-cpg-mssr.c
View file @ f676d861
...@@ -73,6 +73,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { ...@@ -73,6 +73,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
...@@ -110,8 +112,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { ...@@ -110,8 +112,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
}; };
...@@ -255,25 +256,25 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = { ...@@ -255,25 +256,25 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
*/ */
/* /*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz) * 14 13 19 17 (MHz)
*------------------------------------------------------------------- *-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting * 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting * 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting * 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting * 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/ */
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \ (((md) & BIT(13)) >> 11) | \
...@@ -281,23 +282,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = { ...@@ -281,23 +282,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
(((md) & BIT(17)) >> 17)) (((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, }, { 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, }, { 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, }, { 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, }, { 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static int __init r8a7796_cpg_mssr_init(struct device *dev) static int __init r8a7796_cpg_mssr_init(struct device *dev)
......
drivers/clk/renesas/r8a77965-cpg-mssr.c
View file @ f676d861
...@@ -68,6 +68,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { ...@@ -68,6 +68,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
...@@ -104,13 +106,13 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { ...@@ -104,13 +106,13 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
}; };
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
...@@ -192,6 +194,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { ...@@ -192,6 +194,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("vin1", 810, R8A77965_CLK_S0D2), DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
DEF_MOD("vin0", 811, R8A77965_CLK_S0D2), DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6), DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
DEF_MOD("imr1", 822, R8A77965_CLK_S0D2), DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
DEF_MOD("imr0", 823, R8A77965_CLK_S0D2), DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
...@@ -252,25 +255,25 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = { ...@@ -252,25 +255,25 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
*/ */
/* /*
* MD EXTAL PLL0 PLL1 PLL3 PLL4 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
* 14 13 19 17 (MHz) * 14 13 19 17 (MHz)
*----------------------------------------------------------- *-----------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
* 0 0 1 0 Prohibited setting * 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x160 x120 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x106 x120 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
* 0 1 1 0 Prohibited setting * 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x160 x120 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x128 x96 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x84 x96 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
* 1 0 1 0 Prohibited setting * 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x128 x96 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
* 1 1 1 0 Prohibited setting * 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
*/ */
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \ (((md) & BIT(13)) >> 11) | \
...@@ -278,23 +281,23 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = { ...@@ -278,23 +281,23 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
(((md) & BIT(17)) >> 17)) (((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, }, { 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, }, { 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, }, { 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, }, { 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static int __init r8a77965_cpg_mssr_init(struct device *dev) static int __init r8a77965_cpg_mssr_init(struct device *dev)
......
drivers/clk/renesas/r8a77980-cpg-mssr.c
View file @ f676d861
...@@ -41,6 +41,7 @@ enum clk_ids { ...@@ -41,6 +41,7 @@ enum clk_ids {
CLK_S2, CLK_S2,
CLK_S3, CLK_S3,
CLK_SDSRC, CLK_SDSRC,
CLK_OCO,
/* Module Clocks */ /* Module Clocks */
MOD_CLK_BASE MOD_CLK_BASE
...@@ -64,6 +65,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { ...@@ -64,6 +65,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_RATE(".oco", CLK_OCO, 32768),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
...@@ -96,6 +98,9 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { ...@@ -96,6 +98,9 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
}; };
static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
...@@ -117,6 +122,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { ...@@ -117,6 +122,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
DEF_MOD("sdif", 314, R8A77980_CLK_SD0), DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2), DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
DEF_MOD("rwdt", 402, R8A77980_CLK_R),
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1), DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
...@@ -171,23 +177,23 @@ static const unsigned int r8a77980_crit_mod_clks[] __initconst = { ...@@ -171,23 +177,23 @@ static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
*/ */
/* /*
* MD EXTAL PLL2 PLL1 PLL3 * MD EXTAL PLL2 PLL1 PLL3 OSC
* 14 13 (MHz) * 14 13 (MHz)
* -------------------------------------------------- * --------------------------------------------------------
* 0 0 16.66 x 1 x240 x192 x192 * 0 0 16.66 x 1 x240 x192 x192 /16
* 0 1 20 x 1 x200 x160 x160 * 0 1 20 x 1 x200 x160 x160 /19
* 1 0 27 x 1 x148 x118 x118 * 1 0 27 x 1 x148 x118 x118 /26
* 1 1 33.33 / 2 x240 x192 x192 * 1 1 33.33 / 2 x240 x192 x192 /32
*/ */
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13)) (((md) & BIT(13)) >> 13))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 118, 1, 118, 1, }, { 1, 118, 1, 118, 1, 26, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static int __init r8a77980_cpg_mssr_init(struct device *dev) static int __init r8a77980_cpg_mssr_init(struct device *dev)
......
drivers/clk/renesas/r8a77990-cpg-mssr.c
View file @ f676d861
...@@ -44,6 +44,8 @@ enum clk_ids { ...@@ -44,6 +44,8 @@ enum clk_ids {
CLK_S2, CLK_S2,
CLK_S3, CLK_S3,
CLK_SDSRC, CLK_SDSRC,
CLK_RINT,
CLK_OCO,
/* Module Clocks */ /* Module Clocks */
MOD_CLK_BASE MOD_CLK_BASE
...@@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { ...@@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
...@@ -100,8 +106,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { ...@@ -100,8 +106,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1), DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
...@@ -111,6 +117,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { ...@@ -111,6 +117,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
}; };
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
...@@ -202,6 +210,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { ...@@ -202,6 +210,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2), DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4), DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
......
drivers/clk/renesas/r8a77995-cpg-mssr.c
View file @ f676d861
...@@ -46,6 +46,8 @@ enum clk_ids { ...@@ -46,6 +46,8 @@ enum clk_ids {
CLK_S3, CLK_S3,
CLK_SDSRC, CLK_SDSRC,
CLK_SSPSRC, CLK_SSPSRC,
CLK_RINT,
CLK_OCO,
/* Module Clocks */ /* Module Clocks */
MOD_CLK_BASE MOD_CLK_BASE
...@@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { ...@@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
...@@ -90,8 +96,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { ...@@ -90,8 +96,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
...@@ -102,6 +108,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { ...@@ -102,6 +108,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
}; };
static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
......
drivers/clk/renesas/rcar-gen3-cpg.c
View file @ f676d861
/* /*
* R-Car Gen3 Clock Pulse Generator * R-Car Gen3 Clock Pulse Generator
* *
* Copyright (C) 2015-2016 Glider bvba * Copyright (C) 2015-2018 Glider bvba
* *
* Based on clk-rcar-gen3.c * Based on clk-rcar-gen3.c
* *
...@@ -31,6 +31,8 @@ ...@@ -31,6 +31,8 @@
#define CPG_PLL2CR 0x002c #define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4 #define CPG_PLL4CR 0x01f4
#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
struct cpg_simple_notifier { struct cpg_simple_notifier {
struct notifier_block nb; struct notifier_block nb;
void __iomem *reg; void __iomem *reg;
...@@ -444,7 +446,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, ...@@ -444,7 +446,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
unsigned int div = 1; unsigned int div = 1;
u32 value; u32 value;
parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */ parent = clks[core->parent & 0xffff]; /* some types use high bits */
if (IS_ERR(parent)) if (IS_ERR(parent))
return ERR_CAST(parent); return ERR_CAST(parent);
...@@ -524,7 +526,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, ...@@ -524,7 +526,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
if (clk_get_rate(clks[cpg_clk_extalr])) { if (clk_get_rate(clks[cpg_clk_extalr])) {
parent = clks[cpg_clk_extalr]; parent = clks[cpg_clk_extalr];
value |= BIT(15); value |= CPG_RCKCR_CKSEL;
} }
writel(value, csn->reg); writel(value, csn->reg);
...@@ -537,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, ...@@ -537,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
parent = clks[cpg_clk_extalr]; parent = clks[cpg_clk_extalr];
break; break;
case CLK_TYPE_GEN3_PE: case CLK_TYPE_GEN3_MDSEL:
/* /*
* Peripheral clock with a fixed divider, selectable between * Clock selectable between two parents and two fixed dividers
* clean and spread spectrum parents using MD12 * using a mode pin
*/ */
if (cpg_mode & BIT(12)) { if (cpg_mode & BIT(core->offset)) {
/* Clean */
div = core->div & 0xffff; div = core->div & 0xffff;
} else { } else {
/* SCCG */
parent = clks[core->parent >> 16]; parent = clks[core->parent >> 16];
if (IS_ERR(parent)) if (IS_ERR(parent))
return ERR_CAST(parent); return ERR_CAST(parent);
...@@ -563,6 +563,28 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, ...@@ -563,6 +563,28 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
return cpg_z_clk_register(core->name, __clk_get_name(parent), return cpg_z_clk_register(core->name, __clk_get_name(parent),
base, CPG_FRQCRC_Z2FC_MASK); base, CPG_FRQCRC_Z2FC_MASK);
case CLK_TYPE_GEN3_OSC:
/*
* Clock combining OSC EXTAL predivider and a fixed divider
*/
div = cpg_pll_config->osc_prediv * core->div;
break;
case CLK_TYPE_GEN3_RCKSEL:
/*
* Clock selectable between two parents and two fixed dividers
* using RCKCR.CKSEL
*/
if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
div = core->div & 0xffff;
} else {
parent = clks[core->parent >> 16];
if (IS_ERR(parent))
return ERR_CAST(parent);
div = core->div >> 16;
}
break;
default: default:
return ERR_PTR(-EINVAL); return ERR_PTR(-EINVAL);
} }
......
drivers/clk/renesas/rcar-gen3-cpg.h
View file @ f676d861
/* /*
* R-Car Gen3 Clock Pulse Generator * R-Car Gen3 Clock Pulse Generator
* *
* Copyright (C) 2015-2016 Glider bvba * Copyright (C) 2015-2018 Glider bvba
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
...@@ -20,19 +20,32 @@ enum rcar_gen3_clk_types { ...@@ -20,19 +20,32 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL4, CLK_TYPE_GEN3_PLL4,
CLK_TYPE_GEN3_SD, CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_PE, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
}; };
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
(_parent0) << 16 | (_parent1), \
.div = (_div0) << 16 | (_div1), .offset = _md)
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
_div_clean) \ _div_clean) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
(_parent_sscg) << 16 | (_parent_clean), \ _parent_clean, _div_clean)
.div = (_div_sscg) << 16 | (_div_clean))
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
struct rcar_gen3_cpg_pll_config { struct rcar_gen3_cpg_pll_config {
u8 extal_div; u8 extal_div;
...@@ -40,6 +53,7 @@ struct rcar_gen3_cpg_pll_config { ...@@ -40,6 +53,7 @@ struct rcar_gen3_cpg_pll_config {
u8 pll1_div; u8 pll1_div;
u8 pll3_mult; u8 pll3_mult;
u8 pll3_div; u8 pll3_div;
u8 osc_prediv;
}; };
#define CPG_RCKCR 0x240 #define CPG_RCKCR 0x240
......
drivers/clk/renesas/renesas-cpg-mssr.c
View file @ f676d861
...@@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, ...@@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
} }
break; break;
case CLK_TYPE_FR:
clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
core->mult);
break;
default: default:
if (info->cpg_clk_register) if (info->cpg_clk_register)
clk = info->cpg_clk_register(dev, core, info, clk = info->cpg_clk_register(dev, core, info,
...@@ -659,6 +664,12 @@ static const struct of_device_id cpg_mssr_match[] = { ...@@ -659,6 +664,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a77470_cpg_mssr_info, .data = &r8a77470_cpg_mssr_info,
}, },
#endif #endif
#ifdef CONFIG_CLK_R8A774A1
{
.compatible = "renesas,r8a774a1-cpg-mssr",
.data = &r8a774a1_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A7790 #ifdef CONFIG_CLK_R8A7790
{ {
.compatible = "renesas,r8a7790-cpg-mssr", .compatible = "renesas,r8a7790-cpg-mssr",
......
drivers/clk/renesas/renesas-cpg-mssr.h
View file @ f676d861
...@@ -38,6 +38,7 @@ enum clk_types { ...@@ -38,6 +38,7 @@ enum clk_types {
CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
CLK_TYPE_FR, /* Fixed Rate Clock */
/* Custom definitions start here */ /* Custom definitions start here */
CLK_TYPE_CUSTOM, CLK_TYPE_CUSTOM,
...@@ -56,6 +57,8 @@ enum clk_types { ...@@ -56,6 +57,8 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
#define DEF_RATE(_name, _id, _rate) \
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
/* /*
* Definitions of Module Clocks * Definitions of Module Clocks
...@@ -134,6 +137,7 @@ struct cpg_mssr_info { ...@@ -134,6 +137,7 @@ struct cpg_mssr_info {
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info; extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info; extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info; extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
......
include/dt-bindings/clock/r8a774a1-cpg-mssr.h 0 → 100644
View file @ f676d861
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774a1 CPG Core Clocks */
#define R8A774A1_CLK_Z 0
#define R8A774A1_CLK_Z2 1
#define R8A774A1_CLK_ZG 2
#define R8A774A1_CLK_ZTR 3
#define R8A774A1_CLK_ZTRD2 4
#define R8A774A1_CLK_ZT 5
#define R8A774A1_CLK_ZX 6
#define R8A774A1_CLK_S0D1 7
#define R8A774A1_CLK_S0D2 8
#define R8A774A1_CLK_S0D3 9
#define R8A774A1_CLK_S0D4 10
#define R8A774A1_CLK_S0D6 11
#define R8A774A1_CLK_S0D8 12
#define R8A774A1_CLK_S0D12 13
#define R8A774A1_CLK_S1D2 14
#define R8A774A1_CLK_S1D4 15
#define R8A774A1_CLK_S2D1 16
#define R8A774A1_CLK_S2D2 17
#define R8A774A1_CLK_S2D4 18
#define R8A774A1_CLK_S3D1 19
#define R8A774A1_CLK_S3D2 20
#define R8A774A1_CLK_S3D4 21
#define R8A774A1_CLK_LB 22
#define R8A774A1_CLK_CL 23
#define R8A774A1_CLK_ZB3 24
#define R8A774A1_CLK_ZB3D2 25
#define R8A774A1_CLK_ZB3D4 26
#define R8A774A1_CLK_CR 27
#define R8A774A1_CLK_CRD2 28
#define R8A774A1_CLK_SD0H 29
#define R8A774A1_CLK_SD0 30
#define R8A774A1_CLK_SD1H 31
#define R8A774A1_CLK_SD1 32
#define R8A774A1_CLK_SD2H 33
#define R8A774A1_CLK_SD2 34
#define R8A774A1_CLK_SD3H 35
#define R8A774A1_CLK_SD3 36
#define R8A774A1_CLK_RPC 37
#define R8A774A1_CLK_RPCD2 38
#define R8A774A1_CLK_MSO 39
#define R8A774A1_CLK_HDMI 40
#define R8A774A1_CLK_CSI0 41
#define R8A774A1_CLK_CP 42
#define R8A774A1_CLK_CPEX 43
#define R8A774A1_CLK_R 44
#define R8A774A1_CLK_OSC 45
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
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