Commit f6918382 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'powerpc-4.9-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:
 "Fixes marked for stable:
   - fix system reset interrupt winkle wakeups
   - fix setting of AIL in hypervisor mode

  Fixes for code merged this cycle:
   - fix exception vector build with 2.23 era binutils
   - fix missing update of HID register on secondary CPUs

  Other:
   - fix missing pr_cont()s
   - invalidate ERAT on tlbiel for POWER9 DD1"

* tag 'powerpc-4.9-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/mm: Fix missing update of HID register on secondary CPUs
  powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1
  powerpc/64: Fix setting of AIL in hypervisor mode
  powerpc/oops: Fix missing pr_cont()s in instruction dump
  powerpc/oops: Fix missing pr_cont()s in show_regs()
  powerpc/oops: Fix missing pr_cont()s in print_msr_bits() et. al.
  powerpc/oops: Fix missing pr_cont()s in show_stack()
  powerpc: Fix exception vector build with 2.23 era binutils
  powerpc/64s: Fix system reset interrupt winkle wakeups
parents 384b0dc4 cac4a185
...@@ -91,7 +91,7 @@ ...@@ -91,7 +91,7 @@
*/ */
#define LOAD_HANDLER(reg, label) \ #define LOAD_HANDLER(reg, label) \
ld reg,PACAKBASE(r13); /* get high part of &label */ \ ld reg,PACAKBASE(r13); /* get high part of &label */ \
ori reg,reg,(FIXED_SYMBOL_ABS_ADDR(label))@l; ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label);
#define __LOAD_HANDLER(reg, label) \ #define __LOAD_HANDLER(reg, label) \
ld reg,PACAKBASE(r13); \ ld reg,PACAKBASE(r13); \
...@@ -158,14 +158,17 @@ BEGIN_FTR_SECTION_NESTED(943) \ ...@@ -158,14 +158,17 @@ BEGIN_FTR_SECTION_NESTED(943) \
std ra,offset(r13); \ std ra,offset(r13); \
END_FTR_SECTION_NESTED(ftr,ftr,943) END_FTR_SECTION_NESTED(ftr,ftr,943)
#define EXCEPTION_PROLOG_0(area) \ #define EXCEPTION_PROLOG_0_PACA(area) \
GET_PACA(r13); \
std r9,area+EX_R9(r13); /* save r9 */ \ std r9,area+EX_R9(r13); /* save r9 */ \
OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
HMT_MEDIUM; \ HMT_MEDIUM; \
std r10,area+EX_R10(r13); /* save r10 - r12 */ \ std r10,area+EX_R10(r13); /* save r10 - r12 */ \
OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
#define EXCEPTION_PROLOG_0(area) \
GET_PACA(r13); \
EXCEPTION_PROLOG_0_PACA(area)
#define __EXCEPTION_PROLOG_1(area, extra, vec) \ #define __EXCEPTION_PROLOG_1(area, extra, vec) \
OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
...@@ -196,6 +199,12 @@ END_FTR_SECTION_NESTED(ftr,ftr,943) ...@@ -196,6 +199,12 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
EXCEPTION_PROLOG_1(area, extra, vec); \ EXCEPTION_PROLOG_1(area, extra, vec); \
EXCEPTION_PROLOG_PSERIES_1(label, h); EXCEPTION_PROLOG_PSERIES_1(label, h);
/* Have the PACA in r13 already */
#define EXCEPTION_PROLOG_PSERIES_PACA(area, label, h, extra, vec) \
EXCEPTION_PROLOG_0_PACA(area); \
EXCEPTION_PROLOG_1(area, extra, vec); \
EXCEPTION_PROLOG_PSERIES_1(label, h);
#define __KVMTEST(h, n) \ #define __KVMTEST(h, n) \
lbz r10,HSTATE_IN_GUEST(r13); \ lbz r10,HSTATE_IN_GUEST(r13); \
cmpwi r10,0; \ cmpwi r10,0; \
......
...@@ -460,5 +460,6 @@ ...@@ -460,5 +460,6 @@
#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \ #define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \
((IH & 0x7) << 21)) ((IH & 0x7) << 21))
#define PPC_INVALIDATE_ERAT PPC_SLBIA(7)
#endif /* _ASM_POWERPC_PPC_OPCODE_H */ #endif /* _ASM_POWERPC_PPC_OPCODE_H */
...@@ -116,7 +116,9 @@ EXC_VIRT_NONE(0x4000, 0x4100) ...@@ -116,7 +116,9 @@ EXC_VIRT_NONE(0x4000, 0x4100)
EXC_REAL_BEGIN(system_reset, 0x100, 0x200) EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
SET_SCRATCH0(r13) SET_SCRATCH0(r13)
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, GET_PACA(r13)
clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */
EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD,
IDLETEST, 0x100) IDLETEST, 0x100)
EXC_REAL_END(system_reset, 0x100, 0x200) EXC_REAL_END(system_reset, 0x100, 0x200)
...@@ -124,6 +126,9 @@ EXC_VIRT_NONE(0x4100, 0x4200) ...@@ -124,6 +126,9 @@ EXC_VIRT_NONE(0x4100, 0x4200)
#ifdef CONFIG_PPC_P7_NAP #ifdef CONFIG_PPC_P7_NAP
EXC_COMMON_BEGIN(system_reset_idle_common) EXC_COMMON_BEGIN(system_reset_idle_common)
BEGIN_FTR_SECTION
GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
bl pnv_restore_hyp_resource bl pnv_restore_hyp_resource
li r0,PNV_THREAD_RUNNING li r0,PNV_THREAD_RUNNING
...@@ -169,7 +174,7 @@ EXC_REAL_BEGIN(machine_check, 0x200, 0x300) ...@@ -169,7 +174,7 @@ EXC_REAL_BEGIN(machine_check, 0x200, 0x300)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
/* /*
* Running native on arch 2.06 or later, we may wakeup from winkle * Running native on arch 2.06 or later, we may wakeup from winkle
* inside machine check. If yes, then last bit of HSPGR0 would be set * inside machine check. If yes, then last bit of HSPRG0 would be set
* to 1. Hence clear it unconditionally. * to 1. Hence clear it unconditionally.
*/ */
GET_PACA(r13) GET_PACA(r13)
...@@ -388,7 +393,7 @@ EXC_COMMON_BEGIN(machine_check_handle_early) ...@@ -388,7 +393,7 @@ EXC_COMMON_BEGIN(machine_check_handle_early)
/* /*
* Go back to winkle. Please note that this thread was woken up in * Go back to winkle. Please note that this thread was woken up in
* machine check from winkle and have not restored the per-subcore * machine check from winkle and have not restored the per-subcore
* state. Hence before going back to winkle, set last bit of HSPGR0 * state. Hence before going back to winkle, set last bit of HSPRG0
* to 1. This will make sure that if this thread gets woken up * to 1. This will make sure that if this thread gets woken up
* again at reset vector 0x100 then it will get chance to restore * again at reset vector 0x100 then it will get chance to restore
* the subcore state. * the subcore state.
......
...@@ -1215,7 +1215,7 @@ static void show_instructions(struct pt_regs *regs) ...@@ -1215,7 +1215,7 @@ static void show_instructions(struct pt_regs *regs)
int instr; int instr;
if (!(i % 8)) if (!(i % 8))
printk("\n"); pr_cont("\n");
#if !defined(CONFIG_BOOKE) #if !defined(CONFIG_BOOKE)
/* If executing with the IMMU off, adjust pc rather /* If executing with the IMMU off, adjust pc rather
...@@ -1227,18 +1227,18 @@ static void show_instructions(struct pt_regs *regs) ...@@ -1227,18 +1227,18 @@ static void show_instructions(struct pt_regs *regs)
if (!__kernel_text_address(pc) || if (!__kernel_text_address(pc) ||
probe_kernel_address((unsigned int __user *)pc, instr)) { probe_kernel_address((unsigned int __user *)pc, instr)) {
printk(KERN_CONT "XXXXXXXX "); pr_cont("XXXXXXXX ");
} else { } else {
if (regs->nip == pc) if (regs->nip == pc)
printk(KERN_CONT "<%08x> ", instr); pr_cont("<%08x> ", instr);
else else
printk(KERN_CONT "%08x ", instr); pr_cont("%08x ", instr);
} }
pc += sizeof(int); pc += sizeof(int);
} }
printk("\n"); pr_cont("\n");
} }
struct regbit { struct regbit {
...@@ -1282,7 +1282,7 @@ static void print_bits(unsigned long val, struct regbit *bits, const char *sep) ...@@ -1282,7 +1282,7 @@ static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
for (; bits->bit; ++bits) for (; bits->bit; ++bits)
if (val & bits->bit) { if (val & bits->bit) {
printk("%s%s", s, bits->name); pr_cont("%s%s", s, bits->name);
s = sep; s = sep;
} }
} }
...@@ -1305,9 +1305,9 @@ static void print_tm_bits(unsigned long val) ...@@ -1305,9 +1305,9 @@ static void print_tm_bits(unsigned long val)
* T: Transactional (bit 34) * T: Transactional (bit 34)
*/ */
if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
printk(",TM["); pr_cont(",TM[");
print_bits(val, msr_tm_bits, ""); print_bits(val, msr_tm_bits, "");
printk("]"); pr_cont("]");
} }
} }
#else #else
...@@ -1316,10 +1316,10 @@ static void print_tm_bits(unsigned long val) {} ...@@ -1316,10 +1316,10 @@ static void print_tm_bits(unsigned long val) {}
static void print_msr_bits(unsigned long val) static void print_msr_bits(unsigned long val)
{ {
printk("<"); pr_cont("<");
print_bits(val, msr_bits, ","); print_bits(val, msr_bits, ",");
print_tm_bits(val); print_tm_bits(val);
printk(">"); pr_cont(">");
} }
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
...@@ -1347,29 +1347,29 @@ void show_regs(struct pt_regs * regs) ...@@ -1347,29 +1347,29 @@ void show_regs(struct pt_regs * regs)
printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
trap = TRAP(regs); trap = TRAP(regs);
if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
printk("CFAR: "REG" ", regs->orig_gpr3); pr_cont("CFAR: "REG" ", regs->orig_gpr3);
if (trap == 0x200 || trap == 0x300 || trap == 0x600) if (trap == 0x200 || trap == 0x300 || trap == 0x600)
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
#else #else
printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
#endif #endif
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
printk("SOFTE: %ld ", regs->softe); pr_cont("SOFTE: %ld ", regs->softe);
#endif #endif
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
if (MSR_TM_ACTIVE(regs->msr)) if (MSR_TM_ACTIVE(regs->msr))
printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
#endif #endif
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
if ((i % REGS_PER_LINE) == 0) if ((i % REGS_PER_LINE) == 0)
printk("\nGPR%02d: ", i); pr_cont("\nGPR%02d: ", i);
printk(REG " ", regs->gpr[i]); pr_cont(REG " ", regs->gpr[i]);
if (i == LAST_VOLATILE && !FULL_REGS(regs)) if (i == LAST_VOLATILE && !FULL_REGS(regs))
break; break;
} }
printk("\n"); pr_cont("\n");
#ifdef CONFIG_KALLSYMS #ifdef CONFIG_KALLSYMS
/* /*
* Lookup NIP late so we have the best change of getting the * Lookup NIP late so we have the best change of getting the
...@@ -1900,14 +1900,14 @@ void show_stack(struct task_struct *tsk, unsigned long *stack) ...@@ -1900,14 +1900,14 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
#ifdef CONFIG_FUNCTION_GRAPH_TRACER #ifdef CONFIG_FUNCTION_GRAPH_TRACER
if ((ip == rth) && curr_frame >= 0) { if ((ip == rth) && curr_frame >= 0) {
printk(" (%pS)", pr_cont(" (%pS)",
(void *)current->ret_stack[curr_frame].ret); (void *)current->ret_stack[curr_frame].ret);
curr_frame--; curr_frame--;
} }
#endif #endif
if (firstframe) if (firstframe)
printk(" (unreliable)"); pr_cont(" (unreliable)");
printk("\n"); pr_cont("\n");
} }
firstframe = 0; firstframe = 0;
......
...@@ -226,17 +226,25 @@ static void __init configure_exceptions(void) ...@@ -226,17 +226,25 @@ static void __init configure_exceptions(void)
if (firmware_has_feature(FW_FEATURE_OPAL)) if (firmware_has_feature(FW_FEATURE_OPAL))
opal_configure_cores(); opal_configure_cores();
/* Enable AIL if supported, and we are in hypervisor mode */ /* AIL on native is done in cpu_ready_for_interrupts() */
}
}
static void cpu_ready_for_interrupts(void)
{
/*
* Enable AIL if supported, and we are in hypervisor mode. This
* is called once for every processor.
*
* If we are not in hypervisor mode the job is done once for
* the whole partition in configure_exceptions().
*/
if (early_cpu_has_feature(CPU_FTR_HVMODE) && if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
early_cpu_has_feature(CPU_FTR_ARCH_207S)) { early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
unsigned long lpcr = mfspr(SPRN_LPCR); unsigned long lpcr = mfspr(SPRN_LPCR);
mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
} }
}
}
static void cpu_ready_for_interrupts(void)
{
/* Set IR and DR in PACA MSR */ /* Set IR and DR in PACA MSR */
get_paca()->kernel_msr = MSR_KERNEL; get_paca()->kernel_msr = MSR_KERNEL;
} }
......
...@@ -1029,6 +1029,10 @@ void hash__early_init_mmu_secondary(void) ...@@ -1029,6 +1029,10 @@ void hash__early_init_mmu_secondary(void)
{ {
/* Initialize hash table for that CPU */ /* Initialize hash table for that CPU */
if (!firmware_has_feature(FW_FEATURE_LPAR)) { if (!firmware_has_feature(FW_FEATURE_LPAR)) {
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
update_hid_for_hash();
if (!cpu_has_feature(CPU_FTR_ARCH_300)) if (!cpu_has_feature(CPU_FTR_ARCH_300))
mtspr(SPRN_SDR1, _SDR1); mtspr(SPRN_SDR1, _SDR1);
else else
......
...@@ -388,6 +388,10 @@ void radix__early_init_mmu_secondary(void) ...@@ -388,6 +388,10 @@ void radix__early_init_mmu_secondary(void)
* update partition table control register and UPRT * update partition table control register and UPRT
*/ */
if (!firmware_has_feature(FW_FEATURE_LPAR)) { if (!firmware_has_feature(FW_FEATURE_LPAR)) {
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
update_hid_for_radix();
lpcr = mfspr(SPRN_LPCR); lpcr = mfspr(SPRN_LPCR);
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
......
...@@ -50,6 +50,8 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) ...@@ -50,6 +50,8 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) { for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
__tlbiel_pid(pid, set, ric); __tlbiel_pid(pid, set, ric);
} }
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
return; return;
} }
...@@ -83,6 +85,8 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid, ...@@ -83,6 +85,8 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
} }
static inline void _tlbie_va(unsigned long va, unsigned long pid, static inline void _tlbie_va(unsigned long va, unsigned long pid,
......
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