ARM: dts: aspeed: Add uart routing to device tree

Add LPC uart routing to the device tree for Aspeed SoCs.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
Link: https://lore.kernel.org/r/20210927023053.6728-6-chiawei_wang@aspeedtech.comSigned-off-by: Joel Stanley <joel@jms.id.au>

arch/arm/boot/dts/aspeed-g4.dtsi

@@ -383,6 +383,12 @@ ibt: ibt@140 {
 					interrupts = <8>;
 					status = "disabled";
 				};
+
+				uart_routing: uart-routing@9c {
+					compatible = "aspeed,ast2400-uart-routing";
+					reg = <0x9c 0x4>;
+					status = "disabled";
+				};
 			};
 
 			uart2: serial@1e78d000 {

arch/arm/boot/dts/aspeed-g5.dtsi

@@ -491,6 +491,12 @@ lpc_reset: reset-controller@98 {
 					#reset-cells = <1>;
 				};
 
+				uart_routing: uart-routing@9c {
+					compatible = "aspeed,ast2500-uart-routing";
+					reg = <0x9c 0x4>;
+					status = "disabled";
+				};
+
 				lhc: lhc@a0 {
 					compatible = "aspeed,ast2500-lhc";
 					reg = <0xa0 0x24 0xc8 0x8>;

arch/arm/boot/dts/aspeed-g6.dtsi

@@ -571,6 +571,12 @@ lpc_reset: reset-controller@98 {
 					#reset-cells = <1>;
 				};
 
+				uart_routing: uart-routing@98 {
+					compatible = "aspeed,ast2600-uart-routing";
+					reg = <0x98 0x8>;
+					status = "disabled";
+				};
+
 				ibt: ibt@140 {
 					compatible = "aspeed,ast2600-ibt-bmc";
 					reg = <0x140 0x18>;