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Kirill Smelkov
linux
Commits
f9bfccf1
Commit
f9bfccf1
authored
Jun 25, 2009
by
Russell King
Committed by
Russell King
Jun 25, 2009
Browse files
Options
Browse Files
Download
Plain Diff
Merge branch 'omap-fixes' of
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
parents
28d0325c
503dcbeb
Changes
14
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Showing
14 changed files
with
108 additions
and
22 deletions
+108
-22
arch/arm/mach-omap1/board-nokia770.c
arch/arm/mach-omap1/board-nokia770.c
+2
-1
arch/arm/mach-omap1/mailbox.c
arch/arm/mach-omap1/mailbox.c
+1
-1
arch/arm/mach-omap2/board-rx51-peripherals.c
arch/arm/mach-omap2/board-rx51-peripherals.c
+1
-0
arch/arm/mach-omap2/gpmc-onenand.c
arch/arm/mach-omap2/gpmc-onenand.c
+19
-2
arch/arm/mach-omap2/id.c
arch/arm/mach-omap2/id.c
+22
-0
arch/arm/mach-omap2/mailbox.c
arch/arm/mach-omap2/mailbox.c
+3
-3
arch/arm/mach-omap2/mmc-twl4030.c
arch/arm/mach-omap2/mmc-twl4030.c
+12
-1
arch/arm/plat-omap/dma.c
arch/arm/plat-omap/dma.c
+13
-0
arch/arm/plat-omap/gpio.c
arch/arm/plat-omap/gpio.c
+1
-0
arch/arm/plat-omap/include/mach/cpu.h
arch/arm/plat-omap/include/mach/cpu.h
+11
-11
arch/arm/plat-omap/include/mach/dma.h
arch/arm/plat-omap/include/mach/dma.h
+15
-0
arch/arm/plat-omap/include/mach/io.h
arch/arm/plat-omap/include/mach/io.h
+1
-1
arch/arm/plat-omap/iommu.c
arch/arm/plat-omap/iommu.c
+1
-1
arch/arm/plat-omap/sram.c
arch/arm/plat-omap/sram.c
+6
-1
No files found.
arch/arm/mach-omap1/board-nokia770.c
View file @
f9bfccf1
...
@@ -36,7 +36,6 @@
...
@@ -36,7 +36,6 @@
#include <mach/hwa742.h>
#include <mach/hwa742.h>
#include <mach/lcd_mipid.h>
#include <mach/lcd_mipid.h>
#include <mach/mmc.h>
#include <mach/mmc.h>
#include <mach/usb.h>
#include <mach/clock.h>
#include <mach/clock.h>
#define ADS7846_PENDOWN_GPIO 15
#define ADS7846_PENDOWN_GPIO 15
...
@@ -205,9 +204,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot)
...
@@ -205,9 +204,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot)
static
struct
omap_mmc_platform_data
nokia770_mmc2_data
=
{
static
struct
omap_mmc_platform_data
nokia770_mmc2_data
=
{
.
nr_slots
=
1
,
.
nr_slots
=
1
,
.
dma_mask
=
0xffffffff
,
.
dma_mask
=
0xffffffff
,
.
max_freq
=
12000000
,
.
slots
[
0
]
=
{
.
slots
[
0
]
=
{
.
set_power
=
nokia770_mmc_set_power
,
.
set_power
=
nokia770_mmc_set_power
,
.
get_cover_state
=
nokia770_mmc_get_cover_state
,
.
get_cover_state
=
nokia770_mmc_get_cover_state
,
.
ocr_mask
=
MMC_VDD_32_33
|
MMC_VDD_33_34
,
.
name
=
"mmcblk"
,
.
name
=
"mmcblk"
,
},
},
};
};
...
...
arch/arm/mach-omap1/mailbox.c
View file @
f9bfccf1
...
@@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit);
...
@@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit);
MODULE_LICENSE
(
"GPL v2"
);
MODULE_LICENSE
(
"GPL v2"
);
MODULE_DESCRIPTION
(
"omap mailbox: omap1 architecture specific functions"
);
MODULE_DESCRIPTION
(
"omap mailbox: omap1 architecture specific functions"
);
MODULE_AUTHOR
(
"Hiroshi DOYU
"
<
Hiroshi
.
DOYU
@
nokia
.
com
>
);
MODULE_AUTHOR
(
"Hiroshi DOYU
<Hiroshi.DOYU@nokia.com>"
);
MODULE_ALIAS
(
"platform:omap1-mailbox"
);
MODULE_ALIAS
(
"platform:omap1-mailbox"
);
arch/arm/mach-omap2/board-rx51-peripherals.c
View file @
f9bfccf1
...
@@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
...
@@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
.
gpio_irq
=
65
,
.
gpio_irq
=
65
,
.
parts
=
onenand_partitions
,
.
parts
=
onenand_partitions
,
.
nr_parts
=
ARRAY_SIZE
(
onenand_partitions
),
.
nr_parts
=
ARRAY_SIZE
(
onenand_partitions
),
.
flags
=
ONENAND_SYNC_READWRITE
,
};
};
static
void
__init
board_onenand_init
(
void
)
static
void
__init
board_onenand_init
(
void
)
...
...
arch/arm/mach-omap2/gpmc-onenand.c
View file @
f9bfccf1
...
@@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
...
@@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
static
int
omap2_onenand_set_async_mode
(
int
cs
,
void
__iomem
*
onenand_base
)
static
int
omap2_onenand_set_async_mode
(
int
cs
,
void
__iomem
*
onenand_base
)
{
{
struct
gpmc_timings
t
;
struct
gpmc_timings
t
;
u32
reg
;
int
err
;
const
int
t_cer
=
15
;
const
int
t_cer
=
15
;
const
int
t_avdp
=
12
;
const
int
t_avdp
=
12
;
...
@@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
...
@@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
const
int
t_wpl
=
40
;
const
int
t_wpl
=
40
;
const
int
t_wph
=
30
;
const
int
t_wph
=
30
;
/* Ensure sync read and sync write are disabled */
reg
=
readw
(
onenand_base
+
ONENAND_REG_SYS_CFG1
);
reg
&=
~
ONENAND_SYS_CFG1_SYNC_READ
&
~
ONENAND_SYS_CFG1_SYNC_WRITE
;
writew
(
reg
,
onenand_base
+
ONENAND_REG_SYS_CFG1
);
memset
(
&
t
,
0
,
sizeof
(
t
));
memset
(
&
t
,
0
,
sizeof
(
t
));
t
.
sync_clk
=
0
;
t
.
sync_clk
=
0
;
t
.
cs_on
=
0
;
t
.
cs_on
=
0
;
...
@@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
...
@@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
GPMC_CONFIG1_DEVICESIZE_16
|
GPMC_CONFIG1_DEVICESIZE_16
|
GPMC_CONFIG1_MUXADDDATA
);
GPMC_CONFIG1_MUXADDDATA
);
return
gpmc_cs_set_timings
(
cs
,
&
t
);
err
=
gpmc_cs_set_timings
(
cs
,
&
t
);
if
(
err
)
return
err
;
/* Ensure sync read and sync write are disabled */
reg
=
readw
(
onenand_base
+
ONENAND_REG_SYS_CFG1
);
reg
&=
~
ONENAND_SYS_CFG1_SYNC_READ
&
~
ONENAND_SYS_CFG1_SYNC_WRITE
;
writew
(
reg
,
onenand_base
+
ONENAND_REG_SYS_CFG1
);
return
0
;
}
}
static
void
set_onenand_cfg
(
void
__iomem
*
onenand_base
,
int
latency
,
static
void
set_onenand_cfg
(
void
__iomem
*
onenand_base
,
int
latency
,
...
@@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
...
@@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
}
else
if
(
cfg
->
flags
&
ONENAND_SYNC_READWRITE
)
{
}
else
if
(
cfg
->
flags
&
ONENAND_SYNC_READWRITE
)
{
sync_read
=
1
;
sync_read
=
1
;
sync_write
=
1
;
sync_write
=
1
;
}
}
else
return
omap2_onenand_set_async_mode
(
cs
,
onenand_base
);
if
(
!
freq
)
{
if
(
!
freq
)
{
/* Very first call freq is not known */
/* Very first call freq is not known */
...
...
arch/arm/mach-omap2/id.c
View file @
f9bfccf1
...
@@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci)
...
@@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci)
}
}
EXPORT_SYMBOL
(
omap_chip_is
);
EXPORT_SYMBOL
(
omap_chip_is
);
int
omap_type
(
void
)
{
u32
val
=
0
;
if
(
cpu_is_omap24xx
())
val
=
omap_ctrl_readl
(
OMAP24XX_CONTROL_STATUS
);
else
if
(
cpu_is_omap34xx
())
val
=
omap_ctrl_readl
(
OMAP343X_CONTROL_STATUS
);
else
{
pr_err
(
"Cannot detect omap type!
\n
"
);
goto
out
;
}
val
&=
OMAP2_DEVICETYPE_MASK
;
val
>>=
8
;
out:
return
val
;
}
EXPORT_SYMBOL
(
omap_type
);
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
#define OMAP_TAP_IDCODE 0x0204
#define OMAP_TAP_IDCODE 0x0204
...
...
arch/arm/mach-omap2/mailbox.c
View file @
f9bfccf1
...
@@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
...
@@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
return
-
ENOMEM
;
return
-
ENOMEM
;
/* DSP or IVA2 IRQ */
/* DSP or IVA2 IRQ */
mbox_dsp_info
.
irq
=
platform_get_irq
(
pdev
,
0
);
ret
=
platform_get_irq
(
pdev
,
0
);
if
(
mbox_dsp_info
.
irq
<
0
)
{
if
(
ret
<
0
)
{
dev_err
(
&
pdev
->
dev
,
"invalid irq resource
\n
"
);
dev_err
(
&
pdev
->
dev
,
"invalid irq resource
\n
"
);
ret
=
-
ENODEV
;
goto
err_dsp
;
goto
err_dsp
;
}
}
mbox_dsp_info
.
irq
=
ret
;
ret
=
omap_mbox_register
(
&
pdev
->
dev
,
&
mbox_dsp_info
);
ret
=
omap_mbox_register
(
&
pdev
->
dev
,
&
mbox_dsp_info
);
if
(
ret
)
if
(
ret
)
...
...
arch/arm/mach-omap2/mmc-twl4030.c
View file @
f9bfccf1
...
@@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
...
@@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
static
int
twl_mmc23_set_power
(
struct
device
*
dev
,
int
slot
,
int
power_on
,
int
vdd
)
static
int
twl_mmc23_set_power
(
struct
device
*
dev
,
int
slot
,
int
power_on
,
int
vdd
)
{
{
int
ret
=
0
;
int
ret
=
0
;
struct
twl_mmc_controller
*
c
=
&
hsmmc
[
1
]
;
struct
twl_mmc_controller
*
c
=
NULL
;
struct
omap_mmc_platform_data
*
mmc
=
dev
->
platform_data
;
struct
omap_mmc_platform_data
*
mmc
=
dev
->
platform_data
;
int
i
;
for
(
i
=
1
;
i
<
ARRAY_SIZE
(
hsmmc
);
i
++
)
{
if
(
mmc
==
hsmmc
[
i
].
mmc
)
{
c
=
&
hsmmc
[
i
];
break
;
}
}
if
(
c
==
NULL
)
return
-
ENODEV
;
/* If we don't see a Vcc regulator, assume it's a fixed
/* If we don't see a Vcc regulator, assume it's a fixed
* voltage always-on regulator.
* voltage always-on regulator.
...
...
arch/arm/plat-omap/dma.c
View file @
f9bfccf1
...
@@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void)
...
@@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void)
setup_irq
(
irq
,
&
omap24xx_dma_irq
);
setup_irq
(
irq
,
&
omap24xx_dma_irq
);
}
}
/* Enable smartidle idlemodes and autoidle */
if
(
cpu_is_omap34xx
())
{
u32
v
=
dma_read
(
OCP_SYSCONFIG
);
v
&=
~
(
DMA_SYSCONFIG_MIDLEMODE_MASK
|
DMA_SYSCONFIG_SIDLEMODE_MASK
|
DMA_SYSCONFIG_AUTOIDLE
);
v
|=
(
DMA_SYSCONFIG_MIDLEMODE
(
DMA_IDLEMODE_SMARTIDLE
)
|
DMA_SYSCONFIG_SIDLEMODE
(
DMA_IDLEMODE_SMARTIDLE
)
|
DMA_SYSCONFIG_AUTOIDLE
);
dma_write
(
v
,
OCP_SYSCONFIG
);
}
/* FIXME: Update LCD DMA to work on 24xx */
/* FIXME: Update LCD DMA to work on 24xx */
if
(
cpu_class_is_omap1
())
{
if
(
cpu_class_is_omap1
())
{
r
=
request_irq
(
INT_DMA_LCD
,
lcd_dma_irq_handler
,
0
,
r
=
request_irq
(
INT_DMA_LCD
,
lcd_dma_irq_handler
,
0
,
...
...
arch/arm/plat-omap/gpio.c
View file @
f9bfccf1
...
@@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void)
...
@@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void)
__raw_writel
(
0x00000000
,
bank
->
base
+
OMAP24XX_GPIO_IRQENABLE1
);
__raw_writel
(
0x00000000
,
bank
->
base
+
OMAP24XX_GPIO_IRQENABLE1
);
__raw_writel
(
0xffffffff
,
bank
->
base
+
OMAP24XX_GPIO_IRQSTATUS1
);
__raw_writel
(
0xffffffff
,
bank
->
base
+
OMAP24XX_GPIO_IRQSTATUS1
);
__raw_writew
(
0x0015
,
bank
->
base
+
OMAP24XX_GPIO_SYSCONFIG
);
__raw_writew
(
0x0015
,
bank
->
base
+
OMAP24XX_GPIO_SYSCONFIG
);
__raw_writel
(
0x00000000
,
bank
->
base
+
OMAP24XX_GPIO_DEBOUNCE_EN
);
/* Initialize interface clock ungated, module enabled */
/* Initialize interface clock ungated, module enabled */
__raw_writel
(
0
,
bank
->
base
+
OMAP24XX_GPIO_CTRL
);
__raw_writel
(
0
,
bank
->
base
+
OMAP24XX_GPIO_CTRL
);
...
...
arch/arm/plat-omap/include/mach/cpu.h
View file @
f9bfccf1
...
@@ -30,6 +30,17 @@
...
@@ -30,6 +30,17 @@
#ifndef __ASM_ARCH_OMAP_CPU_H
#ifndef __ASM_ARCH_OMAP_CPU_H
#define __ASM_ARCH_OMAP_CPU_H
#define __ASM_ARCH_OMAP_CPU_H
/*
* Omap device type i.e. EMU/HS/TST/GP/BAD
*/
#define OMAP2_DEVICE_TYPE_TEST 0
#define OMAP2_DEVICE_TYPE_EMU 1
#define OMAP2_DEVICE_TYPE_SEC 2
#define OMAP2_DEVICE_TYPE_GP 3
#define OMAP2_DEVICE_TYPE_BAD 4
int
omap_type
(
void
);
struct
omap_chip_id
{
struct
omap_chip_id
{
u8
oc
;
u8
oc
;
u8
type
;
u8
type
;
...
@@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430)
...
@@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430)
int
omap_chip_is
(
struct
omap_chip_id
oci
);
int
omap_chip_is
(
struct
omap_chip_id
oci
);
int
omap_type
(
void
);
/*
* Macro to detect device type i.e. EMU/HS/TST/GP/BAD
*/
#define OMAP2_DEVICE_TYPE_TEST 0
#define OMAP2_DEVICE_TYPE_EMU 1
#define OMAP2_DEVICE_TYPE_SEC 2
#define OMAP2_DEVICE_TYPE_GP 3
#define OMAP2_DEVICE_TYPE_BAD 4
void
omap2_check_revision
(
void
);
void
omap2_check_revision
(
void
);
#endif
/* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
#endif
/* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
arch/arm/plat-omap/include/mach/dma.h
View file @
f9bfccf1
...
@@ -389,6 +389,21 @@
...
@@ -389,6 +389,21 @@
#define DMA_THREAD_FIFO_25 (0x02 << 14)
#define DMA_THREAD_FIFO_25 (0x02 << 14)
#define DMA_THREAD_FIFO_50 (0x03 << 14)
#define DMA_THREAD_FIFO_50 (0x03 << 14)
/* DMA4_OCP_SYSCONFIG bits */
#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
#define DMA_SYSCONFIG_EMUFREE (1 << 5)
#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
#define DMA_IDLEMODE_SMARTIDLE 0x2
#define DMA_IDLEMODE_NO_IDLE 0x1
#define DMA_IDLEMODE_FORCE_IDLE 0x0
/* Chaining modes*/
/* Chaining modes*/
#ifndef CONFIG_ARCH_OMAP1
#ifndef CONFIG_ARCH_OMAP1
#define OMAP_DMA_STATIC_CHAIN 0x1
#define OMAP_DMA_STATIC_CHAIN 0x1
...
...
arch/arm/plat-omap/include/mach/io.h
View file @
f9bfccf1
...
@@ -201,7 +201,7 @@
...
@@ -201,7 +201,7 @@
#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
#ifdef __ASSEMBLER__
#ifdef __ASSEMBLER__
#define IOMEM(x)
x
#define IOMEM(x)
(x)
#else
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#define IOMEM(x) ((void __force __iomem *)(x))
...
...
arch/arm/plat-omap/iommu.c
View file @
f9bfccf1
...
@@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
...
@@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
if
((
start
<=
da
)
&&
(
da
<
start
+
bytes
))
{
if
((
start
<=
da
)
&&
(
da
<
start
+
bytes
))
{
dev_dbg
(
obj
->
dev
,
"%s: %08x<=%08x(%x)
\n
"
,
dev_dbg
(
obj
->
dev
,
"%s: %08x<=%08x(%x)
\n
"
,
__func__
,
start
,
da
,
bytes
);
__func__
,
start
,
da
,
bytes
);
iotlb_load_cr
(
obj
,
&
cr
);
iommu_write_reg
(
obj
,
1
,
MMU_FLUSH_ENTRY
);
iommu_write_reg
(
obj
,
1
,
MMU_FLUSH_ENTRY
);
}
}
}
}
...
...
arch/arm/plat-omap/sram.c
View file @
f9bfccf1
...
@@ -133,7 +133,12 @@ void __init omap_detect_sram(void)
...
@@ -133,7 +133,12 @@ void __init omap_detect_sram(void)
if
(
cpu_is_omap34xx
())
{
if
(
cpu_is_omap34xx
())
{
omap_sram_base
=
OMAP3_SRAM_PUB_VA
;
omap_sram_base
=
OMAP3_SRAM_PUB_VA
;
omap_sram_start
=
OMAP3_SRAM_PUB_PA
;
omap_sram_start
=
OMAP3_SRAM_PUB_PA
;
if
((
omap_type
()
==
OMAP2_DEVICE_TYPE_EMU
)
||
(
omap_type
()
==
OMAP2_DEVICE_TYPE_SEC
))
{
omap_sram_size
=
0x7000
;
/* 28K */
}
else
{
omap_sram_size
=
0x8000
;
/* 32K */
omap_sram_size
=
0x8000
;
/* 32K */
}
}
else
{
}
else
{
omap_sram_base
=
OMAP2_SRAM_PUB_VA
;
omap_sram_base
=
OMAP2_SRAM_PUB_VA
;
omap_sram_start
=
OMAP2_SRAM_PUB_PA
;
omap_sram_start
=
OMAP2_SRAM_PUB_PA
;
...
...
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