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Commit fab9298c authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/max98927', 'asoc/topic/mc13783',... 

Merge remote-tracking branches 'asoc/topic/max98927', 'asoc/topic/mc13783', 'asoc/topic/msm8916', 'asoc/topic/mt8173' and 'asoc/topic/mtk' into asoc-next
parents 2e015bfb 68fea7cd 33953d85 42e193cd d6e2c4ff 11aa2d96
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Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
View file @ fab9298c
...@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701 ...@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701
Required properties: Required properties:
- compatible = "mediatek,mt2701-audio"; - compatible = "mediatek,mt2701-audio";
- reg: register location and size
- interrupts: should contain AFE and ASYS interrupts - interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys" - interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain - power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names
See ../clocks/clock-bindings.txt for details
- clock-names: should have these clock names: - clock-names: should have these clock names:
"infra_sys_audio_clk", "infra_sys_audio_clk",
"top_audio_mux1_sel", "top_audio_mux1_sel",
"top_audio_mux2_sel", "top_audio_mux2_sel",
"top_audio_mux1_div", "top_audio_a1sys_hp",
"top_audio_mux2_div", "top_audio_a2sys_hp",
"top_audio_48k_timing", "i2s0_src_sel",
"top_audio_44k_timing", "i2s1_src_sel",
"top_audpll_mux_sel", "i2s2_src_sel",
"top_apll_sel", "i2s3_src_sel",
"top_aud1_pll_98M", "i2s0_src_div",
"top_aud2_pll_90M", "i2s1_src_div",
"top_hadds2_pll_98M", "i2s2_src_div",
"top_hadds2_pll_294M", "i2s3_src_div",
"top_audpll", "i2s0_mclk_en",
"top_audpll_d4", "i2s1_mclk_en",
"top_audpll_d8", "i2s2_mclk_en",
"top_audpll_d16", "i2s3_mclk_en",
"top_audpll_d24", "i2so0_hop_ck",
"top_audintbus_sel", "i2so1_hop_ck",
"clk_26m", "i2so2_hop_ck",
"top_syspll1_d4", "i2so3_hop_ck",
"top_aud_k1_src_sel", "i2si0_hop_ck",
"top_aud_k2_src_sel", "i2si1_hop_ck",
"top_aud_k3_src_sel", "i2si2_hop_ck",
"top_aud_k4_src_sel", "i2si3_hop_ck",
"top_aud_k5_src_sel", "asrc0_out_ck",
"top_aud_k6_src_sel", "asrc1_out_ck",
"top_aud_k1_src_div", "asrc2_out_ck",
"top_aud_k2_src_div", "asrc3_out_ck",
"top_aud_k3_src_div", "audio_afe_pd",
"top_aud_k4_src_div", "audio_afe_conn_pd",
"top_aud_k5_src_div", "audio_a1sys_pd",
"top_aud_k6_src_div", "audio_a2sys_pd",
"top_aud_i2s1_mclk", "audio_mrgif_pd";
"top_aud_i2s2_mclk", - assigned-clocks: list of input clocks and dividers for the audio system.
"top_aud_i2s3_mclk", See ../clocks/clock-bindings.txt for details.
"top_aud_i2s4_mclk", - assigned-clocks-parents: parent of input clocks of assigned clocks.
"top_aud_i2s5_mclk", - assigned-clock-rates: list of clock frequencies of assigned clocks.
"top_aud_i2s6_mclk",
"top_asm_m_sel", Must be a subnode of MediaTek audsys device tree node.
"top_asm_h_sel", See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
Example: Example:
afe: mt2701-afe-pcm@11220000 { audsys: audio-subsystem@11220000 {
compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
...
afe: audio-controller {
compatible = "mediatek,mt2701-audio"; compatible = "mediatek,mt2701-audio";
reg = <0 0x11220000 0 0x2000>,
<0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys"; interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>,
<&topckgen CLK_TOP_AUD_48K_TIMING>, <&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>, <&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
<&topckgen CLK_TOP_APLL_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>,
<&topckgen CLK_TOP_HADDS2PLL_98M>,
<&topckgen CLK_TOP_HADDS2PLL_294M>,
<&topckgen CLK_TOP_AUDPLL>,
<&topckgen CLK_TOP_AUDPLL_D4>,
<&topckgen CLK_TOP_AUDPLL_D8>,
<&topckgen CLK_TOP_AUDPLL_D16>,
<&topckgen CLK_TOP_AUDPLL_D24>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_SYSPLL1_D4>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>, <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>, <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>, <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>, <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>, <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_AUD_I2S5_MCLK>, <&audsys CLK_AUD_I2SO1>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>, <&audsys CLK_AUD_I2SO2>,
<&topckgen CLK_TOP_ASM_M_SEL>, <&audsys CLK_AUD_I2SO3>,
<&topckgen CLK_TOP_ASM_H_SEL>, <&audsys CLK_AUD_I2SO4>,
<&topckgen CLK_TOP_UNIVPLL2_D4>, <&audsys CLK_AUD_I2SIN1>,
<&topckgen CLK_TOP_UNIVPLL2_D2>, <&audsys CLK_AUD_I2SIN2>,
<&topckgen CLK_TOP_SYSPLL_D5>; <&audsys CLK_AUD_I2SIN3>,
<&audsys CLK_AUD_I2SIN4>,
<&audsys CLK_AUD_ASRCO1>,
<&audsys CLK_AUD_ASRCO2>,
<&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "infra_sys_audio_clk", clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel", "top_audio_mux1_sel",
"top_audio_mux2_sel", "top_audio_mux2_sel",
"top_audio_mux1_div", "top_audio_a1sys_hp",
"top_audio_mux2_div", "top_audio_a2sys_hp",
"top_audio_48k_timing", "i2s0_src_sel",
"top_audio_44k_timing", "i2s1_src_sel",
"top_audpll_mux_sel", "i2s2_src_sel",
"top_apll_sel", "i2s3_src_sel",
"top_aud1_pll_98M", "i2s0_src_div",
"top_aud2_pll_90M", "i2s1_src_div",
"top_hadds2_pll_98M", "i2s2_src_div",
"top_hadds2_pll_294M", "i2s3_src_div",
"top_audpll", "i2s0_mclk_en",
"top_audpll_d4", "i2s1_mclk_en",
"top_audpll_d8", "i2s2_mclk_en",
"top_audpll_d16", "i2s3_mclk_en",
"top_audpll_d24", "i2so0_hop_ck",
"top_audintbus_sel", "i2so1_hop_ck",
"clk_26m", "i2so2_hop_ck",
"top_syspll1_d4", "i2so3_hop_ck",
"top_aud_k1_src_sel", "i2si0_hop_ck",
"top_aud_k2_src_sel", "i2si1_hop_ck",
"top_aud_k3_src_sel", "i2si2_hop_ck",
"top_aud_k4_src_sel", "i2si3_hop_ck",
"top_aud_k5_src_sel", "asrc0_out_ck",
"top_aud_k6_src_sel", "asrc1_out_ck",
"top_aud_k1_src_div", "asrc2_out_ck",
"top_aud_k2_src_div", "asrc3_out_ck",
"top_aud_k3_src_div", "audio_afe_pd",
"top_aud_k4_src_div", "audio_afe_conn_pd",
"top_aud_k5_src_div", "audio_a1sys_pd",
"top_aud_k6_src_div", "audio_a2sys_pd",
"top_aud_i2s1_mclk", "audio_mrgif_pd";
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk", assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
"top_aud_i2s4_mclk", <&topckgen CLK_TOP_AUD_MUX2_SEL>,
"top_aud_i2s5_mclk", <&topckgen CLK_TOP_AUD_MUX1_DIV>,
"top_aud_i2s6_mclk", <&topckgen CLK_TOP_AUD_MUX2_DIV>;
"top_asm_m_sel", assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
"top_asm_h_sel", <&topckgen CLK_TOP_AUD2PLL_90M>;
"top_univpll2_d4", assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
"top_univpll2_d2", };
"top_syspll_d5";
}; };
sound/soc/codecs/max98927.c
View file @ fab9298c
...@@ -682,7 +682,6 @@ static int max98927_probe(struct snd_soc_codec *codec) ...@@ -682,7 +682,6 @@ static int max98927_probe(struct snd_soc_codec *codec)
struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
max98927->codec = codec; max98927->codec = codec;
codec->control_data = max98927->regmap;
/* Software Reset */ /* Software Reset */
regmap_write(max98927->regmap, regmap_write(max98927->regmap,
......
sound/soc/codecs/mc13783.c
View file @ fab9298c
...@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec) ...@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec)
{ {
struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec); struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
snd_soc_codec_init_regmap(codec,
dev_get_regmap(codec->dev->parent, NULL));
/* these are the reset values */ /* these are the reset values */
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893); mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A); mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
...@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = { ...@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
} }
}; };
static struct regmap *mc13783_get_regmap(struct device *dev)
{
return dev_get_regmap(dev->parent, NULL);
}
static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = { static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
.probe = mc13783_probe, .probe = mc13783_probe,
.remove = mc13783_remove, .remove = mc13783_remove,
.get_regmap = mc13783_get_regmap,
.component_driver = { .component_driver = {
.controls = mc13783_control_list, .controls = mc13783_control_list,
.num_controls = ARRAY_SIZE(mc13783_control_list), .num_controls = ARRAY_SIZE(mc13783_control_list),
......
sound/soc/codecs/msm8916-wcd-analog.c
View file @ fab9298c
...@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec) ...@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
return err; return err;
} }
snd_soc_codec_init_regmap(codec,
dev_get_regmap(codec->dev->parent, NULL));
snd_soc_codec_set_drvdata(codec, priv); snd_soc_codec_set_drvdata(codec, priv);
priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1); priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE); priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
...@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec, ...@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec,
return 0; return 0;
} }
static struct regmap *pm8916_get_regmap(struct device *dev)
{
return dev_get_regmap(dev->parent, NULL);
}
static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
{ {
struct pm8916_wcd_analog_priv *priv = arg; struct pm8916_wcd_analog_priv *priv = arg;
...@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = { ...@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = {
.probe = pm8916_wcd_analog_probe, .probe = pm8916_wcd_analog_probe,
.remove = pm8916_wcd_analog_remove, .remove = pm8916_wcd_analog_remove,
.set_jack = pm8916_wcd_analog_set_jack, .set_jack = pm8916_wcd_analog_set_jack,
.get_regmap = pm8916_get_regmap,
.component_driver = { .component_driver = {
.controls = pm8916_wcd_analog_snd_controls, .controls = pm8916_wcd_analog_snd_controls,
.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
......
sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
View file @ fab9298c
...@@ -21,16 +21,15 @@ struct mtk_base_afe; ...@@ -21,16 +21,15 @@ struct mtk_base_afe;
int mt2701_init_clock(struct mtk_base_afe *afe); int mt2701_init_clock(struct mtk_base_afe *afe);
int mt2701_afe_enable_clock(struct mtk_base_afe *afe); int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
void mt2701_afe_disable_clock(struct mtk_base_afe *afe); int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe); int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe); void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe); int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe); void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
int mclk); int mclk);
......
sound/soc/mediatek/mt2701/mt2701-afe-common.h
View file @ fab9298c
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#ifndef _MT_2701_AFE_COMMON_H_ #ifndef _MT_2701_AFE_COMMON_H_
#define _MT_2701_AFE_COMMON_H_ #define _MT_2701_AFE_COMMON_H_
#include <sound/soc.h> #include <sound/soc.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/regmap.h> #include <linux/regmap.h>
...@@ -25,16 +26,7 @@ ...@@ -25,16 +26,7 @@
#define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
#define MT2701_PLL_DOMAIN_0_RATE 98304000 #define MT2701_PLL_DOMAIN_0_RATE 98304000
#define MT2701_PLL_DOMAIN_1_RATE 90316800 #define MT2701_PLL_DOMAIN_1_RATE 90316800
#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2) #define MT2701_I2S_NUM 4
#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
enum {
MT2701_I2S_1,
MT2701_I2S_2,
MT2701_I2S_3,
MT2701_I2S_4,
MT2701_I2S_NUM,
};
enum { enum {
MT2701_MEMIF_DL1, MT2701_MEMIF_DL1,
...@@ -62,60 +54,23 @@ enum { ...@@ -62,60 +54,23 @@ enum {
}; };
enum { enum {
MT2701_IRQ_ASYS_START, MT2701_IRQ_ASYS_IRQ1,
MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
MT2701_IRQ_ASYS_IRQ2, MT2701_IRQ_ASYS_IRQ2,
MT2701_IRQ_ASYS_IRQ3, MT2701_IRQ_ASYS_IRQ3,
MT2701_IRQ_ASYS_END, MT2701_IRQ_ASYS_END,
}; };
/* 2701 clock def */ enum audio_base_clock {
enum audio_system_clock_type { MT2701_INFRA_SYS_AUDIO,
MT2701_AUD_INFRA_SYS_AUDIO, MT2701_TOP_AUD_MCLK_SRC0,
MT2701_AUD_AUD_MUX1_SEL, MT2701_TOP_AUD_MCLK_SRC1,
MT2701_AUD_AUD_MUX2_SEL, MT2701_TOP_AUD_A1SYS,
MT2701_AUD_AUD_MUX1_DIV, MT2701_TOP_AUD_A2SYS,
MT2701_AUD_AUD_MUX2_DIV, MT2701_AUDSYS_AFE,
MT2701_AUD_AUD_48K_TIMING, MT2701_AUDSYS_AFE_CONN,
MT2701_AUD_AUD_44K_TIMING, MT2701_AUDSYS_A1SYS,
MT2701_AUD_AUDPLL_MUX_SEL, MT2701_AUDSYS_A2SYS,
MT2701_AUD_APLL_SEL, MT2701_BASE_CLK_NUM,
MT2701_AUD_AUD1PLL_98M,
MT2701_AUD_AUD2PLL_90M,
MT2701_AUD_HADDS2PLL_98M,
MT2701_AUD_HADDS2PLL_294M,
MT2701_AUD_AUDPLL,
MT2701_AUD_AUDPLL_D4,
MT2701_AUD_AUDPLL_D8,
MT2701_AUD_AUDPLL_D16,
MT2701_AUD_AUDPLL_D24,
MT2701_AUD_AUDINTBUS,
MT2701_AUD_CLK_26M,
MT2701_AUD_SYSPLL1_D4,
MT2701_AUD_AUD_K1_SRC_SEL,
MT2701_AUD_AUD_K2_SRC_SEL,
MT2701_AUD_AUD_K3_SRC_SEL,
MT2701_AUD_AUD_K4_SRC_SEL,
MT2701_AUD_AUD_K5_SRC_SEL,
MT2701_AUD_AUD_K6_SRC_SEL,
MT2701_AUD_AUD_K1_SRC_DIV,
MT2701_AUD_AUD_K2_SRC_DIV,
MT2701_AUD_AUD_K3_SRC_DIV,
MT2701_AUD_AUD_K4_SRC_DIV,
MT2701_AUD_AUD_K5_SRC_DIV,
MT2701_AUD_AUD_K6_SRC_DIV,
MT2701_AUD_AUD_I2S1_MCLK,
MT2701_AUD_AUD_I2S2_MCLK,
MT2701_AUD_AUD_I2S3_MCLK,
MT2701_AUD_AUD_I2S4_MCLK,
MT2701_AUD_AUD_I2S5_MCLK,
MT2701_AUD_AUD_I2S6_MCLK,
MT2701_AUD_ASM_M_SEL,
MT2701_AUD_ASM_H_SEL,
MT2701_AUD_UNIVPLL2_D4,
MT2701_AUD_UNIVPLL2_D2,
MT2701_AUD_SYSPLL_D5,
MT2701_CLOCK_NUM
}; };
static const unsigned int mt2701_afe_backup_list[] = { static const unsigned int mt2701_afe_backup_list[] = {
...@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = { ...@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = {
AFE_MEMIF_PBUF_SIZE, AFE_MEMIF_PBUF_SIZE,
}; };
struct snd_pcm_substream;
struct mtk_base_irq_data;
struct mt2701_i2s_data { struct mt2701_i2s_data {
int i2s_ctrl_reg; int i2s_ctrl_reg;
int i2s_pwn_shift;
int i2s_asrc_fs_shift; int i2s_asrc_fs_shift;
int i2s_asrc_fs_mask; int i2s_asrc_fs_mask;
}; };
...@@ -160,12 +111,18 @@ struct mt2701_i2s_path { ...@@ -160,12 +111,18 @@ struct mt2701_i2s_path {
int mclk_rate; int mclk_rate;
int on[I2S_DIR_NUM]; int on[I2S_DIR_NUM];
int occupied[I2S_DIR_NUM]; int occupied[I2S_DIR_NUM];
const struct mt2701_i2s_data *i2s_data[2]; const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
struct clk *hop_ck[I2S_DIR_NUM];
struct clk *sel_ck;
struct clk *div_ck;
struct clk *mclk_ck;
struct clk *asrco_ck;
}; };
struct mt2701_afe_private { struct mt2701_afe_private {
struct clk *clocks[MT2701_CLOCK_NUM];
struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
struct clk *base_ck[MT2701_BASE_CLK_NUM];
struct clk *mrgif_ck;
bool mrg_enable[MT2701_STREAM_DIR_NUM]; bool mrg_enable[MT2701_STREAM_DIR_NUM];
}; };
......
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
View file @ fab9298c
This diff is collapsed.
sound/soc/mediatek/mt2701/mt2701-reg.h
View file @ fab9298c
...@@ -17,17 +17,6 @@ ...@@ -17,17 +17,6 @@
#ifndef _MT2701_REG_H_ #ifndef _MT2701_REG_H_
#define _MT2701_REG_H_ #define _MT2701_REG_H_
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "mt2701-afe-common.h"
/*****************************************************************************
* R E G I S T E R D E F I N I T I O N
*****************************************************************************/
#define AUDIO_TOP_CON0 0x0000 #define AUDIO_TOP_CON0 0x0000
#define AUDIO_TOP_CON4 0x0010 #define AUDIO_TOP_CON4 0x0010
#define AUDIO_TOP_CON5 0x0014 #define AUDIO_TOP_CON5 0x0014
...@@ -109,18 +98,6 @@ ...@@ -109,18 +98,6 @@
#define AFE_DAI_BASE 0x1370 #define AFE_DAI_BASE 0x1370
#define AFE_DAI_CUR 0x137c #define AFE_DAI_CUR 0x137c
/* AUDIO_TOP_CON0 (0x0000) */
#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
/* AUDIO_TOP_CON4 (0x0010) */
#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
/* AFE_DAIBT_CON0 (0x001c) */ /* AFE_DAIBT_CON0 (0x001c) */
#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
...@@ -137,22 +114,8 @@ ...@@ -137,22 +114,8 @@
#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
/* ASYS_I2SO1_CON (0x061c) */ /* ASYS_TOP_CON (0x0600) */
#define ASYS_I2SO1_CON_FS (0x1f << 8) #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
/* 0:EIAJ 1:I2S */
#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
/* PWR2_TOP_CON (0x0634) */
#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
/* ASYS_IRQ_CLR (0x07c0) */
#define ASYS_IRQ_CLR_ALL (0xffffffff)
/* PWR2_ASM_CON1 (0x1070) */ /* PWR2_ASM_CON1 (0x1070) */
#define PWR2_ASM_CON1_INIT_VAL (0x492492) #define PWR2_ASM_CON1_INIT_VAL (0x492492)
...@@ -182,5 +145,4 @@ ...@@ -182,5 +145,4 @@
#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)
#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)
#define AFE_END_ADDR 0x15e0
#endif #endif
sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
View file @ fab9298c
...@@ -1083,7 +1083,7 @@ static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe) ...@@ -1083,7 +1083,7 @@ static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
{ {
int ret, i; int ret, i;
unsigned int irq_id; int irq_id;
struct mtk_base_afe *afe; struct mtk_base_afe *afe;
struct mt8173_afe_private *afe_priv; struct mt8173_afe_private *afe_priv;
struct resource *res; struct resource *res;
...@@ -1105,9 +1105,9 @@ static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1105,9 +1105,9 @@ static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
afe->dev = &pdev->dev; afe->dev = &pdev->dev;
irq_id = platform_get_irq(pdev, 0); irq_id = platform_get_irq(pdev, 0);
if (!irq_id) { if (irq_id <= 0) {
dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name); dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
return -ENXIO; return irq_id < 0 ? irq_id : -ENXIO;
} }
ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler, ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
0, "Afe_ISR_Handle", (void *)afe); 0, "Afe_ISR_Handle", (void *)afe);
......
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
View file @ fab9298c
...@@ -37,8 +37,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = { ...@@ -37,8 +37,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = {
{"Sub DMIC1R", NULL, "Int Mic"}, {"Sub DMIC1R", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"}, {"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"}, {"Headphone", NULL, "HPOR"},
{"Headset Mic", NULL, "micbias1"},
{"Headset Mic", NULL, "micbias2"},
{"IN1P", NULL, "Headset Mic"}, {"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"}, {"IN1N", NULL, "Headset Mic"},
}; };
......
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
View file @ fab9298c
...@@ -40,8 +40,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = { ...@@ -40,8 +40,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = {
{"Headphone", NULL, "HPOL"}, {"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"}, {"Headphone", NULL, "HPOR"},
{"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */ {"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */
{"Headset Mic", NULL, "micbias1"},
{"Headset Mic", NULL, "micbias2"},
{"IN1P", NULL, "Headset Mic"}, {"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"}, {"IN1N", NULL, "Headset Mic"},
{"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */ {"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */
......
sound/soc/mediatek/mt8173/mt8173-rt5650.c
View file @ fab9298c
...@@ -51,8 +51,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = { ...@@ -51,8 +51,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = {
{"DMIC R1", NULL, "Int Mic"}, {"DMIC R1", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"}, {"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"}, {"Headphone", NULL, "HPOR"},
{"Headset Mic", NULL, "micbias1"},
{"Headset Mic", NULL, "micbias2"},
{"IN1P", NULL, "Headset Mic"}, {"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"}, {"IN1N", NULL, "Headset Mic"},
}; };
......
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